SPRSP45C March   2020  – April 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
        1. 5.4.1.1 GPIO Muxed Pins Table
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 GPIO Input X-BAR
      4. 5.4.4 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5.     Supply Voltages
    6. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption
      2. 6.5.2 Operating Mode Test Description
      3. 6.5.3 Current Consumption Graphs
      4. 6.5.4 Reducing Current Consumption
        1. 6.5.4.1 Typical Current Reduction per Disabled Peripheral
    7. 6.6  Electrical Characteristics
    8. 6.7  Thermal Resistance Characteristics for PN Package
    9. 6.8  Thermal Resistance Characteristics for PM Package
    10. 6.9  Thermal Resistance Characteristics for PT Package
    11. 6.10 Thermal Design Considerations
    12. 6.11 System
      1. 6.11.1  Power Management Module (PMM)
        1. 6.11.1.1 Introduction
        2. 6.11.1.2 Overview
          1. 6.11.1.2.1 Power Rail Monitors
            1. 6.11.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.11.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.11.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.11.1.2.2 External Supervisor Usage
          3. 6.11.1.2.3 Delay Blocks
          4. 6.11.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
        3. 6.11.1.3 External Components
          1. 6.11.1.3.1 Decoupling Capacitors
            1. 6.11.1.3.1.1 VDDIO Decoupling
            2. 6.11.1.3.1.2 VDD Decoupling
        4. 6.11.1.4 Power Sequencing
          1. 6.11.1.4.1 Supply Pins Ganging
          2. 6.11.1.4.2 Signal Pins Power Sequence
          3. 6.11.1.4.3 Supply Pins Power Sequence
            1. 6.11.1.4.3.1 Internal VREG/VDD Mode Sequence
            2. 6.11.1.4.3.2 Supply Sequencing Summary and Effects of Violations
            3. 6.11.1.4.3.3 Supply Slew Rate
        5. 6.11.1.5 Power Management Module Electrical Data and Timing
          1. 6.11.1.5.1 Power Management Module Characteristics
          2. 6.11.1.5.2 Power Management Module Operating Conditions
      2. 6.11.2  Reset Timing
        1. 6.11.2.1 Reset Sources
        2. 6.11.2.2 Reset Electrical Data and Timing
          1. 6.11.2.2.1 Reset (XRSn) Timing Requirements
          2. 6.11.2.2.2 Reset (XRSn) Switching Characteristics
          3. 6.11.2.2.3 Reset Timing Diagrams
      3. 6.11.3  Clock Specifications
        1. 6.11.3.1 Clock Sources
        2. 6.11.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.11.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.11.3.2.1.1 Input Clock Frequency
            2. 6.11.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.11.3.2.1.3 X1 Timing Requirements
            4. 6.11.3.2.1.4 APLL Characteristics
            5. 6.11.3.2.1.5 XCLKOUT Switching Characteristics
            6. 6.11.3.2.1.6 Internal Clock Frequencies
        3. 6.11.3.3 Input Clocks and PLLs
        4. 6.11.3.4 XTAL Oscillator
          1. 6.11.3.4.1 Introduction
          2. 6.11.3.4.2 Overview
            1. 6.11.3.4.2.1 Electrical Oscillator
              1. 6.11.3.4.2.1.1 Modes of Operation
                1. 6.11.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.11.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.11.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.11.3.4.2.2 Quartz Crystal
            3. 6.11.3.4.2.3 GPIO Modes of Operation
          3. 6.11.3.4.3 Functional Operation
            1. 6.11.3.4.3.1 ESR – Effective Series Resistance
            2. 6.11.3.4.3.2 Rneg – Negative Resistance
            3. 6.11.3.4.3.3 Start-up Time
            4. 6.11.3.4.3.4 DL – Drive Level
          4. 6.11.3.4.4 How to Choose a Crystal
          5. 6.11.3.4.5 Testing
          6. 6.11.3.4.6 Common Problems and Debug Tips
          7. 6.11.3.4.7 Crystal Oscillator Specifications
            1. 6.11.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.11.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
        5. 6.11.3.5 Internal Oscillators
          1. 6.11.3.5.1 INTOSC Characteristics
      4. 6.11.4  Flash Parameters
      5. 6.11.5  RAM Specifications
      6. 6.11.6  ROM Specifications
      7. 6.11.7  Emulation/JTAG
        1. 6.11.7.1 JTAG Electrical Data and Timing
          1. 6.11.7.1.1 JTAG Timing Requirements
          2. 6.11.7.1.2 JTAG Switching Characteristics
          3. 6.11.7.1.3 JTAG Timing Diagram
        2. 6.11.7.2 cJTAG Electrical Data and Timing
          1. 6.11.7.2.1 cJTAG Timing Requirements
          2. 6.11.7.2.2 cJTAG Switching Characteristics
          3. 6.11.7.2.3 cJTAG Timing Diagram
      8. 6.11.8  GPIO Electrical Data and Timing
        1. 6.11.8.1 GPIO – Output Timing
          1. 6.11.8.1.1 General-Purpose Output Switching Characteristics
        2. 6.11.8.2 GPIO – Input Timing
          1. 6.11.8.2.1 General-Purpose Input Timing Requirements
          2. 6.11.8.2.2 Sampling Mode
        3. 6.11.8.3 Sampling Window Width for Input Signals
      9. 6.11.9  Interrupts
        1. 6.11.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.11.9.1.1 External Interrupt Timing Requirements
          2. 6.11.9.1.2 External Interrupt Switching Characteristics
          3. 6.11.9.1.3 External Interrupt Timing
      10. 6.11.10 Low-Power Modes
        1. 6.11.10.1 Clock-Gating Low-Power Modes
        2. 6.11.10.2 Low-Power Mode Wake-up Timing
          1. 6.11.10.2.1 IDLE Mode Timing Requirements
          2. 6.11.10.2.2 IDLE Mode Switching Characteristics
          3. 6.11.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.11.10.2.4 STANDBY Mode Timing Requirements
          5. 6.11.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.11.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.11.10.2.7 HALT Mode Timing Requirements
          8. 6.11.10.2.8 HALT Mode Switching Characteristics
          9. 6.11.10.2.9 HALT Entry and Exit Timing Diagram
    13. 6.12 Analog Peripherals
      1. 6.12.1 Analog Pins and Internal Connections
      2. 6.12.2 Analog Signal Descriptions
      3. 6.12.3 Analog-to-Digital Converter (ADC)
        1. 6.12.3.1 ADC Configurability
          1. 6.12.3.1.1 Signal Mode
        2. 6.12.3.2 ADC Electrical Data and Timing
          1. 6.12.3.2.1 ADC Operating Conditions
          2. 6.12.3.2.2 ADC Characteristics
          3. 6.12.3.2.3 ADC INL and DNL
          4. 6.12.3.2.4 ADC Input Model
          5. 6.12.3.2.5 ADC Timing Diagrams
      4. 6.12.4 Temperature Sensor
        1. 6.12.4.1 Temperature Sensor Electrical Data and Timing
          1. 6.12.4.1.1 Temperature Sensor Characteristics
      5. 6.12.5 Comparator Subsystem (CMPSS)
        1. 6.12.5.1 CMPSS Electrical Data and Timing
          1. 6.12.5.1.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.12.5.1.2 CMPSS DAC Static Electrical Characteristics
          4. 6.12.5.1.3 CMPSS Illustrative Graphs
    14. 6.13 Control Peripherals
      1. 6.13.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.13.1.1 Control Peripherals Synchronization
        2. 6.13.1.2 ePWM Electrical Data and Timing
          1. 6.13.1.2.1 ePWM Timing Requirements
          2. 6.13.1.2.2 ePWM Switching Characteristics
          3. 6.13.1.2.3 Trip-Zone Input Timing
            1. 6.13.1.2.3.1 Trip-Zone Input Timing Requirements
        3. 6.13.1.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 6.13.1.3.1 External ADC Start-of-Conversion Switching Characteristics
      2. 6.13.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.13.2.1 HRPWM Electrical Data and Timing
          1. 6.13.2.1.1 High-Resolution PWM Characteristics
      3. 6.13.3 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
        1. 6.13.3.1 High-Resolution Capture (HRCAP)
        2. 6.13.3.2 eCAP and HRCAP Block Diagram
        3. 6.13.3.3 eCAP/HRCAP Synchronization
        4. 6.13.3.4 eCAP Electrical Data and Timing
          1. 6.13.3.4.1 eCAP Timing Requirements
          2. 6.13.3.4.2 eCAP Switching Characteristics
        5. 6.13.3.5 HRCAP Electrical Data and Timing
          1. 6.13.3.5.1 HRCAP Switching Characteristics
          2. 6.13.3.5.2 HRCAP Figure and Graph
      4. 6.13.4 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.13.4.1 eQEP Electrical Data and Timing
          1. 6.13.4.1.1 eQEP Timing Requirements
          2. 6.13.4.1.2 eQEP Switching Characteristics
    15. 6.14 Communications Peripherals
      1. 6.14.1 Controller Area Network (CAN)
      2. 6.14.2 Inter-Integrated Circuit (I2C)
        1. 6.14.2.1 I2C Electrical Data and Timing
          1. 6.14.2.1.1 I2C Timing Requirements
          2. 6.14.2.1.2 I2C Switching Characteristics
          3. 6.14.2.1.3 I2C Timing Diagram
      3. 6.14.3 Power Management Bus (PMBus) Interface
        1. 6.14.3.1 PMBus Electrical Data and Timing
          1. 6.14.3.1.1 PMBus Electrical Characteristics
          2. 6.14.3.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.14.3.1.3 PMBus Standard Mode Switching Characteristics
      4. 6.14.4 Serial Communications Interface (SCI)
      5. 6.14.5 Serial Peripheral Interface (SPI)
        1. 6.14.5.1 SPI Master Mode Timings
          1. 6.14.5.1.1 SPI Master Mode Timing Requirements
          2. 6.14.5.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
          3. 6.14.5.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
          4. 6.14.5.1.4 SPI Master Mode Timing Diagrams
        2. 6.14.5.2 SPI Slave Mode Timings
          1. 6.14.5.2.1 SPI Slave Mode Timing Requirements
          2. 6.14.5.2.2 SPI Slave Mode Switching Characteristics
          3. 6.14.5.2.3 SPI Slave Mode Timing Diagrams
      6. 6.14.6 Local Interconnect Network (LIN)
      7. 6.14.7 Fast Serial Interface (FSI)
        1. 6.14.7.1 FSI Transmitter
          1. 6.14.7.1.1 FSITX Electrical Data and Timing
            1. 6.14.7.1.1.1 FSITX Switching Characteristics
            2. 6.14.7.1.1.2 FSITX Timings
        2. 6.14.7.2 FSI Receiver
          1. 6.14.7.2.1 FSIRX Electrical Data and Timing
            1. 6.14.7.2.1.1 FSIRX Timing Requirements
            2. 6.14.7.2.1.2 FSIRX Switching Characteristics
            3. 6.14.7.2.1.3 FSIRX Timings
        3. 6.14.7.3 FSI SPI Compatibility Mode
          1. 6.14.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.14.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.14.7.3.1.2 FSITX SPI Signaling Mode Timings
      8. 6.14.8 Host Interface Controller (HIC)
        1. 6.14.8.1 HIC Electrical Data and Timing
          1. 6.14.8.1.1 HIC Timing Requirements
          2. 6.14.8.1.2 HIC Switching Characteristics
          3. 6.14.8.1.3 HIC Timing Diagrams
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
        3. 7.3.1.3 Global Shared RAM (GSx RAM)
      2. 7.3.2 Flash Memory Map
        1. 7.3.2.1 Addresses of Flash Sectors
      3. 7.3.3 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit (FPU)
      2. 7.6.2 Fast Integer Division Unit
      3. 7.6.3 Trigonometric Math Unit (TMU)
      4. 7.6.4 VCRC Unit
    7. 7.7  Embedded Real-Time Analysis and Diagnostic (ERAD)
    8. 7.8  Background CRC-32 (BGCRC)
    9. 7.9  Direct Memory Access (DMA)
    10. 7.10 Device Boot Modes
      1. 7.10.1 Device Boot Configurations
        1. 7.10.1.1 Configuring Boot Mode Pins
        2. 7.10.1.2 Configuring Boot Mode Table Options
      2. 7.10.2 GPIO Assignments
    11. 7.11 Dual Code Security Module
    12. 7.12 Watchdog
    13. 7.13 C28x Timers
    14. 7.14 Dual-Clock Comparator (DCC)
      1. 7.14.1 Features
      2. 7.14.2 Mapping of DCCx (DCC0 and DCC1) Clock Source Inputs
    15. 7.15 Configurable Logic Block (CLB)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Key Device Features
    2. 8.2 Application Information
      1. 8.2.1 Typical Application
        1. 8.2.1.1 Servo Drive Control Module
          1. 8.2.1.1.1 System Block Diagram
          2. 8.2.1.1.2 Servo Drive Control Module Resources
        2. 8.2.1.2 Server or Telecom Power Supply Unit (PSU)
          1. 8.2.1.2.1 System Block Diagram
          2. 8.2.1.2.2 Server and Telecom PSU Resources
        3. 8.2.1.3 Merchant Telecom Rectifiers
          1. 8.2.1.3.1 System Block Diagram
          2. 8.2.1.3.2 Merchant Telecom Rectifiers Resources
        4. 8.2.1.4 EV Charging Station Power Module
          1. 8.2.1.4.1 System Block Diagram
          2. 8.2.1.4.2 EV Charging Station Power Module Resources
        5. 8.2.1.5 Air-conditioner Outdoor Unit
          1. 8.2.1.5.1 System Block Diagram
          2. 8.2.1.5.2 Air Conditioner Outdoor Unit Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device and Development Support Tool Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Key Device Features

Table 8-1 Key Device Features
MODULE FEATURE SYSTEM BENEFIT
PROCESSING
Real-time control CPUs

Up to 200 MIPS

C28x: 100 MIPS

CLA: 100 MIPS

Flash: Up to 256KB

RAM : Up to 100KB

32-bit Floating-Point Unit (FPU32)

Trigonometric Math Unit (TMU)

Vertibi Complex Math Unit (VCU)

TI’s 32-bit C28x DSP core, provides 100 MHz of signal-processing performance for floating- or fixed-point code running from either on-chip flash or SRAM

Provides 100 MHz of signal-processing performance for floating- or fixed-point code running from either on-chip flash or SRAM.

FPU32: Native hardware support for IEEE-754 single-precision floating-point operations

TMU: Accelerators used to speed up execution of trigonometric and arithmetic operations for faster computation (such as PLL and DQ transform) optimized for control applications. Helps in achieving faster control loops, resulting in higher efficiency and better component sizing.

Special instructions to support nonlinear PID control algorithms

VCU: Reduces the latency for complex math operations commonly found in encoded applications

Real-time Benchmarks Showcasing C2000™ControlMCU's Optimized Signal Chain
SENSING
Analog-to-Digital Converter (ADC) (12-bit)

Up to 3 ADC modules

3.45 MSPS

Up to 21 channels

ADC provides precise and concurrent sampling of all three-phase currents and DC bus with zero jitter.

ADC post-processing – On-chip hardware reduces ADC ISR complexity and shortens current loop cycles.

More ADCs help in multiphase applications. Provide better effective MSPS (oversampling) and typical ENOB for better control-loop performance.

Comparator Subsystem (CMPSS) CMPSS

2 windowed comparator

Dual 12-bit DACs

DAC ramp generation

Low DAC output on external pin

Digital filters

60-ns detection to trip time

Slope compensation

System protection without false alarms:

Comparator Subsystem (CMPSS) modules are useful for applications such as peak-current mode control, switched-mode power, power factor correction, and voltage trip monitoring.

PWM trip-triggering and removal of unwanted noise are easy with blanking window and filtering features provided with the analog comparator subsystems.

Provides better control accuracy. No need for further CPU configuration to control the PWM with the comparator and 12-bit DAC (CMPSS).

Enables protection and control using the same pin.
Enhanced Quadrature Encoder Pulse (eQEP) 2 eQEP modules Used for direct interface with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine used in a high-performance motion and position-control system. Also can be used in other applications to count input pulses from an external device (such as a sensor).
Enhanced Capture (eCAP) / High Resolution Enhanced Capture (HRCAP)

7 eCAP modules (2 with HRCAP capability)

Measures elapsed time between events (up to 4 time-stamped events).

Connects to any GPIO through the input X-BAR.

When not used in capture mode, the eCAP module can be configured as a single-channel PWM output (APWM).

Applications for eCAP include:

Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall sensors)

Elapsed time measurements between position sensor pulses

Period and duty cycle measurements of pulse train signals

Decoding current or voltage amplitude derived from duty-cycle encoded current/voltage sensors

2 HRCAP channels

Provides the capability to measure the width of external pulses with a typical resolution of 300 ps.

Applications for HRCAP include:

High-resolution period and duty-cycle measurements of pulse train cycles

Instantaneous speed measurements

Instantaneous frequency measurements

Voltage measurements across an isolation boundary

Distance/sonar measurement and scanning

Flow measurements

Capacitive touch applications
ACTUATION
Enhanced Pulse Width Modulation (ePWM) / High-Resolution Pulse Width Modulation (HRPWM)

Up to 16 ePWM channels

Ability to generate high-side/low-side PWMs with deadband

Supports Valley switching (ability to switch PWM output at valley point) and features like blanking window

Flexible PWM waveform generation with best power topology coverage.

Shadowed deadband and shadowed action qualifier enable adaptive PWM generation and protection for improved control accuracy and reduced power loss.

Enables improvement in Power Factor (PF) and Total Harmonic Distortion (THD), which is especially relevant in Power Factor Correction (PFC) applications. Improves light load efficiency.

HRPWM capability:

All the 16 channels provide high-resolution capability (150 ps)

Provides 150-ps steps for duty cycle, period, deadband, and phase offsets for 99% greater precision

Beneficial for accurate control and enables better-performance high-frequency power conversion.

Achieves cleaner waveforms and avoids oscillations/limit cycle at output.

One-shot and global reload feature

Critical for variable-frequency and multiphase DC-DC applications and helps in attaining high-frequency control loops (>2 MHz).

Enables control of interleaved LLC topologies at high frequencies

Independent PWM action on a Cycle-by-Cycle (CBC) trip event and an One-Shot Trip (OST) trip event

 Provides cycle-by-cycle protection and complete shutoff of PWM under fault condition. Helps implement multiphase PFC or DC-DC control.
Load on SYNC (support for shadow-to-active load on a SYNC event) Enables variable-frequency applications (allows LLC control in power conversion).
Ability to shut down the PWMs without software intervention (no ISR latency) Fast protection under fault condition
Delayed Trip Functionality Helps implement the deadband with Peak Current Mode Control (PCMC) Phase- Shifted Full Bride (PSFB) DC-DC easily without occupying much CPU resources (even on trigger events based on comparator, trip, or sync-in events).
Deadband Generator (DB) submodule Prevents simultaneous ON conditions of High and Low side gates by adding programmable delay to rising (RED) and falling (FED) PWM signal edges.
Flexible PWM Phase Relationships and Timer Synchronization Each ePWM module can be synchronized with other ePWM modules or other peripherals. Keeps PWM edges in synchronization with each other or with certain events.

Supports flexible ADC scheduling with specific sampling window in synchronization with power device switching.
CONNECTIVITY
Serial Peripheral Interface (SPI) 2 high-speed SPI port Supports 25 MHz
Serial Communication Interface (SCI) 2 SCI (UART) modules Interfaces with controllers
Local Interconnect Network (LIN) 1 LIN Provides a low-cost solution where the bandwidth and fault tolerance of a Controller Area Network (CAN) are not required.

Can also be used as SCI to communication with other controllers.
Controller Area Network (CAN/DCAN) 1 DCAN module Provides compatibility with classic CAN modules
Inter-Integrated Circuit (I2C) 1 I2C modules Interfaces with external EEPROMs, sensors, or controllers
Power-Management Bus (PMBus)

1 PMBus module

Compliance with the SMI Forum PMBus Specification (Part I v1.0 and Part II v1.1)

 Seamless HW-based host communication
Fast Serial Interface (FSI) with a transmitter and receiver

Up to 1 FSI transmitters and 1 FSI receivers

Serial communication peripheral capable of reliable high-speed

communication (up to 100 MHz) across isolation devices

 Fast serial interface (FSI) can be useful for low-pin count, high-speed communication even across isolation boundary at up to 100Mbps.
OTHER SYSTEM FEATURES
Security enhancers

Dual-zone Code Security Module (DCSM)

Watchdog

Write Protection on Register

Missing Clock Detection Logic (MCD)

Error Correction Code (ECC) and parity

DCSM: Prevents duplication and reverse-engineering of proprietary code

Watchdog: Generates reset if CPU gets stuck in endless loops of execution

Write Protection on Registers:

LOCK protection on system configuration registers

Protection against spurious CPU writes

MCD: Automatic clock failure detection

ECC and parity: Single-bit error correction and double-bit error detection
Crossbars (XBARs)

Provides flexibility to connect device inputs, outputs, and internal resources in a variety of configurations.

• Input X-BAR

• Output X-BAR

• ePWM X-BAR

• CLB X-BAR

Enhances hardware design versatility:

Input X-BAR: Routes signals from any GPIO to multiple IP blocks within the chip

Output XBAR: Routes internal signals onto designated GPIO pins

ePWM X-BAR: Routes internal signals from various IP blocks to EPWM

CLB X-BAR: Allows user to bring signals from various IP blocks to CLB