SPRSP61C October   2021  – December 2023 TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038C-Q1 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
        1. 5.4.1.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption
      2. 6.5.2 System Current Consumption - VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Current Consumption Graphs
      5. 6.5.5 Reducing Current Consumption
        1. 6.5.5.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics for PZ Package
    8. 6.8  Thermal Resistance Characteristics for PN Package
    9. 6.9  Thermal Resistance Characteristics for PM Package
    10. 6.10 Thermal Resistance Characteristics for PT Package
    11. 6.11 Thermal Design Considerations
    12. 6.12 System
      1. 6.12.1 Power Management Module (PMM)
        1. 6.12.1.1 Introduction
        2. 6.12.1.2 Overview
          1. 6.12.1.2.1 Power Rail Monitors
            1. 6.12.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.12.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.12.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.12.1.2.2 External Supervisor Usage
          3. 6.12.1.2.3 Delay Blocks
          4. 6.12.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.12.1.2.5 VREGENZ
        3. 6.12.1.3 External Components
          1. 6.12.1.3.1 Decoupling Capacitors
            1. 6.12.1.3.1.1 VDDIO Decoupling
            2. 6.12.1.3.1.2 VDD Decoupling
        4. 6.12.1.4 Power Sequencing
          1. 6.12.1.4.1 Supply Pins Ganging
          2. 6.12.1.4.2 Signal Pins Power Sequence
          3. 6.12.1.4.3 Supply Pins Power Sequence
            1. 6.12.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.12.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.12.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.12.1.4.3.4 Supply Slew Rate
        5. 6.12.1.5 Power Management Module Electrical Data and Timing
          1. 6.12.1.5.1 Power Management Module Operating Conditions
          2. 6.12.1.5.2 Power Management Module Characteristics
          3.        Supply Voltages
      2. 6.12.2 Reset Timing
        1. 6.12.2.1 Reset Sources
        2. 6.12.2.2 Reset Electrical Data and Timing
          1. 6.12.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.12.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.12.2.2.3 Reset Timing Diagrams
      3. 6.12.3 Clock Specifications
        1. 6.12.3.1 Clock Sources
        2. 6.12.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.12.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.12.3.2.1.1 Input Clock Frequency
            2. 6.12.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.12.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.12.3.2.1.4 X1 Timing Requirements
            5. 6.12.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.12.3.2.1.6 APLL Characteristics
            7. 6.12.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.12.3.2.1.8 Internal Clock Frequencies
        3. 6.12.3.3 Input Clocks and PLLs
        4. 6.12.3.4 XTAL Oscillator
          1. 6.12.3.4.1 Introduction
          2. 6.12.3.4.2 Overview
            1. 6.12.3.4.2.1 Electrical Oscillator
              1. 6.12.3.4.2.1.1 Modes of Operation
                1. 6.12.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.12.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.12.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.12.3.4.2.2 Quartz Crystal
            3. 6.12.3.4.2.3 GPIO Modes of Operation
          3. 6.12.3.4.3 Functional Operation
            1. 6.12.3.4.3.1 ESR – Effective Series Resistance
            2. 6.12.3.4.3.2 Rneg – Negative Resistance
            3. 6.12.3.4.3.3 Start-up Time
              1. 6.12.3.4.3.3.1 X1/X2 Precondition
            4. 6.12.3.4.3.4 DL – Drive Level
          4. 6.12.3.4.4 How to Choose a Crystal
          5. 6.12.3.4.5 Testing
          6. 6.12.3.4.6 Common Problems and Debug Tips
          7. 6.12.3.4.7 Crystal Oscillator Specifications
            1. 6.12.3.4.7.1 Crystal Oscillator Parameters
            2. 6.12.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.12.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.12.3.5 Internal Oscillators
          1. 6.12.3.5.1 INTOSC Characteristics
      4. 6.12.4 Flash Parameters
        1. 6.12.4.1 Flash Parameters 
      5. 6.12.5 RAM and ROM Parameters
      6. 6.12.6 Emulation/JTAG
        1. 6.12.6.1 JTAG Electrical Data and Timing
          1. 6.12.6.1.1 JTAG Timing Requirements
          2. 6.12.6.1.2 JTAG Switching Characteristics
          3. 6.12.6.1.3 JTAG Timing Diagram
        2. 6.12.6.2 cJTAG Electrical Data and Timing
          1. 6.12.6.2.1 cJTAG Timing Requirements
          2. 6.12.6.2.2 cJTAG Switching Characteristics
          3. 6.12.6.2.3 cJTAG Timing Diagram
      7. 6.12.7 GPIO Electrical Data and Timing
        1. 6.12.7.1 GPIO – Output Timing
          1. 6.12.7.1.1 General-Purpose Output Switching Characteristics
          2. 6.12.7.1.2 General-Purpose Output Timing Diagram
        2. 6.12.7.2 GPIO – Input Timing
          1. 6.12.7.2.1 General-Purpose Input Timing Requirements
          2. 6.12.7.2.2 Sampling Mode
        3. 6.12.7.3 Sampling Window Width for Input Signals
      8. 6.12.8 Interrupts
        1. 6.12.8.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.12.8.1.1 External Interrupt Timing Requirements
          2. 6.12.8.1.2 External Interrupt Switching Characteristics
          3. 6.12.8.1.3 External Interrupt Timing
      9. 6.12.9 Low-Power Modes
        1. 6.12.9.1 Clock-Gating Low-Power Modes
        2. 6.12.9.2 Low-Power Mode Wake-up Timing
          1. 6.12.9.2.1 IDLE Mode Timing Requirements
          2. 6.12.9.2.2 IDLE Mode Switching Characteristics
          3. 6.12.9.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.12.9.2.4 STANDBY Mode Timing Requirements
          5. 6.12.9.2.5 STANDBY Mode Switching Characteristics
          6. 6.12.9.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.12.9.2.7 HALT Mode Timing Requirements
          8. 6.12.9.2.8 HALT Mode Switching Characteristics
          9. 6.12.9.2.9 HALT Entry and Exit Timing Diagram
    13. 6.13 Analog Peripherals
      1. 6.13.1 Analog Pins and Internal Connections
      2. 6.13.2 Analog Signal Descriptions
      3. 6.13.3 Analog-to-Digital Converter (ADC)
        1. 6.13.3.1 ADC Configurability
          1. 6.13.3.1.1 Signal Mode
        2. 6.13.3.2 ADC Electrical Data and Timing
          1. 6.13.3.2.1 ADC Operating Conditions
          2. 6.13.3.2.2 ADC Characteristics
          3. 6.13.3.2.3 ADC Input Model
          4. 6.13.3.2.4 ADC Timing Diagrams
      4. 6.13.4 Temperature Sensor
        1. 6.13.4.1 Temperature Sensor Electrical Data and Timing
          1. 6.13.4.1.1 Temperature Sensor Characteristics
      5. 6.13.5 Comparator Subsystem (CMPSS)
        1. 6.13.5.1 CMPSS Connectivity Diagram
        2. 6.13.5.2 Block Diagram
        3. 6.13.5.3 CMPSS Electrical Data and Timing
          1. 6.13.5.3.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.13.5.3.2 CMPSS DAC Static Electrical Characteristics
          4. 6.13.5.3.3 CMPSS Illustrative Graphs
          5. 6.13.5.3.4 CMPSS DAC Dynamic Error
      6. 6.13.6 Buffered Digital-to-Analog Converter (DAC)
        1. 6.13.6.1 Buffered DAC Electrical Data and Timing
          1. 6.13.6.1.1 Buffered DAC Operating Conditions
          2. 6.13.6.1.2 Buffered DAC Electrical Characteristics
    14. 6.14 Control Peripherals
      1. 6.14.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.14.1.1 ePWM Electrical Data and Timing
          1. 6.14.1.1.1 ePWM Timing Requirements
          2. 6.14.1.1.2 ePWM Switching Characteristics
          3. 6.14.1.1.3 Trip-Zone Input Timing
            1. 6.14.1.1.3.1 Trip-Zone Input Timing Requirements
            2. 6.14.1.1.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.14.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.14.2.1 HRPWM Electrical Data and Timing
          1. 6.14.2.1.1 High-Resolution PWM Characteristics
      3. 6.14.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.14.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.14.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.14.4 Enhanced Capture (eCAP)
        1. 6.14.4.1 eCAP and HRCAP Block Diagram
        2. 6.14.4.2 eCAP Synchronization
        3. 6.14.4.3 eCAP Electrical Data and Timing
          1. 6.14.4.3.1 eCAP Timing Requirements
          2. 6.14.4.3.2 eCAP Switching Characteristics
      5. 6.14.5 High-Resolution Capture (HRCAP)
        1. 6.14.5.1 eCAP and HRCAP Block Diagram
        2. 6.14.5.2 HRCAP Electrical Data and Timing
          1. 6.14.5.2.1 HRCAP Switching Characteristics
          2. 6.14.5.2.2 HRCAP Figure and Graph
      6. 6.14.6 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.14.6.1 eQEP Electrical Data and Timing
          1. 6.14.6.1.1 eQEP Timing Requirements
          2. 6.14.6.1.2 eQEP Switching Characteristics
      7. 6.14.7 Sigma-Delta Filter Module (SDFM)
        1. 6.14.7.1 SDFM Electrical Data and Timing
          1. 6.14.7.1.1 SDFM Timing Requirements When Using Asynchronous GPIO - ASYNC - Option
    15. 6.15 Communications Peripherals
      1. 6.15.1 Controller Area Network (CAN)
      2. 6.15.2 Modular Controller Area Network (MCAN)
      3. 6.15.3 Inter-Integrated Circuit (I2C)
        1. 6.15.3.1 I2C Electrical Data and Timing
          1. 6.15.3.1.1 I2C Timing Requirements
          2. 6.15.3.1.2 I2C Switching Characteristics
          3. 6.15.3.1.3 I2C Timing Diagram
      4. 6.15.4 Power Management Bus (PMBus) Interface
        1. 6.15.4.1 PMBus Electrical Data and Timing
          1. 6.15.4.1.1 PMBus Electrical Characteristics
          2. 6.15.4.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.15.4.1.3 PMBus Standard Mode Switching Characteristics
      5. 6.15.5 Serial Communications Interface (SCI)
      6. 6.15.6 Serial Peripheral Interface (SPI)
        1. 6.15.6.1 SPI Master Mode Timings
          1. 6.15.6.1.1 SPI Master Mode Timing Requirements
          2. 6.15.6.1.2 SPI Master Mode Switching Characteristics - Clock Phase  0
          3. 6.15.6.1.3 SPI Master Mode Switching Characteristics - Clock Phase  1
          4. 6.15.6.1.4 SPI Master Mode Timing Diagrams
        2. 6.15.6.2 SPI Slave Mode Timings
          1. 6.15.6.2.1 SPI Slave Mode Timing Requirements
          2. 6.15.6.2.2 SPI Slave Mode Switching Characteristics
          3. 6.15.6.2.3 SPI Slave Mode Timing Diagrams
      7. 6.15.7 Local Interconnect Network (LIN)
      8. 6.15.8 Fast Serial Interface (FSI)
        1. 6.15.8.1 FSI Transmitter
          1. 6.15.8.1.1 FSITX Electrical Data and Timing
            1. 6.15.8.1.1.1 FSITX Switching Characteristics
            2. 6.15.8.1.1.2 FSITX Timings
        2. 6.15.8.2 FSI Receiver
          1. 6.15.8.2.1 FSIRX Electrical Data and Timing
            1. 6.15.8.2.1.1 FSIRX Timing Requirements
            2. 6.15.8.2.1.2 FSIRX Switching Characteristics
            3. 6.15.8.2.1.3 FSIRX Timings
        3. 6.15.8.3 FSI SPI Compatibility Mode
          1. 6.15.8.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.15.8.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.15.8.3.1.2 FSITX SPI Signaling Mode Timings
      9. 6.15.9 Host Interface Controller (HIC)
        1. 6.15.9.1 HIC Electrical Data and Timing
          1. 6.15.9.1.1 HIC Timing Requirements
          2. 6.15.9.1.2 HIC Switching Characteristics
          3. 6.15.9.1.3 HIC Timing Diagrams
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
        3. 7.3.1.3 Global Shared RAM (GSx RAM)
        4. 7.3.1.4 Message RAM
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit (FPU)
      2. 7.6.2 Fast Integer Division Unit
      3. 7.6.3 Trigonometric Math Unit (TMU)
      4. 7.6.4 VCRC Unit
    7. 7.7  Control Law Accelerator (CLA)
    8. 7.8  Embedded Real-Time Analysis and Diagnostic (ERAD)
    9. 7.9  Background CRC-32 (BGCRC)
    10. 7.10 Direct Memory Access (DMA)
    11. 7.11 Device Boot Modes
      1. 7.11.1 Device Boot Configurations
        1. 7.11.1.1 Configuring Boot Mode Pins
        2. 7.11.1.2 Configuring Boot Mode Table Options
      2. 7.11.2 GPIO Assignments
    12. 7.12 Security
      1. 7.12.1 Securing the Boundary of the Chip
        1. 7.12.1.1 JTAGLOCK
        2. 7.12.1.2 Zero-pin Boot
      2. 7.12.2 Dual-Zone Security
      3. 7.12.3 Disclaimer
    13. 7.13 Watchdog
    14. 7.14 C28x Timers
    15. 7.15 Dual-Clock Comparator (DCC)
      1. 7.15.1 Features
      2. 7.15.2 Mapping of DCCx Clock Source Inputs
    16. 7.16 Configurable Logic Block (CLB)
    17. 7.17 Functional Safety
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Applications and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 Automotive Pump
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Automotive Pump Resources
        2. 8.3.1.2 Automotive HVAC Compressor
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 HVAC Resources
        3. 8.3.1.3 On-Board Charger (OBC)
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 OBC Resources
        4. 8.3.1.4 Servo Drive Control Module
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 Servo Drive Control Module Resources
        5. 8.3.1.5 Solar Micro Inverter
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 Solar Micro Inverter Resources
        6. 8.3.1.6 Merchant Telecom Rectifiers
          1. 8.3.1.6.1 System Block Diagram
          2. 8.3.1.6.2 Merchant Telecom Rectifiers Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.2 Pin Attributes

Table 5-1 Pin Attributes
SIGNAL NAME MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION
ANALOG
A0 23 19 15 15 11 I ADC-A Input 0
B15 I ADC-B Input 15
C15 I ADC-C Input 15
CMP3_HP2 I CMPSS-3 High Comparator Positive Input 2
CMP3_LP2 I CMPSS-3 Low Comparator Positive Input 2
DACA_OUT O Buffered DAC-A Output.
AIO231 0, 4, 8, 12 I Analog Pin Used For Digital Input 231 This pin also has digital mux functions which are described in the GPIO section of this table.
A1 22 18 14 14 10 I ADC-A Input 1
B7 I ADC-B Input 7
CMP1_HP4 I CMPSS-1 High Comparator Positive Input 4
CMP1_LP4 I CMPSS-1 Low Comparator Positive Input 4
DACB_OUT O Buffered DAC-B Output.
AIO232 0, 4, 8, 12 I Analog Pin Used For Digital Input 232 This pin also has digital mux functions which are described in the GPIO section of this table.
A2 17 13 9 9 6 I ADC-A Input 2
B6 I ADC-B Input 6
C9 I ADC-C Input 9
CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0
CMP1_LP0 I CMPSS-1 Low Comparator Positive Input 0
AIO224 0, 4, 8, 12 I Analog Pin Used For Digital Input 224 This pin also has digital mux functions which are described in the GPIO section of this table.
A3 18 I ADC-A Input 3
CMP3_HP5 I CMPSS-3 High Comparator Positive Input 5
CMP3_LP5 I CMPSS-3 Low Comparator Positive Input 5
AIO229 0, 4, 8, 12 I Analog Pin Used For Digital Input 229
A3 12 8 8 5 I ADC-A Input 3
CMP3_HP5 I CMPSS-3 High Comparator Positive Input 5
CMP3_LP5 I CMPSS-3 Low Comparator Positive Input 5
A4 36 27 23 23 19 I ADC-A Input 4
B8 I ADC-B Input 8
CMP2_HP0 I CMPSS-2 High Comparator Positive Input 0
CMP2_LP0 I CMPSS-2 Low Comparator Positive Input 0
AIO225 0, 4, 8, 12 I Analog Pin Used For Digital Input 225 This pin also has digital mux functions which are described in the GPIO section of this table.
A5 35 I ADC-A Input 5
CMP2_HP5 I CMPSS-2 High Comparator Positive Input 5
CMP2_LP5 I CMPSS-2 Low Comparator Positive Input 5
AIO249 0, 4, 8, 12 I Analog Pin Used For Digital Input 249
A5 17 13 13 9 I ADC-A Input 5
CMP2_HP5 I CMPSS-2 High Comparator Positive Input 5
CMP2_LP5 I CMPSS-2 Low Comparator Positive Input 5
A6 14 10 6 6 4 I ADC-A Input 6
CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2
CMP1_LP2 I CMPSS-1 Low Comparator Positive Input 2
AIO228 0, 4, 8, 12 I Analog Pin Used For Digital Input 228 This pin also has digital mux functions which are described in the GPIO section of this table.
A8 37 I ADC-A Input 8
CMP4_HP4 I CMPSS-4 High Comparator Positive Input 4
CMP4_LP4 I CMPSS-4 Low Comparator Positive Input 4
AIO240 0, 4, 8, 12 I Analog Pin Used For Digital Input 240 This pin also has digital mux functions which are described in the GPIO section of this table.
A8 24 20 20 16 I ADC-A Input 8
CMP4_HP4 I CMPSS-4 High Comparator Positive Input 4
CMP4_LP4 I CMPSS-4 Low Comparator Positive Input 4
AIO241 0, 4, 8, 12 I Analog Pin Used For Digital Input 241 This pin also has digital mux functions which are described in the GPIO section of this table.
A9 38 28 24 24 20 I ADC-A Input 9
CMP2_HP2 I CMPSS-2 High Comparator Positive Input 2
CMP2_LP2 I CMPSS-2 Low Comparator Positive Input 2
AIO227 0, 4, 8, 12 I Analog Pin Used For Digital Input 227 This pin also has digital mux functions which are described in the GPIO section of this table.
A10 40 29 25 25 21 I ADC-A Input 10
B1 I ADC-B Input 1
C10 I ADC-C Input 10
CMP2_HN0 I CMPSS-2 High Comparator Negative Input 0
CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3
CMP2_LN0 I CMPSS-2 Low Comparator Negative Input 0
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3
AIO230 0, 4, 8, 12 I Analog Pin Used For Digital Input 230 This pin also has digital mux functions which are described in the GPIO section of this table.
A11 20 16 12 12 8 I ADC-A Input 11
B10 I ADC-B Input 10
C0 I ADC-C Input 0
CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1
CMP1_HP1 I CMPSS-1 High Comparator Positive Input 1
CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1
CMP1_LP1 I CMPSS-1 Low Comparator Positive Input 1
AIO237 0, 4, 8, 12 I Analog Pin Used For Digital Input 237 This pin also has digital mux functions which are described in the GPIO section of this table.
A12 28 22 18 18 14 I ADC-A Input 12
CMP2_HN1 I CMPSS-2 High Comparator Negative Input 1
CMP2_HP1 I CMPSS-2 High Comparator Positive Input 1
CMP2_LN1 I CMPSS-2 Low Comparator Negative Input 1
CMP2_LP1 I CMPSS-2 Low Comparator Positive Input 1
AIO238 0, 4, 8, 12 I Analog Pin Used For Digital Input 238 This pin also has digital mux functions which are described in the GPIO section of this table.
A14 19 15 11 11 I ADC-A Input 14
B14 I ADC-B Input 14
C4 I ADC-C Input 4
CMP3_HP4 I CMPSS-3 High Comparator Positive Input 4
CMP3_LP4 I CMPSS-3 Low Comparator Positive Input 4
AIO239 0, 4, 8, 12 I Analog Pin Used For Digital Input 239 This pin also has digital mux functions which are described in the GPIO section of this table.
A15 14 10 10 7 I ADC-A Input 15
CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0
CMP1_HP3 I CMPSS-1 High Comparator Positive Input 3
CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0
CMP1_LP3 I CMPSS-1 Low Comparator Positive Input 3
AIO233 0, 4, 8, 12 I Analog Pin Used For Digital Input 233 This pin also has digital mux functions which are described in the GPIO section of this table.
B0 41 I ADC-B Input 0
C11 I ADC-C Input 11
CMP2_HP4 I CMPSS-2 High Comparator Positive Input 4
CMP2_LP4 I CMPSS-2 Low Comparator Positive Input 4
AIO253 0, 4, 8, 12 I Analog Pin Used For Digital Input 253
B0 24 20 20 16 I ADC-B Input 0
C11 I ADC-C Input 11
CMP2_HP4 I CMPSS-2 High Comparator Positive Input 4
CMP2_LP4 I CMPSS-2 Low Comparator Positive Input 4
B2 15 11 7 7 4 I ADC-B Input 2
C6 I ADC-C Input 6
CMP3_HP0 I CMPSS-3 High Comparator Positive Input 0
CMP3_LP0 I CMPSS-3 Low Comparator Positive Input 0
AIO226 0, 4, 8, 12 I Analog Pin Used For Digital Input 226 This pin also has digital mux functions which are described in the GPIO section of this table.
B3 16 12 8 8 5 I ADC-B Input 3
CMP3_HN0 I CMPSS-3 High Comparator Negative Input 0
CMP3_HP3 I CMPSS-3 High Comparator Positive Input 3
CMP3_LN0 I CMPSS-3 Low Comparator Negative Input 0
CMP3_LP3 I CMPSS-3 Low Comparator Positive Input 3
VDAC I Optional external reference voltage for on-chip DACs.
AIO242 0, 4, 8, 12 I Analog Pin Used For Digital Input 242 This pin also has digital mux functions which are described in the GPIO section of this table.
B4 39 28 24 24 20 I ADC-B Input 4
C8 I ADC-C Input 8
CMP4_HP0 I CMPSS-4 High Comparator Positive Input 0
CMP4_LP0 I CMPSS-4 Low Comparator Positive Input 0
AIO236 0, 4, 8, 12 I Analog Pin Used For Digital Input 236
B5 32 I ADC-B Input 5
CMP1_HP5 I CMPSS-1 High Comparator Positive Input 5
CMP1_LP5 I CMPSS-1 Low Comparator Positive Input 5
AIO252 0, 4, 8, 12 I Analog Pin Used For Digital Input 252 This pin also has digital mux functions which are described in the GPIO section of this table.
B5 48 33 I ADC-B Input 5
CMP1_HP5 I CMPSS-1 High Comparator Positive Input 5
CMP1_LP5 I CMPSS-1 Low Comparator Positive Input 5
GPIO20 I/O General-Purpose Input Output 20 This pin also has digital mux functions which are described in the GPIO section of this table.
B11 30 I ADC-B Input 11
CMP4_HP5 I CMPSS-4 High Comparator Positive Input 5
CMP4_LP5 I CMPSS-4 Low Comparator Positive Input 5
AIO251 0, 4, 8, 12 I Analog Pin Used For Digital Input 251
B11 49 34 I ADC-B Input 11
CMP4_HP5 I CMPSS-4 High Comparator Positive Input 5
CMP4_LP5 I CMPSS-4 Low Comparator Positive Input 5
GPIO21 I/O General-Purpose Input Output 21 This pin also has digital mux functions which are described in the GPIO section of this table.
C1 29 22 18 18 14 I ADC-C Input 1
CMP4_HP2 I CMPSS-4 High Comparator Positive Input 2
CMP4_LP2 I CMPSS-4 Low Comparator Positive Input 2
AIO248 0, 4, 8, 12 I Analog Pin Used For Digital Input 248
AIO248 29 22 18 18 14 I Analog Pin Used For Digital Input 248
B12 21 17 13 13 9 I ADC-B Input 12
C2 I ADC-C Input 2
CMP3_HN1 I CMPSS-3 High Comparator Negative Input 1
CMP3_HP1 I CMPSS-3 High Comparator Positive Input 1
CMP3_LN1 I CMPSS-3 Low Comparator Negative Input 1
CMP3_LP1 I CMPSS-3 Low Comparator Positive Input 1
AIO244 0, 4, 8, 12 I Analog Pin Used For Digital Input 244 This pin also has digital mux functions which are described in the GPIO section of this table.
A7 31 23 19 19 15 I ADC-A Input 7
C3 I ADC-C Input 3
CMP4_HN1 I CMPSS-4 High Comparator Negative Input 1
CMP4_HP1 I CMPSS-4 High Comparator Positive Input 1
CMP4_LN1 I CMPSS-4 Low Comparator Negative Input 1
CMP4_LP1 I CMPSS-4 Low Comparator Positive Input 1
AIO245 0, 4, 8, 12 I Analog Pin Used For Digital Input 245 This pin also has digital mux functions which are described in the GPIO section of this table.
C5 28 12 8 8 5 I ADC-C Input 5
B9 18 14 10 10 7 I ADC-B Input 9
C7 I ADC-C Input 7
C14 42 I ADC-C Input 14
CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0
CMP4_HP3 I CMPSS-4 High Comparator Positive Input 3
CMP4_LN0 I CMPSS-4 Low Comparator Negative Input 0
CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3
AIO247 0, 4, 8, 12 I Analog Pin Used For Digital Input 247
C14 27 23 23 19 I ADC-C Input 14
CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0
CMP4_HP3 I CMPSS-4 High Comparator Positive Input 3
CMP4_LN0 I CMPSS-4 Low Comparator Negative Input 0
CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3
VREFHI 24, 25 20 16 16 12 I ADC High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHI and VREFLO pins.
VREFLO 26, 27 21 17 17 13 I ADC Low Reference
GPIO
AIO231 0, 4, 8, 12 23 19 15 15 11 I Analog Pin Used For Digital Input 231 This pin also has analog functions which are described in the ANALOG section of this table.
SD1_C1 2 I SDFM-1 Channel 1 Clock Input
HIC_BASESEL1 15 I HIC Base address range select 1
AIO232 0, 4, 8, 12 22 18 14 14 10 I Analog Pin Used For Digital Input 232 This pin also has analog functions which are described in the ANALOG section of this table.
SD1_D4 2 I SDFM-1 Channel 4 Data Input
HIC_BASESEL0 15 I HIC Base address range select 0
AIO224 0, 4, 8, 12 17 13 9 9 6 I Analog Pin Used For Digital Input 224 This pin also has analog functions which are described in the ANALOG section of this table.
SD2_D3 2 I SDFM-2 Channel 3 Data Input
HIC_A3 15 I HIC Address 3
AIO225 0, 4, 8, 12 36 27 23 23 19 I Analog Pin Used For Digital Input 225 This pin also has analog functions which are described in the ANALOG section of this table.
SD2_C2 2 I SDFM-2 Channel 2 Clock Input
HIC_NWE 15 I HIC Data Write enable from host
AIO228 0, 4, 8, 12 14 10 6 6 4 I Analog Pin Used For Digital Input 228 This pin also has analog functions which are described in the ANALOG section of this table.
SD2_C1 2 I SDFM-2 Channel 1 Clock Input
HIC_A0 15 I HIC Address 0
AIO240 0, 4, 8, 12 37 I Analog Pin Used For Digital Input 240 This pin also has analog functions which are described in the ANALOG section of this table.
SD2_C1 2 I SDFM-2 Channel 1 Clock Input
HIC_NBE1 15 I HIC Byte enable 1
AIO241 0, 4, 8, 12 24 20 20 16 I Analog Pin Used For Digital Input 241 This pin also has analog functions which are described in the ANALOG section of this table.
SD2_C1 2 I SDFM-2 Channel 1 Clock Input
HIC_NBE1 15 I HIC Byte enable 1
AIO227 0, 4, 8, 12 38 28 24 24 20 I Analog Pin Used For Digital Input 227 This pin also has analog functions which are described in the ANALOG section of this table.
SD1_C3 2 I SDFM-1 Channel 3 Clock Input
HIC_NBE0 15 I HIC Byte enable 0
AIO230 0, 4, 8, 12 40 29 25 25 21 I Analog Pin Used For Digital Input 230 This pin also has analog functions which are described in the ANALOG section of this table.
SD1_C4 2 I SDFM-1 Channel 4 Clock Input
HIC_BASESEL2 15 I HIC Base address range select 2
AIO237 0, 4, 8, 12 20 16 12 12 8 I Analog Pin Used For Digital Input 237 This pin also has analog functions which are described in the ANALOG section of this table.
SD1_D2 2 I SDFM-1 Channel 2 Data Input
HIC_A6 15 I HIC Address 6
AIO238 0, 4, 8, 12 28 22 18 18 14 I Analog Pin Used For Digital Input 238 This pin also has analog functions which are described in the ANALOG section of this table.
SD2_C3 2 I SDFM-2 Channel 3 Clock Input
HIC_NCS 15 I HIC Chip select input
AIO239 0, 4, 8, 12 19 15 11 11 I Analog Pin Used For Digital Input 239 This pin also has analog functions which are described in the ANALOG section of this table.
SD1_D1 2 I SDFM-1 Channel 1 Data Input
HIC_A5 15 I HIC Address 5
AIO233 0, 4, 8, 12 14 10 10 7 I Analog Pin Used For Digital Input 233 This pin also has analog functions which are described in the ANALOG section of this table.
SD2_D1 2 I SDFM-2 Channel 1 Data Input
HIC_A4 15 I HIC Address 4
AIO226 0, 4, 8, 12 15 11 7 7 4 I Analog Pin Used For Digital Input 226 This pin also has analog functions which are described in the ANALOG section of this table.
SD2_D4 2 I SDFM-2 Channel 4 Data Input
HIC_A1 15 I HIC Address 1
AIO242 0, 4, 8, 12 16 12 8 8 5 I Analog Pin Used For Digital Input 242 This pin also has analog functions which are described in the ANALOG section of this table.
SD2_D2 2 I SDFM-2 Channel 2 Data Input
HIC_A2 15 I HIC Address 2
AIO252 0, 4, 8, 12 32 I Analog Pin Used For Digital Input 252 This pin also has analog functions which are described in the ANALOG section of this table.
SD2_C4 2 I SDFM-2 Channel 4 Clock Input
AIO244 0, 4, 8, 12 21 17 13 13 9 I Analog Pin Used For Digital Input 244 This pin also has analog functions which are described in the ANALOG section of this table.
SD1_D3 2 I SDFM-1 Channel 3 Data Input
HIC_A7 15 I HIC Address 7
AIO245 0, 4, 8, 12 31 23 19 19 15 I Analog Pin Used For Digital Input 245 This pin also has analog functions which are described in the ANALOG section of this table.
SD1_C2 2 I SDFM-1 Channel 2 Clock Input
HIC_NOE 15 O HIC Output enable for data bus
GPIO0 0, 4, 8, 12 79 63 52 52 42 I/O General-Purpose Input Output 0
EPWM1_A 1 O ePWM-1 Output A
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
SPIA_STE 7 I/O SPI-A Slave Transmit Enable (STE)
FSIRXA_CLK 9 I FSIRX-A Input Clock
MCAN_RX 10 I CAN/CAN FD Receive
CLB_OUTPUTXBAR8 11 O CLB Output X-BAR Output 8
EQEP1_INDEX 13 I/O eQEP-1 Index
HIC_D7 14 I/O HIC Data 7
HIC_BASESEL1 15 I HIC Base address range select 1
GPIO1 0, 4, 8, 12 78 62 51 51 41 I/O General-Purpose Input Output 1
EPWM1_B 1 O ePWM-1 Output B
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
SPIA_SOMI 7 I/O SPI-A Slave Out, Master In (SOMI)
MCAN_TX 10 O CAN/CAN FD Transmit
CLB_OUTPUTXBAR7 11 O CLB Output X-BAR Output 7
HIC_A2 13 I HIC Address 2
FSITXA_TDM_D1 14 I FSITX-A Time Division Multiplexed Additional Data Input
HIC_D10 15 I/O HIC Data 10
GPIO2 0, 4, 8, 12 77 61 50 50 40 I/O General-Purpose Input Output 2
EPWM2_A 1 O ePWM-2 Output A
OUTPUTXBAR1 5 O Output X-BAR Output 1
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
SPIA_SIMO 7 I/O SPI-A Slave In, Master Out (SIMO)
SCIA_TX 9 O SCI-A Transmit Data
FSIRXA_D1 10 I FSIRX-A Optional Additional Data Input
I2CB_SDA 11 I/OD I2C-B Open-Drain Bidirectional Data
HIC_A1 13 I HIC Address 1
CANA_TX 14 O CAN-A Transmit
HIC_D9 15 I/O HIC Data 9
GPIO3 0, 4, 8, 12 76 60 49 49 39 I/O General-Purpose Input Output 3
EPWM2_B 1 O ePWM-2 Output B
OUTPUTXBAR2 2, 5 O Output X-BAR Output 2
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
SPIA_CLK 7 I/O SPI-A Clock
SCIA_RX 9 I SCI-A Receive Data
FSIRXA_D0 10 I FSIRX-A Primary Data Input
I2CB_SCL 11 I/OD I2C-B Open-Drain Bidirectional Clock
HIC_NOE 13 O HIC Output enable for data bus
CANA_RX 14 I CAN-A Receive
HIC_D4 15 I/O HIC Data 4
GPIO4 0, 4, 8, 12 75 59 48 48 38 I/O General-Purpose Input Output 4
EPWM3_A 1 O ePWM-3 Output A
MCAN_TX 3 O CAN/CAN FD Transmit
OUTPUTXBAR3 5 O Output X-BAR Output 3
CANA_TX 6 O CAN-A Transmit
SPIB_CLK 7 I/O SPI-B Clock
EQEP2_STROBE 9 I/O eQEP-2 Strobe
FSIRXA_CLK 10 I FSIRX-A Input Clock
CLB_OUTPUTXBAR6 11 O CLB Output X-BAR Output 6
HIC_BASESEL2 13 I HIC Base address range select 2
HIC_NWE 15 I HIC Data Write enable from host
GPIO5 0, 4, 8, 12 89 74 61 61 47 I/O General-Purpose Input Output 5
EPWM3_B 1 O ePWM-3 Output B
OUTPUTXBAR3 3 O Output X-BAR Output 3
MCAN_RX 5 I CAN/CAN FD Receive
CANA_RX 6 I CAN-A Receive
SPIA_STE 7 I/O SPI-A Slave Transmit Enable (STE)
FSITXA_D1 9 O FSITX-A Optional Additional Data Output
CLB_OUTPUTXBAR5 10 O CLB Output X-BAR Output 5
HIC_A7 13 I HIC Address 7
HIC_D4 14 I/O HIC Data 4
HIC_D15 15 I/O HIC Data 15
GPIO6 0, 4, 8, 12 97 80 64 64 48 I/O General-Purpose Input Output 6
EPWM4_A 1 O ePWM-4 Output A
OUTPUTXBAR4 2 O Output X-BAR Output 4
SYNCOUT 3 O External ePWM Synchronization Pulse
EQEP1_A 5 I eQEP-1 Input A
SPIB_SOMI 7 I/O SPI-B Slave Out, Master In (SOMI)
FSITXA_D0 9 O FSITX-A Primary Data Output
FSITXA_D1 11 O FSITX-A Optional Additional Data Output
HIC_NBE1 13 I HIC Byte enable 1
CLB_OUTPUTXBAR8 14 O CLB Output X-BAR Output 8
HIC_D14 15 I/O HIC Data 14
GPIO7 0, 4, 8, 12 84 68 57 57 43 I/O General-Purpose Input Output 7
EPWM4_B 1 O ePWM-4 Output B
OUTPUTXBAR5 3 O Output X-BAR Output 5
EQEP1_B 5 I eQEP-1 Input B
SPIB_SIMO 7 I/O SPI-B Slave In, Master Out (SIMO)
FSITXA_CLK 9 O FSITX-A Output Clock
CLB_OUTPUTXBAR2 10 O CLB Output X-BAR Output 2
HIC_A6 13 I HIC Address 6
HIC_D14 15 I/O HIC Data 14
GPIO8 0, 4, 8, 12 74 58 47 47 I/O General-Purpose Input Output 8
EPWM5_A 1 O ePWM-5 Output A
ADCSOCAO 3 O ADC Start of Conversion A for External ADC
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SCIA_TX 6 O SCI-A Transmit Data
SPIA_SIMO 7 I/O SPI-A Slave In, Master Out (SIMO)
I2CA_SCL 9 I/OD I2C-A Open-Drain Bidirectional Clock
FSITXA_D1 10 O FSITX-A Optional Additional Data Output
CLB_OUTPUTXBAR5 11 O CLB Output X-BAR Output 5
HIC_A0 13 I HIC Address 0
FSITXA_TDM_CLK 14 I FSITX-A Time Division Multiplexed Clock Input
HIC_D8 15 I/O HIC Data 8
GPIO9 0, 4, 8, 12 90 75 62 62 I/O General-Purpose Input Output 9
EPWM5_B 1 O ePWM-5 Output B
SCIB_TX 2 O SCI-B Transmit Data
OUTPUTXBAR6 3 O Output X-BAR Output 6
EQEP1_INDEX 5 I/O eQEP-1 Index
SCIA_RX 6 I SCI-A Receive Data
SPIA_CLK 7 I/O SPI-A Clock
FSITXA_D0 10 O FSITX-A Primary Data Output
LINB_RX 11 I LIN-B Receive
HIC_BASESEL0 13 I HIC Base address range select 0
I2CB_SCL 14 I/OD I2C-B Open-Drain Bidirectional Clock
HIC_NRDY 15 O HIC Ready from device to host
GPIO10 0, 4, 8, 12 93 76 63 63 I/O General-Purpose Input Output 10
EPWM6_A 1 O ePWM-6 Output A
ADCSOCBO 3 O ADC Start of Conversion B for External ADC
EQEP1_A 5 I eQEP-1 Input A
SCIB_TX 6 O SCI-B Transmit Data
SPIA_SOMI 7 I/O SPI-A Slave Out, Master In (SOMI)
I2CA_SDA 9 I/OD I2C-A Open-Drain Bidirectional Data
FSITXA_CLK 10 O FSITX-A Output Clock
LINB_TX 11 O LIN-B Transmit
HIC_NWE 13 I HIC Data Write enable from host
FSITXA_TDM_D0 14 I FSITX-A Time Division Multiplexed Data Input
CLB_OUTPUTXBAR4 15 O CLB Output X-BAR Output 4
GPIO11 0, 4, 8, 12 52 37 31 31 I/O General-Purpose Input Output 11
EPWM6_B 1 O ePWM-6 Output B
OUTPUTXBAR7 3 O Output X-BAR Output 7
EQEP1_B 5 I eQEP-1 Input B
SCIB_RX 6 I SCI-B Receive Data
SPIA_STE 7 I/O SPI-A Slave Transmit Enable (STE)
FSIRXA_D1 9 I FSIRX-A Optional Additional Data Input
LINB_RX 10 I LIN-B Receive
EQEP2_A 11 I eQEP-2 Input A
SPIA_SIMO 13 I/O SPI-A Slave In, Master Out (SIMO)
HIC_D6 14 I/O HIC Data 6
HIC_NBE0 15 I HIC Byte enable 0
GPIO12 0, 4, 8, 12 51 36 30 30 I/O General-Purpose Input Output 12
EPWM7_A 1 O ePWM-7 Output A
MCAN_RX 3 I CAN/CAN FD Receive
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SCIB_TX 6 O SCI-B Transmit Data
PMBUSA_CTL 7 I/O PMBus-A Control Signal - Slave Input/Master Output
FSIRXA_D0 9 I FSIRX-A Primary Data Input
LINB_TX 10 O LIN-B Transmit
SPIA_CLK 11 I/O SPI-A Clock
CANA_RX 13 I CAN-A Receive
HIC_D13 14 I/O HIC Data 13
HIC_INT 15 O HIC Device interrupt to host
GPIO13 0, 4, 8, 12 50 35 29 29 I/O General-Purpose Input Output 13
EPWM7_B 1 O ePWM-7 Output B
MCAN_TX 3 O CAN/CAN FD Transmit
EQEP1_INDEX 5 I/O eQEP-1 Index
SCIB_RX 6 I SCI-B Receive Data
PMBUSA_ALERT 7 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
FSIRXA_CLK 9 I FSIRX-A Input Clock
LINB_RX 10 I LIN-B Receive
SPIA_SOMI 11 I/O SPI-A Slave Out, Master In (SOMI)
CANA_TX 13 O CAN-A Transmit
HIC_D11 14 I/O HIC Data 11
HIC_D5 15 I/O HIC Data 5
GPIO14 0, 4, 8, 12 96 79 I/O General-Purpose Input Output 14
EPWM8_A 1 O ePWM-8 Output A
SCIB_TX 2 O SCI-B Transmit Data
I2CB_SDA 5 I/OD I2C-B Open-Drain Bidirectional Data
OUTPUTXBAR3 6 O Output X-BAR Output 3
PMBUSA_SDA 7 I/OD PMBus-A Open-Drain Bidirectional Data
SPIB_CLK 9 I/O SPI-B Clock
EQEP2_A 10 I eQEP-2 Input A
LINB_TX 11 O LIN-B Transmit
EPWM3_A 13 O ePWM-3 Output A
CLB_OUTPUTXBAR7 14 O CLB Output X-BAR Output 7
HIC_D15 15 I/O HIC Data 15
GPIO15 0, 4, 8, 12 95 78 I/O General-Purpose Input Output 15
EPWM8_B 1 O ePWM-8 Output B
SCIB_RX 2 I SCI-B Receive Data
I2CB_SCL 5 I/OD I2C-B Open-Drain Bidirectional Clock
OUTPUTXBAR4 6 O Output X-BAR Output 4
PMBUSA_SCL 7 I/OD PMBus-A Open-Drain Bidirectional Clock
SPIB_STE 9 I/O SPI-B Slave Transmit Enable (STE)
EQEP2_B 10 I eQEP-2 Input B
LINB_RX 11 I LIN-B Receive
EPWM3_B 13 O ePWM-3 Output B
CLB_OUTPUTXBAR6 14 O CLB Output X-BAR Output 6
HIC_D12 15 I/O HIC Data 12
GPIO16 0, 4, 8, 12 54 39 33 33 26 I/O General-Purpose Input Output 16
SPIA_SIMO 1 I/O SPI-A Slave In, Master Out (SIMO)
OUTPUTXBAR7 3 O Output X-BAR Output 7
EPWM5_A 5 O ePWM-5 Output A
SCIA_TX 6 O SCI-A Transmit Data
SD1_D1 7 I SDFM-1 Channel 1 Data Input
EQEP1_STROBE 9 I/O eQEP-1 Strobe
PMBUSA_SCL 10 I/OD PMBus-A Open-Drain Bidirectional Clock
XCLKOUT 11 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
EQEP2_B 13 I eQEP-2 Input B
SPIB_SOMI 14 I/O SPI-B Slave Out, Master In (SOMI)
HIC_D1 15 I/O HIC Data 1
GPIO17 0, 4, 8, 12 55 40 34 34 I/O General-Purpose Input Output 17
SPIA_SOMI 1 I/O SPI-A Slave Out, Master In (SOMI)
OUTPUTXBAR8 3 O Output X-BAR Output 8
EPWM5_B 5 O ePWM-5 Output B
SCIA_RX 6 I SCI-A Receive Data
SD1_C1 7 I SDFM-1 Channel 1 Clock Input
EQEP1_INDEX 9 I/O eQEP-1 Index
PMBUSA_SDA 10 I/OD PMBus-A Open-Drain Bidirectional Data
CANA_TX 11 O CAN-A Transmit
HIC_D2 15 I/O HIC Data 2
GPIO18 0, 4, 8, 12 68 50 41 41 33 I/O General-Purpose Input Output 18
SPIA_CLK 1 I/O SPI-A Clock
SCIB_TX 2 O SCI-B Transmit Data
CANA_RX 3 I CAN-A Receive
EPWM6_A 5 O ePWM-6 Output A
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
SD1_D2 7 I SDFM-1 Channel 2 Data Input
EQEP2_A 9 I eQEP-2 Input A
PMBUSA_CTL 10 I/O PMBus-A Control Signal - Slave Input/Master Output
XCLKOUT 11 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
LINB_TX 13 O LIN-B Transmit
FSITXA_TDM_CLK 14 I FSITX-A Time Division Multiplexed Clock Input
HIC_INT 15 O HIC Device interrupt to host
X2 ALT I/O Crystal oscillator output.
GPIO19 0, 4, 8, 12 69 51 42 42 34 I/O General-Purpose Input Output 19
SPIA_STE 1 I/O SPI-A Slave Transmit Enable (STE)
SCIB_RX 2 I SCI-B Receive Data
CANA_TX 3 O CAN-A Transmit
EPWM6_B 5 O ePWM-6 Output B
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
SD1_C2 7 I SDFM-1 Channel 2 Clock Input
EQEP2_B 9 I eQEP-2 Input B
PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
CLB_OUTPUTXBAR1 11 O CLB Output X-BAR Output 1
LINB_RX 13 I LIN-B Receive
FSITXA_TDM_D0 14 I FSITX-A Time Division Multiplexed Data Input
HIC_NBE0 15 I HIC Byte enable 0
X1 ALT I/O Crystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock. See the XTAL section for usage details.
GPIO20 0, 4, 8, 12 48 33 I/O General-Purpose Input Output 20 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP1_A 1 I eQEP-1 Input A
SPIB_SIMO 6 I/O SPI-B Slave In, Master Out (SIMO)
SD1_D3 7 I SDFM-1 Channel 3 Data Input
MCAN_TX 9 O CAN/CAN FD Transmit
GPIO21 0, 4, 8, 12 49 34 I/O General-Purpose Input Output 21 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP1_B 1 I eQEP-1 Input B
SPIB_SOMI 6 I/O SPI-B Slave Out, Master In (SOMI)
SD1_C3 7 I SDFM-1 Channel 3 Clock Input
MCAN_RX 9 I CAN/CAN FD Receive
GPIO22 0, 4, 8, 12 83 67 56 56 I/O General-Purpose Input Output 22
EQEP1_STROBE 1 I/O eQEP-1 Strobe
SCIB_TX 3 O SCI-B Transmit Data
SPIB_CLK 6 I/O SPI-B Clock
SD1_D4 7 I SDFM-1 Channel 4 Data Input
LINA_TX 9 O LIN-A Transmit
CLB_OUTPUTXBAR1 10 O CLB Output X-BAR Output 1
LINB_TX 11 O LIN-B Transmit
HIC_A5 13 I HIC Address 5
EPWM4_A 14 O ePWM-4 Output A
HIC_D13 15 I/O HIC Data 13
GPIO23 0, 4, 8, 12 81 65 54 54 I/O General-Purpose Input Output 23
EQEP1_INDEX 1 I/O eQEP-1 Index
SCIB_RX 3 I SCI-B Receive Data
SPIB_STE 6 I/O SPI-B Slave Transmit Enable (STE)
SD1_C4 7 I SDFM-1 Channel 4 Clock Input
LINA_RX 9 I LIN-A Receive
CLB_OUTPUTXBAR3 10 O CLB Output X-BAR Output 3
LINB_RX 11 I LIN-B Receive
HIC_A3 13 I HIC Address 3
EPWM4_B 14 O ePWM-4 Output B
HIC_D11 15 I/O HIC Data 11
GPIO24 0, 4, 8, 12 56 41 35 35 27 I/O General-Purpose Input Output 24
OUTPUTXBAR1 1 O Output X-BAR Output 1
EQEP2_A 2 I eQEP-2 Input A
EPWM8_A 5 O ePWM-8 Output A
SPIB_SIMO 6 I/O SPI-B Slave In, Master Out (SIMO)
SD2_D1 7 I SDFM-2 Channel 1 Data Input
LINB_TX 9 O LIN-B Transmit
PMBUSA_SCL 10 I/OD PMBus-A Open-Drain Bidirectional Clock
SCIA_TX 11 O SCI-A Transmit Data
ERRORSTS 13 O Error Status Output. This signal requires an external pulldown.
HIC_D3 15 I/O HIC Data 3
GPIO25 0, 4, 8, 12 57 42 I/O General-Purpose Input Output 25
OUTPUTXBAR2 1 O Output X-BAR Output 2
EQEP2_B 2 I eQEP-2 Input B
EQEP1_A 5 I eQEP-1 Input A
SPIB_SOMI 6 I/O SPI-B Slave Out, Master In (SOMI)
SD2_C1 7 I SDFM-2 Channel 1 Clock Input
FSITXA_D1 9 O FSITX-A Optional Additional Data Output
PMBUSA_SDA 10 I/OD PMBus-A Open-Drain Bidirectional Data
SCIA_RX 11 I SCI-A Receive Data
HIC_BASESEL0 14 I HIC Base address range select 0
GPIO26 0, 4, 8, 12 58 43 I/O General-Purpose Input Output 26
OUTPUTXBAR3 1, 5 O Output X-BAR Output 3
EQEP2_INDEX 2 I/O eQEP-2 Index
SPIB_CLK 6 I/O SPI-B Clock
SD2_D2 7 I SDFM-2 Channel 2 Data Input
FSITXA_D0 9 O FSITX-A Primary Data Output
PMBUSA_CTL 10 I/O PMBus-A Control Signal - Slave Input/Master Output
I2CA_SDA 11 I/OD I2C-A Open-Drain Bidirectional Data
HIC_D0 14 I/O HIC Data 0
HIC_A1 15 I HIC Address 1
GPIO27 0, 4, 8, 12 59 44 I/O General-Purpose Input Output 27
OUTPUTXBAR4 1, 5 O Output X-BAR Output 4
EQEP2_STROBE 2 I/O eQEP-2 Strobe
SPIB_STE 6 I/O SPI-B Slave Transmit Enable (STE)
SD2_C2 7 I SDFM-2 Channel 2 Clock Input
FSITXA_CLK 9 O FSITX-A Output Clock
PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
I2CA_SCL 11 I/OD I2C-A Open-Drain Bidirectional Clock
HIC_D1 14 I/O HIC Data 1
HIC_A4 15 I HIC Address 4
GPIO28 0, 4, 8, 12 1 4 2 2 2 I/O General-Purpose Input Output 28
SCIA_RX 1 I SCI-A Receive Data
EPWM7_A 3 O ePWM-7 Output A
OUTPUTXBAR5 5 O Output X-BAR Output 5
EQEP1_A 6 I eQEP-1 Input A
SD2_D3 7 I SDFM-2 Channel 3 Data Input
EQEP2_STROBE 9 I/O eQEP-2 Strobe
LINA_TX 10 O LIN-A Transmit
SPIB_CLK 11 I/O SPI-B Clock
ERRORSTS 13 O Error Status Output. This signal requires an external pulldown.
I2CB_SDA 14 I/OD I2C-B Open-Drain Bidirectional Data
HIC_NOE 15 O HIC Output enable for data bus
GPIO29 0, 4, 8, 12 100 3 1 1 1 I/O General-Purpose Input Output 29
SCIA_TX 1 O SCI-A Transmit Data
EPWM7_B 3 O ePWM-7 Output B
OUTPUTXBAR6 5 O Output X-BAR Output 6
EQEP1_B 6 I eQEP-1 Input B
SD2_C3 7 I SDFM-2 Channel 3 Clock Input
EQEP2_INDEX 9 I/O eQEP-2 Index
LINA_RX 10 I LIN-A Receive
SPIB_STE 11 I/O SPI-B Slave Transmit Enable (STE)
ERRORSTS 13 O Error Status Output. This signal requires an external pulldown.
I2CB_SCL 14 I/OD I2C-B Open-Drain Bidirectional Clock
HIC_NCS 15 I HIC Chip select input
AUXCLKIN ALT I Auxiliary Clock Input
GPIO30 0, 4, 8, 12 98 1 I/O General-Purpose Input Output 30
CANA_RX 1 I CAN-A Receive
SPIB_SIMO 3 I/O SPI-B Slave In, Master Out (SIMO)
OUTPUTXBAR7 5 O Output X-BAR Output 7
EQEP1_STROBE 6 I/O eQEP-1 Strobe
SD2_D4 7 I SDFM-2 Channel 4 Data Input
FSIRXA_CLK 9 I FSIRX-A Input Clock
MCAN_RX 10 I CAN/CAN FD Receive
EPWM1_A 11 O ePWM-1 Output A
HIC_D8 14 I/O HIC Data 8
GPIO31 0, 4, 8, 12 99 2 I/O General-Purpose Input Output 31
CANA_TX 1 O CAN-A Transmit
SPIB_SOMI 3 I/O SPI-B Slave Out, Master In (SOMI)
OUTPUTXBAR8 5 O Output X-BAR Output 8
EQEP1_INDEX 6 I/O eQEP-1 Index
SD2_C4 7 I SDFM-2 Channel 4 Clock Input
FSIRXA_D1 9 I FSIRX-A Optional Additional Data Input
MCAN_TX 10 O CAN/CAN FD Transmit
EPWM1_B 11 O ePWM-1 Output B
HIC_D10 14 I/O HIC Data 10
GPIO32 0, 4, 8, 12 64 49 40 40 32 I/O General-Purpose Input Output 32
I2CA_SDA 1 I/OD I2C-A Open-Drain Bidirectional Data
SPIB_CLK 3 I/O SPI-B Clock
EPWM8_B 5 O ePWM-8 Output B
LINA_TX 6 O LIN-A Transmit
SD1_D2 7 I SDFM-1 Channel 2 Data Input
FSIRXA_D0 9 I FSIRX-A Primary Data Input
CANA_TX 10 O CAN-A Transmit
PMBUSA_SDA 11 I/OD PMBus-A Open-Drain Bidirectional Data
ADCSOCBO 13 O ADC Start of Conversion B for External ADC
HIC_INT 15 O HIC Device interrupt to host
GPIO33 0, 4, 8, 12 53 38 32 32 25 I/O General-Purpose Input Output 33
I2CA_SCL 1 I/OD I2C-A Open-Drain Bidirectional Clock
SPIB_STE 3 I/O SPI-B Slave Transmit Enable (STE)
OUTPUTXBAR4 5 O Output X-BAR Output 4
LINA_RX 6 I LIN-A Receive
SD1_C2 7 I SDFM-1 Channel 2 Clock Input
FSIRXA_CLK 9 I FSIRX-A Input Clock
CANA_RX 10 I CAN-A Receive
EQEP2_B 11 I eQEP-2 Input B
ADCSOCAO 13 O ADC Start of Conversion A for External ADC
SD1_C1 14 I SDFM-1 Channel 1 Clock Input
HIC_D0 15 I/O HIC Data 0
GPIO34 0, 4, 8, 12 94 77 I/O General-Purpose Input Output 34
OUTPUTXBAR1 1 O Output X-BAR Output 1
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
HIC_NBE1 13 I HIC Byte enable 1
I2CB_SDA 14 I/OD I2C-B Open-Drain Bidirectional Data
HIC_D9 15 I/O HIC Data 9
GPIO35 0, 4, 8, 12 63 48 39 39 31 I/O General-Purpose Input Output 35
SCIA_RX 1 I SCI-A Receive Data
I2CA_SDA 3 I/OD I2C-A Open-Drain Bidirectional Data
CANA_RX 5 I CAN-A Receive
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
LINA_RX 7 I LIN-A Receive
EQEP1_A 9 I eQEP-1 Input A
PMBUSA_CTL 10 I/O PMBus-A Control Signal - Slave Input/Master Output
EPWM5_B 11 O ePWM-5 Output B
SD2_C1 13 I SDFM-2 Channel 1 Clock Input
HIC_NWE 14 I HIC Data Write enable from host
TDI 15 I JTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input.
GPIO37 0, 4, 8, 12 61 46 37 37 29 I/O General-Purpose Input Output 37
OUTPUTXBAR2 1 O Output X-BAR Output 2
I2CA_SCL 3 I/OD I2C-A Open-Drain Bidirectional Clock
SCIA_TX 5 O SCI-A Transmit Data
CANA_TX 6 O CAN-A Transmit
LINA_TX 7 O LIN-A Transmit
EQEP1_B 9 I eQEP-1 Input B
PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
HIC_NRDY 14 O HIC Ready from device to host
TDO 15 O JTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input.
GPIO39 0, 4, 8, 12 56 46 I/O General-Purpose Input Output 39
MCAN_RX 6 I CAN/CAN FD Receive
FSIRXA_CLK 7 I FSIRX-A Input Clock
EQEP2_INDEX 9 I/O eQEP-2 Index
CLB_OUTPUTXBAR2 11 O CLB Output X-BAR Output 2
SYNCOUT 13 O External ePWM Synchronization Pulse
EQEP1_INDEX 14 I/O eQEP-1 Index
HIC_D7 15 I/O HIC Data 7
GPIO40 0, 4, 8, 12 80 64 53 53 I/O General-Purpose Input Output 40
SPIB_SIMO 1 I/O SPI-B Slave In, Master Out (SIMO)
EPWM2_B 5 O ePWM-2 Output B
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
FSIRXA_D0 7 I FSIRX-A Primary Data Input
SCIB_TX 9 O SCI-B Transmit Data
EQEP1_A 10 I eQEP-1 Input A
LINB_TX 11 O LIN-B Transmit
HIC_NBE1 14 I HIC Byte enable 1
HIC_D5 15 I/O HIC Data 5
GPIO41 0, 4, 8, 12 82 66 55 55 I/O General-Purpose Input Output 41
EPWM2_A 5 O ePWM-2 Output A
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
FSIRXA_D1 7 I FSIRX-A Optional Additional Data Input
SCIB_RX 9 I SCI-B Receive Data
EQEP1_B 10 I eQEP-1 Input B
LINB_RX 11 I LIN-B Receive
HIC_A4 13 I HIC Address 4
SPIB_SOMI 14 I/O SPI-B Slave Out, Master In (SOMI)
HIC_D12 15 I/O HIC Data 12
GPIO42 0, 4, 8, 12 57 I/O General-Purpose Input Output 42
LINA_RX 2 I LIN-A Receive
OUTPUTXBAR5 3 O Output X-BAR Output 5
PMBUSA_CTL 5 I/O PMBus-A Control Signal - Slave Input/Master Output
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
EQEP1_STROBE 10 I/O eQEP-1 Strobe
CLB_OUTPUTXBAR3 11 O CLB Output X-BAR Output 3
HIC_D2 14 I/O HIC Data 2
HIC_A6 15 I HIC Address 6
GPIO43 0, 4, 8, 12 54 I/O General-Purpose Input Output 43
OUTPUTXBAR6 3 O Output X-BAR Output 6
PMBUSA_ALERT 5, 9 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
EQEP1_INDEX 10 I/O eQEP-1 Index
CLB_OUTPUTXBAR4 11 O CLB Output X-BAR Output 4
SD2_D3 13 I SDFM-2 Channel 3 Data Input
HIC_D3 14 I/O HIC Data 3
HIC_A7 15 I HIC Address 7
GPIO44 0, 4, 8, 12 85 69 I/O General-Purpose Input Output 44
OUTPUTXBAR7 3 O Output X-BAR Output 7
EQEP1_A 5 I eQEP-1 Input A
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
FSITXA_CLK 7 O FSITX-A Output Clock
PMBUSA_CTL 9 I/O PMBus-A Control Signal - Slave Input/Master Output
CLB_OUTPUTXBAR3 10 O CLB Output X-BAR Output 3
FSIRXA_D0 11 I FSIRX-A Primary Data Input
HIC_D7 13 I/O HIC Data 7
LINB_TX 14 O LIN-B Transmit
HIC_D5 15 I/O HIC Data 5
GPIO45 0, 4, 8, 12 73 I/O General-Purpose Input Output 45
OUTPUTXBAR8 3 O Output X-BAR Output 8
FSITXA_D0 7 O FSITX-A Primary Data Output
PMBUSA_ALERT 9 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
CLB_OUTPUTXBAR4 10 O CLB Output X-BAR Output 4
SD2_C3 13 I SDFM-2 Channel 3 Clock Input
HIC_D6 15 I/O HIC Data 6
GPIO46 0, 4, 8, 12 6 I/O General-Purpose Input Output 46
LINA_TX 3 O LIN-A Transmit
MCAN_TX 5 O CAN/CAN FD Transmit
FSITXA_D1 7 O FSITX-A Optional Additional Data Output
PMBUSA_SDA 9 I/OD PMBus-A Open-Drain Bidirectional Data
SD2_C4 13 I SDFM-2 Channel 4 Clock Input
HIC_NWE 15 I HIC Data Write enable from host
GPIO47 0, 4, 8, 12 6 I/O General-Purpose Input Output 47
LINA_RX 3 I LIN-A Receive
MCAN_RX 5 I CAN/CAN FD Receive
CLB_OUTPUTXBAR2 7 O CLB Output X-BAR Output 2
PMBUSA_SCL 9 I/OD PMBus-A Open-Drain Bidirectional Clock
SD2_D4 13 I SDFM-2 Channel 4 Data Input
FSITXA_TDM_CLK 14 I FSITX-A Time Division Multiplexed Clock Input
HIC_A6 15 I HIC Address 6
GPIO48 0, 4, 8, 12 7 I/O General-Purpose Input Output 48
OUTPUTXBAR3 1 O Output X-BAR Output 3
CANA_TX 3 O CAN-A Transmit
SCIA_TX 6 O SCI-A Transmit Data
SD1_D1 7 I SDFM-1 Channel 1 Data Input
PMBUSA_SDA 9 I/OD PMBus-A Open-Drain Bidirectional Data
HIC_A7 15 I HIC Address 7
GPIO49 0, 4, 8, 12 8 I/O General-Purpose Input Output 49
OUTPUTXBAR4 1 O Output X-BAR Output 4
CANA_RX 3 I CAN-A Receive
SCIA_RX 6 I SCI-A Receive Data
SD1_C1 7 I SDFM-1 Channel 1 Clock Input
LINA_RX 9 I LIN-A Receive
SD2_D1 13 I SDFM-2 Channel 1 Data Input
FSITXA_D0 14 O FSITX-A Primary Data Output
HIC_D2 15 I/O HIC Data 2
GPIO50 0, 4, 8, 12 9 I/O General-Purpose Input Output 50
EQEP1_A 1 I eQEP-1 Input A
MCAN_TX 5 O CAN/CAN FD Transmit
SPIB_SIMO 6 I/O SPI-B Slave In, Master Out (SIMO)
SD1_D2 7 I SDFM-1 Channel 2 Data Input
I2CB_SDA 9 I/OD I2C-B Open-Drain Bidirectional Data
SD2_D2 13 I SDFM-2 Channel 2 Data Input
FSITXA_D1 14 O FSITX-A Optional Additional Data Output
HIC_D3 15 I/O HIC Data 3
GPIO51 0, 4, 8, 12 10 I/O General-Purpose Input Output 51
EQEP1_B 1 I eQEP-1 Input B
MCAN_RX 5 I CAN/CAN FD Receive
SPIB_SOMI 6 I/O SPI-B Slave Out, Master In (SOMI)
SD1_C2 7 I SDFM-1 Channel 2 Clock Input
I2CB_SCL 9 I/OD I2C-B Open-Drain Bidirectional Clock
SD2_D3 13 I SDFM-2 Channel 3 Data Input
FSITXA_CLK 14 O FSITX-A Output Clock
HIC_D6 15 I/O HIC Data 6
GPIO52 0, 4, 8, 12 11 I/O General-Purpose Input Output 52
EQEP1_STROBE 1 I/O eQEP-1 Strobe
CLB_OUTPUTXBAR5 5 O CLB Output X-BAR Output 5
SPIB_CLK 6 I/O SPI-B Clock
SD1_D3 7 I SDFM-1 Channel 3 Data Input
SYNCOUT 9 O External ePWM Synchronization Pulse
SD2_D4 13 I SDFM-2 Channel 4 Data Input
FSIRXA_D0 14 I FSIRX-A Primary Data Input
HIC_NWE 15 I HIC Data Write enable from host
GPIO53 0, 4, 8, 12 12 I/O General-Purpose Input Output 53
EQEP1_INDEX 1 I/O eQEP-1 Index
CLB_OUTPUTXBAR6 5 O CLB Output X-BAR Output 6
SPIB_STE 6 I/O SPI-B Slave Transmit Enable (STE)
SD1_C3 7 I SDFM-1 Channel 3 Clock Input
ADCSOCAO 9 O ADC Start of Conversion A for External ADC
CANA_RX 10 I CAN-A Receive
SD1_C1 13 I SDFM-1 Channel 1 Clock Input
FSIRXA_D1 14 I FSIRX-A Optional Additional Data Input
GPIO54 0, 4, 8, 12 13 I/O General-Purpose Input Output 54
SPIA_SIMO 1 I/O SPI-A Slave In, Master Out (SIMO)
EQEP2_A 5 I eQEP-2 Input A
OUTPUTXBAR2 6 O Output X-BAR Output 2
SD1_D4 7 I SDFM-1 Channel 4 Data Input
ADCSOCBO 9 O ADC Start of Conversion B for External ADC
LINB_TX 10 O LIN-B Transmit
SD1_C2 13 I SDFM-1 Channel 2 Clock Input
FSIRXA_CLK 14 I FSIRX-A Input Clock
FSITXA_TDM_D1 15 I FSITX-A Time Division Multiplexed Additional Data Input
GPIO55 0, 4, 8, 12 43 I/O General-Purpose Input Output 55
SPIA_SOMI 1 I/O SPI-A Slave Out, Master In (SOMI)
EQEP2_B 5 I eQEP-2 Input B
OUTPUTXBAR3 6 O Output X-BAR Output 3
SD1_C4 7 I SDFM-1 Channel 4 Clock Input
ERRORSTS 9 O Error Status Output. This signal requires an external pulldown.
LINB_RX 10 I LIN-B Receive
SD1_C3 13 I SDFM-1 Channel 3 Clock Input
HIC_A0 15 I HIC Address 0
GPIO56 0, 4, 8, 12 65 I/O General-Purpose Input Output 56
SPIA_CLK 1 I/O SPI-A Clock
CLB_OUTPUTXBAR7 2 O CLB Output X-BAR Output 7
MCAN_TX 3 O CAN/CAN FD Transmit
EQEP2_STROBE 5 I/O eQEP-2 Strobe
SCIB_TX 6 O SCI-B Transmit Data
SD2_D1 7 I SDFM-2 Channel 1 Data Input
SPIB_SIMO 9 I/O SPI-B Slave In, Master Out (SIMO)
I2CA_SDA 10 I/OD I2C-A Open-Drain Bidirectional Data
EQEP1_A 11 I eQEP-1 Input A
SD1_C4 13 I SDFM-1 Channel 4 Clock Input
FSIRXA_D1 14 I FSIRX-A Optional Additional Data Input
HIC_D6 15 I/O HIC Data 6
GPIO57 0, 4, 8, 12 66 I/O General-Purpose Input Output 57
SPIA_STE 1 I/O SPI-A Slave Transmit Enable (STE)
CLB_OUTPUTXBAR8 2 O CLB Output X-BAR Output 8
MCAN_RX 3 I CAN/CAN FD Receive
EQEP2_INDEX 5 I/O eQEP-2 Index
SCIB_RX 6 I SCI-B Receive Data
SD2_C1 7 I SDFM-2 Channel 1 Clock Input
SPIB_SOMI 9 I/O SPI-B Slave Out, Master In (SOMI)
I2CA_SCL 10 I/OD I2C-A Open-Drain Bidirectional Clock
EQEP1_B 11 I eQEP-1 Input B
FSIRXA_CLK 14 I FSIRX-A Input Clock
HIC_D4 15 I/O HIC Data 4
GPIO58 0, 4, 8, 12 67 I/O General-Purpose Input Output 58
OUTPUTXBAR1 5 O Output X-BAR Output 1
SPIB_CLK 6 I/O SPI-B Clock
SD2_D2 7 I SDFM-2 Channel 2 Data Input
LINA_TX 9 O LIN-A Transmit
CANA_TX 10 O CAN-A Transmit
EQEP1_STROBE 11 I/O eQEP-1 Strobe
SD2_C2 13 I SDFM-2 Channel 2 Clock Input
FSIRXA_D0 14 I FSIRX-A Primary Data Input
HIC_NRDY 15 O HIC Ready from device to host
GPIO59 0, 4, 8, 12 92 I/O General-Purpose Input Output 59
OUTPUTXBAR2 5 O Output X-BAR Output 2
SPIB_STE 6 I/O SPI-B Slave Transmit Enable (STE)
SD2_C2 7 I SDFM-2 Channel 2 Clock Input
LINA_RX 9 I LIN-A Receive
CANA_RX 10 I CAN-A Receive
EQEP1_INDEX 11 I/O eQEP-1 Index
SD2_C3 13 I SDFM-2 Channel 3 Clock Input
FSITXA_TDM_D1 14 I FSITX-A Time Division Multiplexed Additional Data Input
GPIO60 0, 4, 8, 12 44 I/O General-Purpose Input Output 60
MCAN_TX 3 O CAN/CAN FD Transmit
OUTPUTXBAR3 5 O Output X-BAR Output 3
SPIB_SIMO 6 I/O SPI-B Slave In, Master Out (SIMO)
SD2_D3 7 I SDFM-2 Channel 3 Data Input
SD2_C4 13 I SDFM-2 Channel 4 Clock Input
HIC_A0 15 I HIC Address 0
GPIO61 0, 4, 8, 12 91 I/O General-Purpose Input Output 61
MCAN_RX 3 I CAN/CAN FD Receive
OUTPUTXBAR4 5 O Output X-BAR Output 4
SPIB_SOMI 6 I/O SPI-B Slave Out, Master In (SOMI)
SD2_C3 7 I SDFM-2 Channel 3 Clock Input
CANA_RX 14 I CAN-A Receive
TEST, JTAG, AND RESET
TCK 60 45 36 36 28 I JTAG test clock with internal pullup.
TMS 62 47 38 38 30 I/O JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. This device does not have a TRSTn pin. An external pullup resistor (recommended 2.2 kΩ) on the TMS pin to VDDIO should be placed on the board to keep JTAG in reset during normal operation.
XRSn 2 5 3 3 3 I/OD Device Reset (in) and Watchdog Reset (out). During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRSn pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor between 2.2 kΩ and 10 kΩ should be placed between XRSn and VDDIO. If a capacitor is placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. This pin is an open-drain output with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device.
POWER AND GROUND
VDD 4, 46, 71, 87 8, 31, 53, 71 4, 27, 44, 59 4, 27, 44, 59 23, 36, 45 1.2-V Digital Logic Power Pins. See the Power Management Module (PMM) section for usage details.
VDDA 34 26 22 22 18 3.3-V Analog Power Pins. Place a minimum 2.2-µF decoupling capacitor on each pin. See the Power Management Module (PMM) section for usage details.
VDDIO 3, 47, 70, 88 7, 32, 52, 72 28, 43, 60 28, 43, 60 24, 35, 46 3.3-V Digital I/O Power Pins. See the Power Management Module (PMM) section for usage details.
VREGENZ 73 46 I Internal voltage regulator enable with internal pulldown. Tie low to VSS to enable internal VREG. Tie high to VDDIO to use an external supply. See the Power Management Module (PMM) section for usage details.
VSS 5, 45, 72, 86 9, 30, 55, 70 5, 26, 45, 58 5, 26, 45, 58 22, 37, 44 Digital Ground
VSSA 33 25 21 21 17 Analog Ground