SPRS945G January 2017 – January 2023 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
PRODUCTION DATA
MIN | MAX | UNIT | ||
---|---|---|---|---|
Mode 0 | ||||
tc(SDC)M0 | Cycle time, SDx_Cy | 5 * SYSCLK period | 256 * SYSCLK period | ns |
tw(SDCHL)M0 | Pulse duration, SDx_Cy high/low | 2 * SYSCLK period | 3 * SYSCLK period | ns |
tsu(SDDV-SDCH)M0 | Setup time, SDx_Dy valid before SDx_Cy goes high | 2 * SYSCLK period | ns | |
th(SDCH-SDD)M0 | Hold time, SDx_Dy wait after SDx_Cy goes high | 2 * SYSCLK period | ns | |
Mode 1 | ||||
tc(SDC)M1 | Cycle time, SDx_Cy | 10 * SYSCLK period | 256 * SYSCLK period | ns |
tw(SDCHL)M1 | Pulse duration, SDx_Cy high/low | 2 * SYSCLK period | 8 * SYSCLK period | ns |
tsu(SDDV-SDCL)M1 | Setup time, SDx_Dy valid before SDx_Cy goes low | 2 * SYSCLK period | ns | |
tsu(SDDV-SDCH)M1 | Setup time, SDx_Dy valid before SDx_Cy goes high | 2 * SYSCLK period | ns | |
th(SDCL-SDD)M1 | Hold time, SDx_Dy wait after SDx_Cy goes low | 2 * SYSCLK period | ns | |
th(SDCH-SDD)M1 | Hold time, SDx_Dy wait after SDx_Cy goes high | 2 * SYSCLK period | ns | |
Mode 2 | ||||
tc(SDD)M2 | Cycle time, SDx_Dy | Option unavailable | ||
tw(SDDH)M2 | Pulse duration, SDx_Dy high | |||
Mode 3 | ||||
tc(SDC)M3 | Cycle time, SDx_Cy | 5 * SYSCLK period | 256 * SYSCLK period | ns |
tw(SDCHL)M3 | Pulse duration, SDx_Cy high/low | 2 * SYSCLK period | 3 * SYSCLK period | ns |
tsu(SDDV-SDCH)M3 | Setup time, SDx_Dy valid before SDx_Cy goes high | 2 * SYSCLK period | ns | |
th(SDCH-SDD)M3 | Hold time, SDx_Dy wait after SDx_Cy goes high | 2 * SYSCLK period | ns |
The SDFM Synchronized GPIO (SYNC) option provides protection against SDFM module corruption due to occasional random noise glitches on the SDx_Cy pin that may result in a false comparator trip and filter output.
The SDFM Synchronized GPIO (SYNC) mode does not provide protection against persistent violations of the above timing requirements. Timing violations will result in data corruption proportional to the number of bits which violate the requirements.