SPRS945G January 2017 – January 2023 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
PRODUCTION DATA
SIGNAL NAME | DESCRIPTION | PIN TYPE | GPIO | 100 PZ | 64 PMQ | 64 PM | 56 RSH |
---|---|---|---|---|---|---|---|
VDD | 1.2-V Digital Logic Power Pins. TI recommends placing a decoupling capacitor near each VDD pin with a minimum total capacitance of approximately 20 µF. When not using the internal voltage regulator, the exact value of the decoupling capacitance should be determined by your system voltage regulation solution. | 4, 46, 71, 87 | 27, 4, 44, 59 | 27, 4, 44, 59 | 24, 41, 5, 53 | ||
VDDA | 3.3-V Analog Power Pins. Place a minimum 2.2-µF decoupling capacitor to VSSA on each pin. | 11, 34 | 22 | 22 | 20 | ||
VDDIO | 3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF decoupling capacitor on each pin. | 3, 47, 70, 88 | 28, 43, 60 | 28, 43, 60 | 25, 40, 54 | ||
VDDIO_SW | 3.3-V Supply pin for the internal DC-DC regulator. If the internal DC-DC regulator is used, a bulk input capacitance of 20-µF should be placed on this pin. Always tie this pin to the VDDIO pin. A ferrite bead may be used for isolation if desired but VDDIO_SW and VDDIO must be supplied from the same source. | 80 | 53 | 53 | 48 | ||
VSS | Digital Ground | 45, 5, 72, 86 | 26, 45, 5, 58 | 26, 45, 5, 58 | PAD | ||
VSSA | Analog Ground | 12, 33 | 21 | 21 | 19 | ||
VSS_SW | Internal DC-DC regulator ground. Always tie this pin to the VSS pin. | 82 | 55 | 55 | 50 |