SPRS945G January   2017  – January 2023 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1 Analog Signals
      2. 6.3.2 Digital Signals
      3. 6.3.3 Power and Ground
      4. 6.3.4 Test, JTAG, and Reset
    4. 6.4 Pin Multiplexing
      1. 6.4.1 GPIO Muxed Pins
      2. 6.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 6.4.3 GPIO Input X-BAR
      4. 6.4.4 GPIO Output X-BAR and ePWM X-BAR
    5. 6.5 Pins With Internal Pullup and Pulldown
    6. 6.6 Connections for Unused Pins
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 System Current Consumption (External Supply)
      2. 7.5.2 System Current Consumption (Internal VREG)
      3. 7.5.3 System Current Consumption (DCDC)
      4. 7.5.4 Operating Mode Test Description
      5. 7.5.5 Current Consumption Graphs
      6. 7.5.6 Reducing Current Consumption
        1. 7.5.6.1 Typical IDD Current Reduction per Disabled Peripheral (at 100-MHz SYSCLK)
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics
      1. 7.7.1 PZ Package
      2. 7.7.2 PM Package
      3. 7.7.3 RSH Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  System
      1. 7.9.1 Power Management Module (PMM)
        1. 7.9.1.1 Introduction
        2. 7.9.1.2 Overview
          1. 7.9.1.2.1 Power Rail Monitors
            1. 7.9.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 7.9.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 7.9.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 7.9.1.2.2 External Supervisor Usage
          3. 7.9.1.2.3 Delay Blocks
          4. 7.9.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 7.9.1.2.5 VREGENZ
          6. 7.9.1.2.6 Internal 1.2-V Switching Regulator (DC-DC)
            1. 7.9.1.2.6.1 PCB Layout and Component Guidelines
        3. 7.9.1.3 External Components
          1. 7.9.1.3.1 Decoupling Capacitors
            1. 7.9.1.3.1.1 VDDIO Decoupling
            2. 7.9.1.3.1.2 VDD Decoupling
        4. 7.9.1.4 Power Sequencing
          1. 7.9.1.4.1 Supply Pins Ganging
          2. 7.9.1.4.2 Signal Pins Power Sequence
          3. 7.9.1.4.3 Supply Pins Power Sequence
            1. 7.9.1.4.3.1 External VREG/VDD Mode Sequence
            2. 7.9.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 7.9.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 7.9.1.4.3.4 Supply Slew Rate
        5. 7.9.1.5 Power Management Module Electrical Data and Timing
          1. 7.9.1.5.1 Power Management Module Operating Conditions
          2. 7.9.1.5.2 Power Management Module Characteristics
          3.        Supply Voltages
      2. 7.9.2 Reset Timing
        1. 7.9.2.1 Reset Sources
        2. 7.9.2.2 Reset Electrical Data and Timing
          1. 7.9.2.2.1 Reset (XRSn) Timing Requirements
          2. 7.9.2.2.2 Reset (XRSn) Switching Characteristics
          3. 7.9.2.2.3 Reset Timing Diagram
      3. 7.9.3 Clock Specifications
        1. 7.9.3.1 Clock Sources
        2. 7.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 7.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 7.9.3.2.1.1 Input Clock Frequency
            2. 7.9.3.2.1.2 XTAL Oscillator Characteristics
            3. 7.9.3.2.1.3 X1 Timing Requirements
            4. 7.9.3.2.1.4 PLL Lock Times
          2. 7.9.3.2.2 Internal Clock Frequencies
            1. 7.9.3.2.2.1 Internal Clock Frequencies
          3. 7.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. 7.9.3.2.3.1 XCLKOUT Switching Characteristics
        3. 7.9.3.3 Input Clocks and PLLs
        4. 7.9.3.4 Crystal (XTAL) Oscillator
          1. 7.9.3.4.1 Introduction
          2. 7.9.3.4.2 Overview
            1. 7.9.3.4.2.1 Electrical Oscillator
              1. 7.9.3.4.2.1.1 Modes of Operation
                1. 7.9.3.4.2.1.1.1 Crystal Mode of Operation
                2. 7.9.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 7.9.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 7.9.3.4.2.2 Quartz Crystal
            3. 7.9.3.4.2.3 GPIO Modes of Operation
          3. 7.9.3.4.3 Functional Operation
            1. 7.9.3.4.3.1 ESR – Effective Series Resistance
            2. 7.9.3.4.3.2 Rneg – Negative Resistance
            3. 7.9.3.4.3.3 Start-up Time
            4. 7.9.3.4.3.4 DL – Drive Level
          4. 7.9.3.4.4 How to Choose a Crystal
          5. 7.9.3.4.5 Testing
          6. 7.9.3.4.6 Common Problems and Debug Tips
          7. 7.9.3.4.7 Crystal Oscillator Specifications
            1. 7.9.3.4.7.1 Crystal Oscillator Parameters
            2. 7.9.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 7.9.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 7.9.3.5 Internal Oscillators
          1. 7.9.3.5.1 INTOSC Characteristics
      4. 7.9.4 Flash Parameters
      5. 7.9.5 Emulation/JTAG
        1. 7.9.5.1 JTAG Electrical Data and Timing
          1. 7.9.5.1.1 JTAG Timing Requirements
          2. 7.9.5.1.2 JTAG Switching Characteristics
          3. 7.9.5.1.3 JTAG Timing Diagram
        2. 7.9.5.2 cJTAG Electrical Data and Timing
          1. 7.9.5.2.1 cJTAG Timing Requirements
          2. 7.9.5.2.2 cJTAG Switching Characteristics
          3. 7.9.5.2.3 cJTAG Timing Diagram
      6. 7.9.6 GPIO Electrical Data and Timing
        1. 7.9.6.1 GPIO – Output Timing
          1. 7.9.6.1.1 General-Purpose Output Switching Characteristics
        2. 7.9.6.2 GPIO – Input Timing
          1. 7.9.6.2.1 General-Purpose Input Timing Requirements
        3. 7.9.6.3 Sampling Window Width for Input Signals
      7. 7.9.7 Interrupts
        1. 7.9.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. 7.9.7.1.1 External Interrupt Timing Requirements
          2. 7.9.7.1.2 External Interrupt Switching Characteristics
          3. 7.9.7.1.3 Interrupt Timing Diagram
      8. 7.9.8 Low-Power Modes
        1. 7.9.8.1 Clock-Gating Low-Power Modes
        2. 7.9.8.2 Low-Power Mode Wake-up Timing
          1. 7.9.8.2.1 IDLE Mode Timing Requirements
          2. 7.9.8.2.2 IDLE Mode Switching Characteristics
          3. 7.9.8.2.3 IDLE Mode Timing Diagram
          4. 7.9.8.2.4 HALT Mode Timing Requirements
          5. 7.9.8.2.5 HALT Mode Switching Characteristics
          6. 7.9.8.2.6 HALT Mode Timing Diagram
    10. 7.10 Analog Peripherals
      1. 7.10.1 Analog-to-Digital Converter (ADC)
        1. 7.10.1.1 Result Register Mapping
        2. 7.10.1.2 ADC Configurability
          1. 7.10.1.2.1 Signal Mode
        3. 7.10.1.3 ADC Electrical Data and Timing
          1. 7.10.1.3.1 ADC Operating Conditions
          2. 7.10.1.3.2 ADC Characteristics
          3. 7.10.1.3.3 ADC Input Model
          4. 7.10.1.3.4 ADC Timing Diagrams
      2. 7.10.2 Programmable Gain Amplifier (PGA)
        1. 7.10.2.1 PGA Electrical Data and Timing
          1. 7.10.2.1.1 PGA Operating Conditions
          2. 7.10.2.1.2 PGA Characteristics
          3. 7.10.2.1.3 PGA Typical Characteristics Graphs
      3. 7.10.3 Temperature Sensor
        1. 7.10.3.1 Temperature Sensor Electrical Data and Timing
          1. 7.10.3.1.1 Temperature Sensor Characteristics
      4. 7.10.4 Buffered Digital-to-Analog Converter (DAC)
        1. 7.10.4.1 Buffered DAC Electrical Data and Timing
          1. 7.10.4.1.1 Buffered DAC Operating Conditions
          2. 7.10.4.1.2 Buffered DAC Electrical Characteristics
          3. 7.10.4.1.3 Buffered DAC Illustrative Graphs
          4. 7.10.4.1.4 Buffered DAC Typical Characteristics Graphs
      5. 7.10.5 Comparator Subsystem (CMPSS)
        1. 7.10.5.1 CMPSS Electrical Data and Timing
          1. 7.10.5.1.1 Comparator Electrical Characteristics
          2. 7.10.5.1.2 CMPSS DAC Static Electrical Characteristics
          3. 7.10.5.1.3 CMPSS Illustrative Graphs
    11. 7.11 Control Peripherals
      1. 7.11.1 Enhanced Capture (eCAP)
        1. 7.11.1.1 eCAP Electrical Data and Timing
          1. 7.11.1.1.1 eCAP Timing Requirements
          2. 7.11.1.1.2 eCAP Switching Characteristics
      2. 7.11.2 High-Resolution Capture Submodule (HRCAP6–HRCAP7)
        1. 7.11.2.1 HRCAP Electrical Data and Timing
          1. 7.11.2.1.1 HRCAP Switching Characteristics
      3. 7.11.3 Enhanced Pulse Width Modulator (ePWM)
        1. 7.11.3.1 Control Peripherals Synchronization
        2. 7.11.3.2 ePWM Electrical Data and Timing
          1. 7.11.3.2.1 ePWM Timing Requirements
          2. 7.11.3.2.2 ePWM Switching Characteristics
          3. 7.11.3.2.3 Trip-Zone Input Timing
            1. 7.11.3.2.3.1 Trip-Zone Input Timing Requirements
        3. 7.11.3.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 7.11.3.3.1 External ADC Start-of-Conversion Switching Characteristics
      4. 7.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 7.11.4.1 HRPWM Electrical Data and Timing
          1. 7.11.4.1.1 High-Resolution PWM Characteristics
      5. 7.11.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.11.5.1 eQEP Electrical Data and Timing
          1. 7.11.5.1.1 eQEP Timing Requirements
          2. 7.11.5.1.2 eQEP Switching Characteristics
      6. 7.11.6 Sigma-Delta Filter Module (SDFM)
        1. 7.11.6.1 SDFM Electrical Data and Timing
          1. 7.11.6.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
          2. 7.11.6.1.2 SDFM Timing Diagram
        2. 7.11.6.2 SDFM Electrical Data and Timing (Synchronized GPIO)
          1. 7.11.6.2.1 SDFM Timing Requirements When Using Synchronized GPIO (SYNC) Option
    12. 7.12 Communications Peripherals
      1. 7.12.1 Controller Area Network (CAN)
      2. 7.12.2 Inter-Integrated Circuit (I2C)
        1. 7.12.2.1 I2C Electrical Data and Timing
          1. 7.12.2.1.1 I2C Timing Requirements
          2. 7.12.2.1.2 I2C Switching Characteristics
          3. 7.12.2.1.3 I2C Timing Diagram
      3. 7.12.3 Power Management Bus (PMBus) Interface
        1. 7.12.3.1 PMBus Electrical Data and Timing
          1. 7.12.3.1.1 PMBus Electrical Characteristics
          2. 7.12.3.1.2 PMBus Fast Mode Switching Characteristics
          3. 7.12.3.1.3 PMBus Standard Mode Switching Characteristics
      4. 7.12.4 Serial Communications Interface (SCI)
      5. 7.12.5 Serial Peripheral Interface (SPI)
        1. 7.12.5.1 SPI Electrical Data and Timing
          1. 7.12.5.1.1 Non-High-Speed Master Mode Timings
            1. 7.12.5.1.1.1 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            2. 7.12.5.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            3. 7.12.5.1.1.3 SPI Master Mode Timing Requirements
          2. 7.12.5.1.2 Non-High-Speed Slave Mode Timings
            1. 7.12.5.1.2.1 SPI Slave Mode Switching Characteristics
            2. 7.12.5.1.2.2 SPI Slave Mode Timing Requirements
          3. 7.12.5.1.3 High-Speed Master Mode Timings
            1. 7.12.5.1.3.1 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 0)
            2. 7.12.5.1.3.2 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 1)
            3. 7.12.5.1.3.3 SPI High-Speed Master Mode Timing Requirements
          4. 7.12.5.1.4 High-Speed Slave Mode Timings
            1. 7.12.5.1.4.1 SPI High-Speed Slave Mode Switching Characteristics
            2. 7.12.5.1.4.2 SPI High-Speed Slave Mode Timing Requirements
      6. 7.12.6 Local Interconnect Network (LIN)
      7. 7.12.7 Fast Serial Interface (FSI)
        1. 7.12.7.1 FSI Transmitter
          1. 7.12.7.1.1 FSITX Electrical Data and Timing
            1. 7.12.7.1.1.1 FSITX Switching Characteristics
        2. 7.12.7.2 FSI Receiver
          1. 7.12.7.2.1 FSIRX Electrical Data and Timing
            1. 7.12.7.2.1.1 FSIRX Switching Characteristics
            2. 7.12.7.2.1.2 FSIRX Timing Requirements
        3. 7.12.7.3 FSI SPI Compatibility Mode
          1. 7.12.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 7.12.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
  8. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Memory
      1. 8.3.1 C28x Memory Map
      2. 8.3.2 Control Law Accelerator (CLA) ROM Memory Map
      3. 8.3.3 Flash Memory Map
      4. 8.3.4 Peripheral Registers Memory Map
      5. 8.3.5 Memory Types
        1. 8.3.5.1 Dedicated RAM (Mx RAM)
        2. 8.3.5.2 Local Shared RAM (LSx RAM)
        3. 8.3.5.3 Global Shared RAM (GSx RAM)
        4. 8.3.5.4 CLA Message RAM (CLA MSGRAM)
    4. 8.4  Identification
    5. 8.5  Bus Architecture – Peripheral Connectivity
    6. 8.6  C28x Processor
      1. 8.6.1 Embedded Real-Time Analysis and Diagnostic (ERAD)
      2. 8.6.2 Floating-Point Unit (FPU)
      3. 8.6.3 Trigonometric Math Unit (TMU)
      4. 8.6.4 Viterbi, Complex Math and CRC Unit (VCU-I)
    7. 8.7  Control Law Accelerator (CLA)
    8. 8.8  Direct Memory Access (DMA)
    9. 8.9  Boot ROM and Peripheral Booting
      1. 8.9.1 Configuring Alternate Boot Mode Select Pins
      2. 8.9.2 Configuring Alternate Boot Mode Options
      3. 8.9.3 GPIO Assignments
    10. 8.10 Dual Code Security Module
    11. 8.11 Watchdog
    12. 8.12 Configurable Logic Block (CLB)
    13. 8.13 Functional Safety
  9. 9 Applications, Implementation, and Layout
    1. 9.1 Key Device Features
    2. 9.2 Application Information
      1. 9.2.1 Typical Application
        1. 9.2.1.1 Server Telecom Power Supply Unit (PSU)
          1. 9.2.1.1.1 System Block Diagram
          2. 9.2.1.1.2 Server and Telecom PSU Resources
        2. 9.2.1.2 Single-Phase Online UPS
          1. 9.2.1.2.1 System Block Diagram
          2. 9.2.1.2.2 Single phase online UPS Resources
        3. 9.2.1.3 Solar Micro Inverter
          1. 9.2.1.3.1 System Block Diagram
          2. 9.2.1.3.2 Solar Micro Inverter Resources
        4. 9.2.1.4 EV Charging Station Power Module
          1. 9.2.1.4.1 System Block Diagram
          2. 9.2.1.4.2 EV charging station power module Resources
        5. 9.2.1.5 Servo Drive Control Module
          1. 9.2.1.5.1 System Block Diagram
          2. 9.2.1.5.2 Servo Drive Control Module Resources
  10. 10Device and Documentation Support
    1. 10.1 Device and Development Support Tool Nomenclature
    2. 10.2 Markings
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.2 Pin Attributes

Table 6-1 Pin Attributes
SIGNAL NAME MUX POSITION 100 PZ 64 PMQ 64 PM 56 RSH PIN TYPE DESCRIPTION
ANALOG
A0 23 15 15 13 I ADC-A Input 0
B15 I ADC-B Input 15
C15 I ADC-C Input 15
DACA_OUT O Buffered DAC-A Output
AIO231 I Digital Input-231 on ADC Pin
A1 22 14 14 12 I ADC-A Input 1
DACB_OUT O Buffered DAC-B Output
AIO232 I Digital Input-232 on ADC Pin
A10 40 25 25 23 I ADC-A Input 10
B1 I ADC-B Input 1
C10 I ADC-C Input 10
PGA7_OF O PGA-7 Output Filter (Optional)
CMP7_HP0 I CMPSS-7 High Comparator Positive Input 0
CMP7_LP0 I CMPSS-7 Low Comparator Positive Input 0
AIO230 I Digital Input-230 on ADC Pin
A2 9 9 9 8 I ADC-A Input 2
B6 I ADC-B Input 6
PGA1_OF O PGA-1 Output Filter (Optional)
CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0
CMP1_LP0 I CMPSS-1 Low Comparator Positive Input 0
AIO224 I Digital Input-224 on ADC Pin
A3 10 I ADC-A Input 3
CMP1_HP3 I CMPSS-1 High Comparator Positive Input 3
CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0
CMP1_LP3 I CMPSS-1 Low Comparator Positive Input 3
CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0
AIO233 I Digital Input-233 on ADC Pin
A4 36 23 23 21 I ADC-A Input 4
B8 I ADC-B Input 8
PGA2_OF O PGA-2 Output Filter (Optional)
CMP2_HP0 I CMPSS-2 High Comparator Positive Input 0
CMP2_LP0 I CMPSS-2 Low Comparator Positive Input 0
AIO225 I Digital Input-225 on ADC Pin
A5 35 I ADC-A Input 5
CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3
CMP2_HN0 I CMPSS-2 High Comparator Negative Input 0
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3
CMP2_LN0 I CMPSS-2 Low Comparator Negative Input 0
AIO234 I Digital Input-234 on ADC Pin
A6 6 6 6 I ADC-A Input 6
PGA5_OF O PGA-5 Output Filter (Optional)
CMP5_HP0 I CMPSS-5 High Comparator Positive Input 0
CMP5_LP0 I CMPSS-5 Low Comparator Positive Input 0
AIO228 I Digital Input-228 on ADC Pin
A8 37 I ADC-A Input 8
PGA6_OF O PGA-6 Output Filter (Optional)
CMP6_HP0 I CMPSS-6 High Comparator Positive Input 0
CMP6_LP0 I CMPSS-6 Low Comparator Positive Input 0
AIO229 I Digital Input-229 on ADC Pin
A9 38 I ADC-A Input 9
CMP6_HP3 I CMPSS-6 High Comparator Positive Input 3
CMP6_HN0 I CMPSS-6 High Comparator Negative Input 0
CMP6_LP3 I CMPSS-6 Low Comparator Positive Input 3
CMP6_LN0 I CMPSS-6 Low Comparator Negative Input 0
AIO236 I Digital Input-236 on ADC Pin
B0 41 I ADC-B Input 0
CMP7_HP3 I CMPSS-7 High Comparator Positive Input 3
CMP7_HN0 I CMPSS-7 High Comparator Negative Input 0
CMP7_LP3 I CMPSS-7 Low Comparator Positive Input 3
CMP7_LN0 I CMPSS-7 Low Comparator Negative Input 0
AIO241 I Digital Input-241 on ADC Pin
B2 7 7 7 6 I ADC-B Input 2
C6 I ADC-C Input 6
PGA3_OF O PGA-3 Output Filter (Optional)
CMP3_HP0 I CMPSS-3 High Comparator Positive Input 0
CMP3_LP0 I CMPSS-3 Low Comparator Positive Input 0
AIO226 I Digital Input-226 on ADC Pin
B3 8 8 8 7 I ADC-B Input 3
VDAC I Optional external reference voltage for on-chip DACs. There is a 100-pF capacitor to VSSA on this pin whether used for ADC input or DAC reference which cannot be disabled. If this pin is being used as a reference for the on-chip DACs, place at least a 1-µF capacitor on this pin.
CMP3_HP3 I CMPSS-3 High Comparator Positive Input 3
CMP3_HN0 I CMPSS-3 High Comparator Negative Input 0
CMP3_LP3 I CMPSS-3 Low Comparator Positive Input 3
CMP3_LN0 I CMPSS-3 Low Comparator Negative Input 0
AIO242 I Digital Input-242 on ADC Pin
B4 39 24 24 22 I ADC-B Input 4
C8 I ADC-C Input 8
PGA4_OF O PGA-4 Output Filter (Optional)
CMP4_HP0 I CMPSS-4 High Comparator Positive Input 0
CMP4_LP0 I CMPSS-4 Low Comparator Positive Input 0
AIO227 I Digital Input-227 on ADC Pin
C0 19 12 12 10 I ADC-C Input 0
CMP1_HP1 I CMPSS-1 High Comparator Positive Input 1
CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1
CMP1_LP1 I CMPSS-1 Low Comparator Positive Input 1
CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1
AIO237 I Digital Input-237 on ADC Pin
C1 29 18 18 16 I ADC-C Input 1
CMP2_HP1 I CMPSS-2 High Comparator Positive Input 1
CMP2_HN1 I CMPSS-2 High Comparator Negative Input 1
CMP2_LP1 I CMPSS-2 Low Comparator Positive Input 1
CMP2_LN1 I CMPSS-2 Low Comparator Negative Input 1
AIO238 I Digital Input-238 on ADC Pin
C14 44 I ADC-C Input 14
CMP7_HP1 I CMPSS-7 High Comparator Positive Input 1
CMP7_HN1 I CMPSS-7 High Comparator Negative Input 1
CMP7_LP1 I CMPSS-7 Low Comparator Positive Input 1
CMP7_LN1 I CMPSS-7 Low Comparator Negative Input 1
AIO246 I Digital Input-246 on ADC Pin
C2 21 13 13 11 I ADC-C Input 2
CMP3_HP1 I CMPSS-3 High Comparator Positive Input 1
CMP3_HN1 I CMPSS-3 High Comparator Negative Input 1
CMP3_LP1 I CMPSS-3 Low Comparator Positive Input 1
CMP3_LN1 I CMPSS-3 Low Comparator Negative Input 1
AIO244 I Digital Input-244 on ADC Pin
C3 31 19 19 17 I ADC-C Input 3
CMP4_HP1 I CMPSS-4 High Comparator Positive Input 1
CMP4_HN1 I CMPSS-4 High Comparator Negative Input 1
CMP4_LP1 I CMPSS-4 Low Comparator Positive Input 1
CMP4_LN1 I CMPSS-4 Low Comparator Negative Input 1
AIO245 I Digital Input-245 on ADC Pin
C4 17 11 11 I ADC-C Input 4
CMP5_HP1 I CMPSS-5 High Comparator Positive Input 1
CMP5_HN1 I CMPSS-5 High Comparator Negative Input 1
CMP5_LP1 I CMPSS-5 Low Comparator Positive Input 1
CMP5_LN1 I CMPSS-5 Low Comparator Negative Input 1
AIO239 I Digital Input-239 on ADC Pin
C5 28 I ADC-C Input 5
CMP6_HP1 I CMPSS-6 High Comparator Positive Input 1
CMP6_HN1 I CMPSS-6 High Comparator Negative Input 1
CMP6_LP1 I CMPSS-6 Low Comparator Positive Input 1
CMP6_LN1 I CMPSS-6 Low Comparator Negative Input 1
AIO240 I Digital Input-240 on ADC Pin
PGA1_GND 14 10 10 9 I PGA-1 Ground
PGA1_IN 18 12 12 10 I PGA-1 Input
CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2
CMP1_LP2 I CMPSS-1 Low Comparator Positive Input 2
PGA2_GND 32 20 20 18 I PGA-2 Ground
PGA2_IN 30 18 18 16 I PGA-2 Input
CMP2_HP2 I CMPSS-2 High Comparator Positive Input 2
CMP2_LP2 I CMPSS-2 Low Comparator Positive Input 2
PGA3_GND 15 10 10 9 I PGA-3 Ground
PGA3_IN 20 13 13 11 I PGA-3 Input
CMP3_HP2 I CMPSS-3 High Comparator Positive Input 2
CMP3_LP2 I CMPSS-3 Low Comparator Positive Input 2
PGA4_GND 32 20 20 18 I PGA-4 Ground
PGA4_IN 31 19 19 17 I PGA-4 Input
CMP4_HP2 I CMPSS-4 High Comparator Positive Input 2
CMP4_LP2 I CMPSS-4 Low Comparator Positive Input 2
PGA5_GND 13 10 10 9 I PGA-5 Ground
PGA5_IN 16 11 11 I PGA-5 Input
CMP5_HP2 I CMPSS-5 High Comparator Positive Input 2
CMP5_LP2 I CMPSS-5 Low Comparator Positive Input 2
PGA6_GND 32 20 20 18 I PGA-6 Ground
PGA6_IN 28 I PGA-6 Input
CMP6_HP2 I CMPSS-6 High Comparator Positive Input 2
CMP6_LP2 I CMPSS-6 Low Comparator Positive Input 2
PGA7_GND 42 I PGA-7 Ground
PGA7_IN 43 I PGA-7 Input
CMP7_HP2 I CMPSS-7 High Comparator Positive Input 2
CMP7_LP2 I CMPSS-7 Low Comparator Positive Input 2
VREFHIA 25 16 16 14 I/O ADC-A High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHIA and VREFLOA pins. Do not load this pin externally in either internal or external reference mode.
VREFHIB 24 16 16 14 I/O ADC-B High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHIB and VREFLOB pins. Do not load this pin externally in either internal or external reference mode.
VREFHIC 24 16 16 14 I/O ADC-C High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHIC and VREFLOC pins. Do not load this pin externally in either internal or external reference mode.
VREFLOA 27 17 17 15 I ADC-A Low Reference
VREFLOB 26 17 17 15 I ADC-B Low Reference
VREFLOC 26 17 17 15 I ADC-C Low Reference
GPIO
GPIO0 0, 4, 8, 12 79 52 52 47 I/O General-Purpose Input Output 0
EPWM1_A 1 O ePWM-1 Output A
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
GPIO1 0, 4, 8, 12 78 51 51 46 I/O General-Purpose Input Output 1
EPWM1_B 1 O ePWM-1 Output B
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
GPIO2 0, 4, 8, 12 77 50 50 45 I/O General-Purpose Input Output 2
EPWM2_A 1 O ePWM-2 Output A
OUTPUTXBAR1 5 O Output X-BAR Output 1
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
SCIA_TX 9 O SCI-A Transmit Data
FSIRXA_D1 10 I FSIRX-A Optional Additional Data Input
GPIO3 0, 4, 8, 12 76 49 49 44 I/O General-Purpose Input Output 3
EPWM2_B 1 O ePWM-2 Output B
OUTPUTXBAR2 2, 5 O Output X-BAR Output 2
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
SPIA_CLK 7 I/O SPI-A Clock
SCIA_RX 9 I SCI-A Receive Data
FSIRXA_D0 10 I FSIRX-A Primary Data Input
GPIO4 0, 4, 8, 12 75 48 48 43 I/O General-Purpose Input Output 4
EPWM3_A 1 O ePWM-3 Output A
OUTPUTXBAR3 5 O Output X-BAR Output 3
CANA_TX 6 O CAN-A Transmit
FSIRXA_CLK 10 I FSIRX-A Input Clock
GPIO5 0, 4, 8, 12 89 61 61 55 I/O General-Purpose Input Output 5
EPWM3_B 1 O ePWM-3 Output B
OUTPUTXBAR3 3 O Output X-BAR Output 3
CANA_RX 6 I CAN-A Receive
SPIA_STE 7 I/O SPI-A Slave Transmit Enable (STE)
FSITXA_D1 9 O FSITX-A Optional Additional Data Output
GPIO6 0, 4, 8, 12 97 64 64 1 I/O General-Purpose Input Output 6
EPWM4_A 1 O ePWM-4 Output A
OUTPUTXBAR4 2 O Output X-BAR Output 4
SYNCOUT 3 O External ePWM Synchronization Pulse
EQEP1_A 5 I eQEP-1 Input A
CANB_TX 6 O CAN-B Transmit
SPIB_SOMI 7 I/O SPI-B Slave Out, Master In (SOMI)
FSITXA_D0 9 O FSITX-A Primary Data Output
GPIO7 0, 4, 8, 12 84 57 57 52 I/O General-Purpose Input Output 7
EPWM4_B 1 O ePWM-4 Output B
OUTPUTXBAR5 3 O Output X-BAR Output 5
EQEP1_B 5 I eQEP-1 Input B
CANB_RX 6 I CAN-B Receive
SPIB_SIMO 7 I/O SPI-B Slave In, Master Out (SIMO)
FSITXA_CLK 9 O FSITX-A Output Clock
GPIO8 0, 4, 8, 12 74 47 47 42 I/O General-Purpose Input Output 8
EPWM5_A 1 O ePWM-5 Output A
CANB_TX 2 O CAN-B Transmit
ADCSOCAO 3 O ADC Start of Conversion A Output for External ADC (from ePWM modules)
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SCIA_TX 6 O SCI-A Transmit Data
SPIA_SIMO 7 I/O SPI-A Slave In, Master Out (SIMO)
I2CA_SCL 9 I/OD I2C-A Open-Drain Bidirectional Clock
FSITXA_D1 10 O FSITX-A Optional Additional Data Output
GPIO9 0, 4, 8, 12 90 62 62 56 I/O General-Purpose Input Output 9
EPWM5_B 1 O ePWM-5 Output B
SCIB_TX 2 O SCI-B Transmit Data
OUTPUTXBAR6 3 O Output X-BAR Output 6
EQEP1_INDEX 5 I/O eQEP-1 Index
SCIA_RX 6 I SCI-A Receive Data
SPIA_CLK 7 I/O SPI-A Clock
FSITXA_D0 10 O FSITX-A Primary Data Output
GPIO10 0, 4, 8, 12 93 63 63 I/O General-Purpose Input Output 10
EPWM6_A 1 O ePWM-6 Output A
CANB_RX 2 I CAN-B Receive
ADCSOCBO 3 O ADC Start of Conversion B Output for External ADC (from ePWM modules)
EQEP1_A 5 I eQEP-1 Input A
SCIB_TX 6 O SCI-B Transmit Data
SPIA_SOMI 7 I/O SPI-A Slave Out, Master In (SOMI)
I2CA_SDA 9 I/OD I2C-A Open-Drain Bidirectional Data
FSITXA_CLK 10 O FSITX-A Output Clock
GPIO11 0, 4, 8, 12 52 31 31 28 I/O General-Purpose Input Output 11
EPWM6_B 1 O ePWM-6 Output B
SCIB_RX 2, 6 I SCI-B Receive Data
OUTPUTXBAR7 3 O Output X-BAR Output 7
EQEP1_B 5 I eQEP-1 Input B
SPIA_STE 7 I/O SPI-A Slave Transmit Enable (STE)
FSIRXA_D1 9 I FSIRX-A Optional Additional Data Input
GPIO12 0, 4, 8, 12 51 30 27 I/O General-Purpose Input Output 12
EPWM7_A 1 O ePWM-7 Output A
CANB_TX 2 O CAN-B Transmit
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SCIB_TX 6 O SCI-B Transmit Data
PMBUSA_CTL 7 I PMBus-A Control Signal
FSIRXA_D0 9 I FSIRX-A Primary Data Input
GPIO13 0, 4, 8, 12 50 29 26 I/O General-Purpose Input Output 13
EPWM7_B 1 O ePWM-7 Output B
CANB_RX 2 I CAN-B Receive
EQEP1_INDEX 5 I/O eQEP-1 Index
SCIB_RX 6 I SCI-B Receive Data
PMBUSA_ALERT 7 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
FSIRXA_CLK 9 I FSIRX-A Input Clock
GPIO14 0, 4, 8, 12 96 I/O General-Purpose Input Output 14
EPWM8_A 1 O ePWM-8 Output A
SCIB_TX 2 O SCI-B Transmit Data
OUTPUTXBAR3 6 O Output X-BAR Output 3
PMBUSA_SDA 7 I/OD PMBus-A Open-Drain Bidirectional Data
SPIB_CLK 9 I/O SPI-B Clock
EQEP2_A 10 I eQEP-2 Input A
GPIO15 0, 4, 8, 12 95 I/O General-Purpose Input Output 15
EPWM8_B 1 O ePWM-8 Output B
SCIB_RX 2 I SCI-B Receive Data
OUTPUTXBAR4 6 O Output X-BAR Output 4
PMBUSA_SCL 7 I/OD PMBus-A Open-Drain Bidirectional Clock
SPIB_STE 9 I/O SPI-B Slave Transmit Enable (STE)
EQEP2_B 10 I eQEP-2 Input B
GPIO16 0, 4, 8, 12 54 33 33 30 I/O General-Purpose Input Output 16
SPIA_SIMO 1 I/O SPI-A Slave In, Master Out (SIMO)
CANB_TX 2 O CAN-B Transmit
OUTPUTXBAR7 3 O Output X-BAR Output 7
EPWM5_A 5 O ePWM-5 Output A
SCIA_TX 6 O SCI-A Transmit Data
SD1_D1 7 I SDFM-1 Channel 1 Data Input
EQEP1_STROBE 9 I/O eQEP-1 Strobe
PMBUSA_SCL 10 I/OD PMBus-A Open-Drain Bidirectional Clock
XCLKOUT 11 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
GPIO17 0, 4, 8, 12 55 34 34 31 I/O General-Purpose Input Output 17
SPIA_SOMI 1 I/O SPI-A Slave Out, Master In (SOMI)
CANB_RX 2 I CAN-B Receive
OUTPUTXBAR8 3 O Output X-BAR Output 8
EPWM5_B 5 O ePWM-5 Output B
SCIA_RX 6 I SCI-A Receive Data
SD1_C1 7 I SDFM-1 Channel 1 Clock Input
EQEP1_INDEX 9 I/O eQEP-1 Index
PMBUSA_SDA 10 I/OD PMBus-A Open-Drain Bidirectional Data
GPIO18_X2 0, 4, 8, 12 68 41 41 38 I/O General-Purpose Input Output 18. This pin and its digital mux options can only be used when the system is clocked by INTOSC and X1 has an external pulldown resistor (recommended 1 kΩ).
SPIA_CLK 1 I/O SPI-A Clock
SCIB_TX 2 O SCI-B Transmit Data
CANA_RX 3 I CAN-A Receive
EPWM6_A 5 O ePWM-6 Output A
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
SD1_D2 7 I SDFM-1 Channel 2 Data Input
EQEP2_A 9 I eQEP-2 Input A
PMBUSA_CTL 10 I PMBus-A Control Signal
XCLKOUT 11 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
X2 ALT I/O Crystal oscillator output
GPIO20 0 I/O General-Purpose Input Output 20
GPIO21 0 I/O General-Purpose Input Output 21
GPIO22_VFBSW 0, 4, 8, 12 83 56 56 51 I/O General-Purpose Input Output 22. This pin is configured for DC-DC mode by default. If the internal DC-DC regulator is not used, this can be configured as General-Purpose Input Output 22 by disabling DC-DC(DCDCCTL.DCDCEN = 0) and clearing their bits in GPAAMSEL register.
EQEP1_STROBE 1 I/O eQEP-1 Strobe
SCIB_TX 3 O SCI-B Transmit Data
SPIB_CLK 6 I/O SPI-B Clock
SD1_D4 7 I SDFM-1 Channel 4 Data Input
LINA_TX 9 O LIN-A Transmit
VFBSW(1) ALT - Internal DC-DC regulator feedback signal. If the internal DC-DC regulator is used(DCDCCTL.DCDCEN = 1), tie this pin to the node where L(VSW) connects to the VDD rail (as close as possible to the device).
GPIO23_VSW 0 81 54 54 49 I/O General-Purpose Input Output 23. This pin is configured for DC-DC mode by default. If the internal DC-DC regulator is not used, this can be configured as General-Purpose Input Output 23 by disabling DC-DC(DCDCCTL.DCDCEN = 0) and clearing their bits in GPAAMSEL register. This pin has an internal capacitance of approximately 100 pF. TI Recommends using an alternate GPIO, or using this pin only for applications which do not require a fast switching response.
VSW(1) ALT - Switching output of the internal DC-DC regulator(when DCDCCTL.DCDCEN = 1)
GPIO24 0, 4, 8, 12 56 35 35 32 I/O General-Purpose Input Output 24
OUTPUTXBAR1 1 O Output X-BAR Output 1
EQEP2_A 2 I eQEP-2 Input A
EPWM8_A 5 O ePWM-8 Output A
SPIB_SIMO 6 I/O SPI-B Slave In, Master Out (SIMO)
SD1_D1 7 I SDFM-1 Channel 1 Data Input
PMBUSA_SCL 10 I/OD PMBus-A Open-Drain Bidirectional Clock
SCIA_TX 11 O SCI-A Transmit Data
ERRORSTS 13 O Active-low Error Status Output. If you want an error state to be asserted during power up or during a fault with the ERRORSTS signal itself, an external pulldown resistor may be used. A pullup resistor may be used if you do not want an error state asserted for the conditions mentioned.
GPIO25 0, 4, 8, 12 57 I/O General-Purpose Input Output 25
OUTPUTXBAR2 1 O Output X-BAR Output 2
EQEP2_B 2 I eQEP-2 Input B
SPIB_SOMI 6 I/O SPI-B Slave Out, Master In (SOMI)
SD1_C1 7 I SDFM-1 Channel 1 Clock Input
FSITXA_D1 9 O FSITX-A Optional Additional Data Output
PMBUSA_SDA 10 I/OD PMBus-A Open-Drain Bidirectional Data
SCIA_RX 11 I SCI-A Receive Data
GPIO26 0, 4, 8, 12 58 I/O General-Purpose Input Output 26
OUTPUTXBAR3 1, 5 O Output X-BAR Output 3
EQEP2_INDEX 2 I/O eQEP-2 Index
SPIB_CLK 6 I/O SPI-B Clock
SD1_D2 7 I SDFM-1 Channel 2 Data Input
FSITXA_D0 9 O FSITX-A Primary Data Output
PMBUSA_CTL 10 I PMBus-A Control Signal
I2CA_SDA 11 I/OD I2C-A Open-Drain Bidirectional Data
GPIO27 0, 4, 8, 12 59 I/O General-Purpose Input Output 27
OUTPUTXBAR4 1, 5 O Output X-BAR Output 4
EQEP2_STROBE 2 I/O eQEP-2 Strobe
SPIB_STE 6 I/O SPI-B Slave Transmit Enable (STE)
SD1_C2 7 I SDFM-1 Channel 2 Clock Input
FSITXA_CLK 9 O FSITX-A Output Clock
PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
I2CA_SCL 11 I/OD I2C-A Open-Drain Bidirectional Clock
GPIO28 0, 4, 8, 12 1 2 2 3 I/O General-Purpose Input Output 28
SCIA_RX 1 I SCI-A Receive Data
EPWM7_A 3 O ePWM-7 Output A
OUTPUTXBAR5 5 O Output X-BAR Output 5
EQEP1_A 6 I eQEP-1 Input A
SD1_D3 7 I SDFM-1 Channel 3 Data Input
EQEP2_STROBE 9 I/O eQEP-2 Strobe
LINA_TX 10 O LIN-A Transmit
SPIB_CLK 11 I/O SPI-B Clock
ERRORSTS 13 O Active-low Error Status Output. If you want an error state to be asserted during power up or during a fault with the ERRORSTS signal itself, an external pulldown resistor may be used. A pullup resistor may be used if you do not want an error state asserted for the conditions mentioned.
GPIO29 0, 4, 8, 12 100 1 1 2 I/O General-Purpose Input Output 29
SCIA_TX 1 O SCI-A Transmit Data
EPWM7_B 3 O ePWM-7 Output B
OUTPUTXBAR6 5 O Output X-BAR Output 6
EQEP1_B 6 I eQEP-1 Input B
SD1_C3 7 I SDFM-1 Channel 3 Clock Input
EQEP2_INDEX 9 I/O eQEP-2 Index
LINA_RX 10 I LIN-A Receive
SPIB_STE 11 I/O SPI-B Slave Transmit Enable (STE)
ERRORSTS 13 O Active-low Error Status Output. If you want an error state to be asserted during power up or during a fault with the ERRORSTS signal itself, an external pulldown resistor may be used. A pullup resistor may be used if you do not want an error state asserted for the conditions mentioned.
GPIO30 0, 4, 8, 12 98 I/O General-Purpose Input Output 30
CANA_RX 1 I CAN-A Receive
SPIB_SIMO 3 I/O SPI-B Slave In, Master Out (SIMO)
OUTPUTXBAR7 5 O Output X-BAR Output 7
EQEP1_STROBE 6 I/O eQEP-1 Strobe
SD1_D4 7 I SDFM-1 Channel 4 Data Input
GPIO31 0, 4, 8, 12 99 I/O General-Purpose Input Output 31
CANA_TX 1 O CAN-A Transmit
SPIB_SOMI 3 I/O SPI-B Slave Out, Master In (SOMI)
OUTPUTXBAR8 5 O Output X-BAR Output 8
EQEP1_INDEX 6 I/O eQEP-1 Index
SD1_C4 7 I SDFM-1 Channel 4 Clock Input
FSIRXA_D1 9 I FSIRX-A Optional Additional Data Input
GPIO32 0, 4, 8, 12 64 40 40 37 I/O General-Purpose Input Output 32
I2CA_SDA 1 I/OD I2C-A Open-Drain Bidirectional Data
SPIB_CLK 3 I/O SPI-B Clock
EPWM8_B 5 O ePWM-8 Output B
LINA_TX 6 O LIN-A Transmit
SD1_D3 7 I SDFM-1 Channel 3 Data Input
FSIRXA_D0 9 I FSIRX-A Primary Data Input
CANA_TX 10 O CAN-A Transmit
GPIO33 0, 4, 8, 12 53 32 32 29 I/O General-Purpose Input Output 33
I2CA_SCL 1 I/OD I2C-A Open-Drain Bidirectional Clock
SPIB_STE 3 I/O SPI-B Slave Transmit Enable (STE)
OUTPUTXBAR4 5 O Output X-BAR Output 4
LINA_RX 6 I LIN-A Receive
SD1_C3 7 I SDFM-1 Channel 3 Clock Input
FSIRXA_CLK 9 I FSIRX-A Input Clock
CANA_RX 10 I CAN-A Receive
GPIO34 0, 4, 8, 12 94 I/O General-Purpose Input Output 34
OUTPUTXBAR1 1 O Output X-BAR Output 1
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
GPIO35 0, 4, 8, 12 63 39 39 36 I/O General-Purpose Input Output 35
SCIA_RX 1 I SCI-A Receive Data
I2CA_SDA 3 I/OD I2C-A Open-Drain Bidirectional Data
CANA_RX 5 I CAN-A Receive
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
LINA_RX 7 I LIN-A Receive
EQEP1_A 9 I eQEP-1 Input A
PMBUSA_CTL 10 I PMBus-A Control Signal
TDI 15 I JTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input.
GPIO37 0, 4, 8, 12 61 37 37 34 I/O General-Purpose Input Output 37
OUTPUTXBAR2 1 O Output X-BAR Output 2
I2CA_SCL 3 I/OD I2C-A Open-Drain Bidirectional Clock
SCIA_TX 5 O SCI-A Transmit Data
CANA_TX 6 O CAN-A Transmit
LINA_TX 7 O LIN-A Transmit
EQEP1_B 9 I eQEP-1 Input B
PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
TDO 15 O JTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input.
GPIO39 0, 4, 8, 12 91 I/O General-Purpose Input Output 39
CANB_RX 6 I CAN-B Receive
FSIRXA_CLK 7 I FSIRX-A Input Clock
GPIO40 0, 4, 8, 12 85 I/O General-Purpose Input Output 40
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
FSIRXA_D0 7 I FSIRX-A Primary Data Input
SCIB_TX 9 O SCI-B Transmit Data
EQEP1_A 10 I eQEP-1 Input A
GPIO41 0 I/O General-Purpose Input Output 41
GPIO42 0 I/O General-Purpose Input Output 42
GPIO43 0 I/O General-Purpose Input Output 43
GPIO44 0 I/O General-Purpose Input Output 44
GPIO45 0 I/O General-Purpose Input Output 45
GPIO46 0 I/O General-Purpose Input Output 46
GPIO47 0 I/O General-Purpose Input Output 47
GPIO48 0 I/O General-Purpose Input Output 48
GPIO49 0 I/O General-Purpose Input Output 49
GPIO50 0 I/O General-Purpose Input Output 50
GPIO51 0 I/O General-Purpose Input Output 51
GPIO52 0 I/O General-Purpose Input Output 52
GPIO53 0 I/O General-Purpose Input Output 53
GPIO54 0 I/O General-Purpose Input Output 54
GPIO55 0 I/O General-Purpose Input Output 55
GPIO56 0, 4, 8, 12 65 I/O General-Purpose Input Output 56
SPIA_CLK 1 I/O SPI-A Clock
EQEP2_STROBE 5 I/O eQEP-2 Strobe
SCIB_TX 6 O SCI-B Transmit Data
SD1_D3 7 I SDFM-1 Channel 3 Data Input
SPIB_SIMO 9 I/O SPI-B Slave In, Master Out (SIMO)
EQEP1_A 11 I eQEP-1 Input A
GPIO57 0, 4, 8, 12 66 I/O General-Purpose Input Output 57
SPIA_STE 1 I/O SPI-A Slave Transmit Enable (STE)
EQEP2_INDEX 5 I/O eQEP-2 Index
SCIB_RX 6 I SCI-B Receive Data
SD1_C3 7 I SDFM-1 Channel 3 Clock Input
SPIB_SOMI 9 I/O SPI-B Slave Out, Master In (SOMI)
EQEP1_B 11 I eQEP-1 Input B
GPIO58 0, 4, 8, 12 67 I/O General-Purpose Input Output 58
OUTPUTXBAR1 5 O Output X-BAR Output 1
SPIB_CLK 6 I/O SPI-B Clock
SD1_D4 7 I SDFM-1 Channel 4 Data Input
LINA_TX 9 O LIN-A Transmit
CANB_TX 10 O CAN-B Transmit
EQEP1_STROBE 11 I/O eQEP-1 Strobe
GPIO59 0, 4, 8, 12 92 I/O General-Purpose Input Output 59
OUTPUTXBAR2 5 O Output X-BAR Output 2
SPIB_STE 6 I/O SPI-B Slave Transmit Enable (STE)
SD1_C4 7 I SDFM-1 Channel 4 Clock Input
LINA_RX 9 I LIN-A Receive
CANB_RX 10 I CAN-B Receive
EQEP1_INDEX 11 I/O eQEP-1 Index
TEST, JTAG, AND RESET
FLT1 49 30 I/O Flash test pin 1. Reserved for TI. Must be left unconnected.
FLT2 48 29 I/O Flash test pin 2. Reserved for TI. Must be left unconnected.
TCK 60 36 36 33 I JTAG test clock with internal pullup.
TMS 62 38 38 35 I/O JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. This device does not have a TRSTn pin. An external pullup resistor (recommended 2.2 kΩ) on the TMS pin to VDDIO should be placed on the board to keep JTAG in reset during normal operation.
VREGENZ 73 46 46 I Internal voltage regulator enable with internal pulldown. Tie directly to VSS (low) to enable the internal VREG. Tie directly to VDDIO (high) to use an external supply.
X1 69 42 42 39 I/O Crystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock. GPIO19 is not supported. Internally GPIO19 is connected to the X1 function, therefore the GPIO19 should be kept in Input Mode with the Pullup disabled to avoid interference with the X1 clock function.
XRSn 2 3 3 4 I/OD Device Reset (in) and Watchdog Reset (out). During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRSn pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRSn and VDDIO. If a capacitor is placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values allow the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. The output buffer of this pin is an open-drain with an internal pullup. If this pin is driven by an external device, It should be done using an open-drain device. If this pin is driven by an external device, it should be done using an open-drain device.
POWER AND GROUND
VDD 4, 46, 71, 87 4, 27, 44, 59 4, 27, 44, 59 5, 24, 41, 53 1.2-V Digital Logic Power Pins. TI recommends placing a decoupling capacitor near each VDD pin with a minimum total capacitance of approximately 20 µF. When not using the internal voltage regulator, the exact value of the decoupling capacitance should be determined by your system voltage regulation solution.
VDDA 11, 34 22 22 20 3.3-V Analog Power Pins. Place a minimum 2.2-µF decoupling capacitor to VSSA on each pin.
VDDIO 3, 47, 70, 88 28, 43, 60 28, 43, 60 25, 40, 54 3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF decoupling capacitor on each pin.
VDDIO_SW 80 53 53 48 3.3-V Supply pin for the internal DC-DC regulator. If the internal DC-DC regulator is used, a bulk input capacitance of 20-µF should be placed on this pin. Always tie this pin to the VDDIO pin. A ferrite bead may be used for isolation if desired but VDDIO_SW and VDDIO must be supplied from the same source.
VSS 5, 45, 72, 86 5, 26, 45, 58 5, 26, 45, 58 PAD Digital Ground
VSSA 12, 33 21 21 19 Analog Ground
VSS_SW 82 55 55 50 Internal DC-DC regulator ground. Always tie this pin to the VSS pin.
(1) When DCDCEN = 1 the respective bits in AMSEL register are don't cares.