SPRS945G January 2017 – January 2023 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
PRODUCTION DATA
IDLE and HALT modes on this device are similar to those on other C28x devices. Table 7-12 describes the effect on the system when any of the clock-gating low-power modes are entered.
MODULES/ CLOCK DOMAIN | IDLE | HALT |
---|---|---|
SYSCLK | Active | Gated |
CPUCLK | Gated | Gated |
Clock to modules connected to PERx.SYSCLK | Active | Gated |
WDCLK | Active | Gated if CLKSRCCTL1.WDHALTI = 0 |
PLL | Powered | Software must power down PLL before entering HALT. |
INTOSC1 | Powered | Powered down if CLKSRCCTL1.WDHALTI = 0 |
INTOSC2 | Powered | Powered down if CLKSRCCTL1.WDHALTI = 0 |
Flash(1) | Powered | Powered |
XTAL(2) | Powered | Powered |