SPRS945G January 2017 – January 2023 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
PRODUCTION DATA
The delay blocks in the path of the voltage monitors work together to delay the release time between the voltage monitors and XRSn. These delays ensure that the voltages are stable when XRSn releases in external VREG mode. The delay blocks are only active during power up (that is, when VDDIO and VDD are ramping up).
The delay blocks contribute to the minimum slew rates specified in Power Management Module Electrical Data and Timing for the power rails.