SPRS584Q April   2009  – January 2024 TMS320F28030 , TMS320F28030-Q1 , TMS320F28031 , TMS320F28031-Q1 , TMS320F28032 , TMS320F28032-Q1 , TMS320F28033 , TMS320F28033-Q1 , TMS320F28034 , TMS320F28034-Q1 , TMS320F28035 , TMS320F28035-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Signal Descriptions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Automotive
    3. 6.3  ESD Ratings – Commercial
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 TMS320F2803x Current Consumption at 60-MHz SYSCLKOUT
      2. 6.5.2 Reducing Current Consumption
      3. 6.5.3 Current Consumption Graphs (VREG Enabled)
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics
      1. 6.7.1 PN Package
      2. 6.7.2 PAG Package
      3. 6.7.3 RSH Package
    8. 6.8  Thermal Design Considerations
    9. 6.9  JTAG Debug Probe Connection Without Signal Buffering for the MCU
    10. 6.10 Parameter Information
      1. 6.10.1 Timing Parameter Symbology
      2. 6.10.2 General Notes on Timing Parameters
    11. 6.11 Test Load Circuit
    12. 6.12 Power Sequencing
      1. 6.12.1 Reset ( XRS) Timing Requirements
      2. 6.12.2 Reset ( XRS) Switching Characteristics
    13. 6.13 Clock Specifications
      1. 6.13.1 Device Clock Table
        1. 6.13.1.1 2803x Clock Table and Nomenclature (60-MHz Devices)
        2. 6.13.1.2 Device Clocking Requirements/Characteristics
        3. 6.13.1.3 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 6.13.2 Clock Requirements and Characteristics
        1. 6.13.2.1 XCLKIN Timing Requirements – PLL Enabled
        2. 6.13.2.2 XCLKIN Timing Requirements – PLL Disabled
        3. 6.13.2.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 6.14 Flash Timing
      1. 6.14.1 Flash/OTP Endurance for T Temperature Material
      2. 6.14.2 Flash/OTP Endurance for S Temperature Material
      3. 6.14.3 Flash/OTP Endurance for Q Temperature Material
      4. 6.14.4 Flash Parameters at 60-MHz SYSCLKOUT
      5. 6.14.5 Flash/OTP Access Timing
      6. 6.14.6 Flash Data Retention Duration
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1  CPU
      2. 7.1.2  Control Law Accelerator (CLA)
      3. 7.1.3  Memory Bus (Harvard Bus Architecture)
      4. 7.1.4  Peripheral Bus
      5. 7.1.5  Real-Time JTAG and Analysis
      6. 7.1.6  Flash
      7. 7.1.7  M0, M1 SARAMs
      8. 7.1.8  L0 SARAM, and L1, L2, and L3 DPSARAMs
      9. 7.1.9  Boot ROM
        1. 7.1.9.1 Emulation Boot
        2. 7.1.9.2 GetMode
        3. 7.1.9.3 Peripheral Pins Used by the Bootloader
      10. 7.1.10 Security
      11. 7.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 7.1.12 External Interrupts (XINT1–XINT3)
      13. 7.1.13 Internal Zero Pin Oscillators, Oscillator, and PLL
      14. 7.1.14 Watchdog
      15. 7.1.15 Peripheral Clocking
      16. 7.1.16 Low-power Modes
      17. 7.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 7.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 7.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 7.1.20 Control Peripherals
      21. 7.1.21 Serial Port Peripherals
    2. 7.2 Memory Maps
    3. 7.3 Register Maps
    4. 7.4 Device Emulation Registers
    5. 7.5 VREG/BOR/POR
      1. 7.5.1 On-chip Voltage Regulator (VREG)
        1. 7.5.1.1 Using the On-chip VREG
        2. 7.5.1.2 Disabling the On-chip VREG
      2. 7.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
    6. 7.6 System Control
      1. 7.6.1 Internal Zero Pin Oscillators
      2. 7.6.2 Crystal Oscillator Option
      3. 7.6.3 PLL-Based Clock Module
      4. 7.6.4 Loss of Input Clock (NMI Watchdog Function)
      5. 7.6.5 CPU Watchdog Module
    7. 7.7 Low-power Modes Block
    8. 7.8 Interrupts
      1. 7.8.1 External Interrupts
        1. 7.8.1.1 External Interrupt Electrical Data/Timing
          1. 7.8.1.1.1 External Interrupt Timing Requirements
          2. 7.8.1.1.2 External Interrupt Switching Characteristics
    9. 7.9 Peripherals
      1. 7.9.1  Control Law Accelerator (CLA) Overview
      2. 7.9.2  Analog Block
        1. 7.9.2.1 Analog-to-Digital Converter (ADC)
          1. 7.9.2.1.1 Features
          2. 7.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. 7.9.2.1.2.1 External ADC Start-of-Conversion Switching Characteristics
          3. 7.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. 7.9.2.1.3.1 ADC Electrical Characteristics
            2. 7.9.2.1.3.2 ADC Power Modes
            3. 7.9.2.1.3.3 Internal Temperature Sensor
              1. 7.9.2.1.3.3.1 Temperature Sensor Coefficient
            4. 7.9.2.1.3.4 ADC Power-Up Control Bit Timing
              1. 7.9.2.1.3.4.1 ADC Power-Up Delays
            5. 7.9.2.1.3.5 ADC Sequential and Simultaneous Timings
        2. 7.9.2.2 ADC MUX
        3. 7.9.2.3 Comparator Block
          1. 7.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. 7.9.2.3.1.1 Electrical Characteristics of the Comparator/DAC
      3. 7.9.3  Detailed Descriptions
      4. 7.9.4  Serial Peripheral Interface (SPI) Module
        1. 7.9.4.1 SPI Master Mode Electrical Data/Timing
          1. 7.9.4.1.1 SPI Master Mode External Timing (Clock Phase = 0)
          2. 7.9.4.1.2 SPI Master Mode External Timing (Clock Phase = 1)
        2. 7.9.4.2 SPI Slave Mode Electrical Data/Timing
          1. 7.9.4.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
          2. 7.9.4.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 7.9.5  Serial Communications Interface (SCI) Module
      6. 7.9.6  Local Interconnect Network (LIN)
      7. 7.9.7  Enhanced Controller Area Network (eCAN) Module
      8. 7.9.8  Inter-Integrated Circuit (I2C)
        1. 7.9.8.1 I2C Electrical Data/Timing
          1. 7.9.8.1.1 I2C Timing Requirements
          2. 7.9.8.1.2 I2C Switching Characteristics
      9. 7.9.9  Enhanced PWM Modules (ePWM1/2/3/4/5/6/7)
        1. 7.9.9.1 ePWM Electrical Data/Timing
          1. 7.9.9.1.1 ePWM Timing Requirements
          2. 7.9.9.1.2 ePWM Switching Characteristics
        2. 7.9.9.2 Trip-Zone Input Timing
          1. 7.9.9.2.1 Trip-Zone Input Timing Requirements
      10. 7.9.10 High-Resolution PWM (HRPWM)
        1. 7.9.10.1 HRPWM Electrical Data/Timing
          1. 7.9.10.1.1 High-Resolution PWM Characteristics
      11. 7.9.11 Enhanced Capture Module (eCAP1)
        1. 7.9.11.1 eCAP Electrical Data/Timing
          1. 7.9.11.1.1 Enhanced Capture (eCAP) Timing Requirement
          2. 7.9.11.1.2 eCAP Switching Characteristics
      12. 7.9.12 High-Resolution Capture (HRCAP) Module
        1. 7.9.12.1 HRCAP Electrical Data/Timing
          1. 7.9.12.1.1 High-Resolution Capture (HRCAP) Timing Requirements
      13. 7.9.13 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.9.13.1 eQEP Electrical Data/Timing
          1. 7.9.13.1.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
          2. 7.9.13.1.2 eQEP Switching Characteristics
      14. 7.9.14 JTAG Port
      15. 7.9.15 General-Purpose Input/Output (GPIO) MUX
        1. 7.9.15.1 GPIO Electrical Data/Timing
          1. 7.9.15.1.1 GPIO - Output Timing
            1. 7.9.15.1.1.1 General-Purpose Output Switching Characteristics
          2. 7.9.15.1.2 GPIO - Input Timing
            1. 7.9.15.1.2.1 General-Purpose Input Timing Requirements
          3. 7.9.15.1.3 Sampling Window Width for Input Signals
          4. 7.9.15.1.4 Low-Power Mode Wakeup Timing
            1. 7.9.15.1.4.1 IDLE Mode Timing Requirements
            2. 7.9.15.1.4.2 IDLE Mode Switching Characteristics
            3. 7.9.15.1.4.3 STANDBY Mode Timing Requirements
            4. 7.9.15.1.4.4 STANDBY Mode Switching Characteristics
            5. 7.9.15.1.4.5 HALT Mode Timing Requirements
            6. 7.9.15.1.4.6 HALT Mode Switching Characteristics
  9. 8 Applications, Implementation, and Layout
    1. 8.1 TI Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device and Development Support Tool Nomenclature
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.8 Interrupts

Figure 7-12 shows how the various interrupt sources are multiplexed.

GUID-7F38ED99-46D5-4894-9C3D-CA206C4ADA86-low.gifFigure 7-12 External and PIE Interrupt Sources

Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. Table 7-19 shows the interrupts used by 2803x devices.

The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. The TRAP #0 instruction attempts to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, the TRAP #0 instruction should not be used when the PIE is enabled. Doing so will result in undefined behavior.

When the PIE is enabled, the TRAP #1 to TRAP #12 instructions will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group. For example: the TRAP #1 instruction fetches the vector from INT1.1, the TRAP #2 instruction fetches the vector from INT2.1, and so forth.

GUID-36B07754-7CC8-4399-ADE6-3DCC823FA0B0-low.gifFigure 7-13 Multiplexing of Interrupts Using the PIE Block

In Table 7-19, out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:

  1. No peripheral within the group is asserting interrupts.
  2. No peripheral interrupts are assigned to the group (for example, PIE group 7).
Table 7-19 PIE MUXed Peripheral Interrupt Vector Table
INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
INT1.y WAKEINT TINT0 ADCINT9 XINT2 XINT1 Reserved ADCINT2 ADCINT1
(LPM/WD) (TIMER 0) (ADC) Ext. int. 2 Ext. int. 1 – (ADC) (ADC)
0xD4E 0xD4C 0xD4A 0xD48 0xD46 0xD44 0xD42 0xD40
INT2.y Reserved EPWM7_TZINT EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT
– (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)
0xD5E 0xD5C 0xD5A 0xD58 0xD56 0xD54 0xD52 0xD50
INT3.y Reserved EPWM7_INT EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT
– (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)
0xD6E 0xD6C 0xD6A 0xD68 0xD66 0xD64 0xD62 0xD60
INT4.y HRCAP2_INT HRCAP1_INT Reserved Reserved Reserved Reserved Reserved ECAP1_INT
(HRCAP2) (HRCAP1) – – – – – (eCAP1)
0xD7E 0xD7C 0xD7A 0xD78 0xD76 0xD74 0xD72 0xD70
INT5.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved EQEP1_INT
– – – – – – – (eQEP1)
0xD8E 0xD8C 0xD8A 0xD88 0xD86 0xD84 0xD82 0xD80
INT6.y Reserved Reserved Reserved Reserved SPITXINTB SPIRXINTB SPITXINTA SPIRXINTA
– – – – (SPI-B) (SPI-B) (SPI-A) (SPI-A)
0xD9E 0xD9C 0xD9A 0xD98 0xD96 0xD94 0xD92 0xD90
INT7.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
– – – – – – – –
0xDAE 0xDAC 0xDAA 0xDA8 0xDA6 0xDA4 0xDA2 0xDA0
INT8.y Reserved Reserved Reserved Reserved Reserved Reserved I2CINT2A I2CINT1A
– – – – – – (I2C-A) (I2C-A)
0xDBE 0xDBC 0xDBA 0xDB8 0xDB6 0xDB4 0xDB2 0xDB0
INT9.y Reserved Reserved ECAN1_INTA ECAN0_INTA LIN1_INTA LIN0_INTA SCITXINTA SCIRXINTA
– – (CAN-A) (CAN-A) (LIN-A) (LIN-A) (SCI-A) (SCI-A)
0xDCE 0xDCC 0xDCA 0xDC8 0xDC6 0xDC4 0xDC2 0xDC0
INT10.y ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1
(ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC)
0xDDE 0xDDC 0xDDA 0xDD8 0xDD6 0xDD4 0xDD2 0xDD0
INT11.y CLA1_INT8 CLA1_INT7 CLA1_INT6 CLA1_INT5 CLA1_INT4 CLA1_INT3 CLA1_INT2 CLA1_INT1
(CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA)
0xDEE 0xDEC 0xDEA 0xDE8 0xDE6 0xDE4 0xDE2 0xDE0
INT12.y LUF LVF Reserved Reserved Reserved Reserved Reserved XINT3
(CLA) (CLA) – – – – – Ext. Int. 3
0xDFE 0xDFC 0xDFA 0xDF8 0xDF6 0xDF4 0xDF2 0xDF0
Table 7-20 PIE Configuration and Control Registers
NAMEADDRESSSIZE (x16)DESCRIPTION(1)
PIECTRL0x0CE01PIE, Control Register
PIEACK0x0CE11PIE, Acknowledge Register
PIEIER10x0CE21PIE, INT1 Group Enable Register
PIEIFR10x0CE31PIE, INT1 Group Flag Register
PIEIER20x0CE41PIE, INT2 Group Enable Register
PIEIFR20x0CE51PIE, INT2 Group Flag Register
PIEIER30x0CE61PIE, INT3 Group Enable Register
PIEIFR30x0CE71PIE, INT3 Group Flag Register
PIEIER40x0CE81PIE, INT4 Group Enable Register
PIEIFR40x0CE91PIE, INT4 Group Flag Register
PIEIER50x0CEA1PIE, INT5 Group Enable Register
PIEIFR50x0CEB1PIE, INT5 Group Flag Register
PIEIER60x0CEC1PIE, INT6 Group Enable Register
PIEIFR60x0CED1PIE, INT6 Group Flag Register
PIEIER70x0CEE1PIE, INT7 Group Enable Register
PIEIFR70x0CEF1PIE, INT7 Group Flag Register
PIEIER80x0CF01PIE, INT8 Group Enable Register
PIEIFR80x0CF11PIE, INT8 Group Flag Register
PIEIER90x0CF21PIE, INT9 Group Enable Register
PIEIFR90x0CF31PIE, INT9 Group Flag Register
PIEIER100x0CF41PIE, INT10 Group Enable Register
PIEIFR100x0CF51PIE, INT10 Group Flag Register
PIEIER110x0CF61PIE, INT11 Group Enable Register
PIEIFR110x0CF71PIE, INT11 Group Flag Register
PIEIER120x0CF81PIE, INT12 Group Enable Register
PIEIFR120x0CF91PIE, INT12 Group Flag Register
Reserved0x0CFA –
0x0CFF		6Reserved
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.