SPRS584Q April   2009  – January 2024 TMS320F28030 , TMS320F28030-Q1 , TMS320F28031 , TMS320F28031-Q1 , TMS320F28032 , TMS320F28032-Q1 , TMS320F28033 , TMS320F28033-Q1 , TMS320F28034 , TMS320F28034-Q1 , TMS320F28035 , TMS320F28035-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Signal Descriptions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Automotive
    3. 6.3  ESD Ratings – Commercial
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 TMS320F2803x Current Consumption at 60-MHz SYSCLKOUT
      2. 6.5.2 Reducing Current Consumption
      3. 6.5.3 Current Consumption Graphs (VREG Enabled)
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics
      1. 6.7.1 PN Package
      2. 6.7.2 PAG Package
      3. 6.7.3 RSH Package
    8. 6.8  Thermal Design Considerations
    9. 6.9  JTAG Debug Probe Connection Without Signal Buffering for the MCU
    10. 6.10 Parameter Information
      1. 6.10.1 Timing Parameter Symbology
      2. 6.10.2 General Notes on Timing Parameters
    11. 6.11 Test Load Circuit
    12. 6.12 Power Sequencing
      1. 6.12.1 Reset ( XRS) Timing Requirements
      2. 6.12.2 Reset ( XRS) Switching Characteristics
    13. 6.13 Clock Specifications
      1. 6.13.1 Device Clock Table
        1. 6.13.1.1 2803x Clock Table and Nomenclature (60-MHz Devices)
        2. 6.13.1.2 Device Clocking Requirements/Characteristics
        3. 6.13.1.3 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 6.13.2 Clock Requirements and Characteristics
        1. 6.13.2.1 XCLKIN Timing Requirements – PLL Enabled
        2. 6.13.2.2 XCLKIN Timing Requirements – PLL Disabled
        3. 6.13.2.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 6.14 Flash Timing
      1. 6.14.1 Flash/OTP Endurance for T Temperature Material
      2. 6.14.2 Flash/OTP Endurance for S Temperature Material
      3. 6.14.3 Flash/OTP Endurance for Q Temperature Material
      4. 6.14.4 Flash Parameters at 60-MHz SYSCLKOUT
      5. 6.14.5 Flash/OTP Access Timing
      6. 6.14.6 Flash Data Retention Duration
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1  CPU
      2. 7.1.2  Control Law Accelerator (CLA)
      3. 7.1.3  Memory Bus (Harvard Bus Architecture)
      4. 7.1.4  Peripheral Bus
      5. 7.1.5  Real-Time JTAG and Analysis
      6. 7.1.6  Flash
      7. 7.1.7  M0, M1 SARAMs
      8. 7.1.8  L0 SARAM, and L1, L2, and L3 DPSARAMs
      9. 7.1.9  Boot ROM
        1. 7.1.9.1 Emulation Boot
        2. 7.1.9.2 GetMode
        3. 7.1.9.3 Peripheral Pins Used by the Bootloader
      10. 7.1.10 Security
      11. 7.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 7.1.12 External Interrupts (XINT1–XINT3)
      13. 7.1.13 Internal Zero Pin Oscillators, Oscillator, and PLL
      14. 7.1.14 Watchdog
      15. 7.1.15 Peripheral Clocking
      16. 7.1.16 Low-power Modes
      17. 7.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 7.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 7.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 7.1.20 Control Peripherals
      21. 7.1.21 Serial Port Peripherals
    2. 7.2 Memory Maps
    3. 7.3 Register Maps
    4. 7.4 Device Emulation Registers
    5. 7.5 VREG/BOR/POR
      1. 7.5.1 On-chip Voltage Regulator (VREG)
        1. 7.5.1.1 Using the On-chip VREG
        2. 7.5.1.2 Disabling the On-chip VREG
      2. 7.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
    6. 7.6 System Control
      1. 7.6.1 Internal Zero Pin Oscillators
      2. 7.6.2 Crystal Oscillator Option
      3. 7.6.3 PLL-Based Clock Module
      4. 7.6.4 Loss of Input Clock (NMI Watchdog Function)
      5. 7.6.5 CPU Watchdog Module
    7. 7.7 Low-power Modes Block
    8. 7.8 Interrupts
      1. 7.8.1 External Interrupts
        1. 7.8.1.1 External Interrupt Electrical Data/Timing
          1. 7.8.1.1.1 External Interrupt Timing Requirements
          2. 7.8.1.1.2 External Interrupt Switching Characteristics
    9. 7.9 Peripherals
      1. 7.9.1  Control Law Accelerator (CLA) Overview
      2. 7.9.2  Analog Block
        1. 7.9.2.1 Analog-to-Digital Converter (ADC)
          1. 7.9.2.1.1 Features
          2. 7.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. 7.9.2.1.2.1 External ADC Start-of-Conversion Switching Characteristics
          3. 7.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. 7.9.2.1.3.1 ADC Electrical Characteristics
            2. 7.9.2.1.3.2 ADC Power Modes
            3. 7.9.2.1.3.3 Internal Temperature Sensor
              1. 7.9.2.1.3.3.1 Temperature Sensor Coefficient
            4. 7.9.2.1.3.4 ADC Power-Up Control Bit Timing
              1. 7.9.2.1.3.4.1 ADC Power-Up Delays
            5. 7.9.2.1.3.5 ADC Sequential and Simultaneous Timings
        2. 7.9.2.2 ADC MUX
        3. 7.9.2.3 Comparator Block
          1. 7.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. 7.9.2.3.1.1 Electrical Characteristics of the Comparator/DAC
      3. 7.9.3  Detailed Descriptions
      4. 7.9.4  Serial Peripheral Interface (SPI) Module
        1. 7.9.4.1 SPI Master Mode Electrical Data/Timing
          1. 7.9.4.1.1 SPI Master Mode External Timing (Clock Phase = 0)
          2. 7.9.4.1.2 SPI Master Mode External Timing (Clock Phase = 1)
        2. 7.9.4.2 SPI Slave Mode Electrical Data/Timing
          1. 7.9.4.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
          2. 7.9.4.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 7.9.5  Serial Communications Interface (SCI) Module
      6. 7.9.6  Local Interconnect Network (LIN)
      7. 7.9.7  Enhanced Controller Area Network (eCAN) Module
      8. 7.9.8  Inter-Integrated Circuit (I2C)
        1. 7.9.8.1 I2C Electrical Data/Timing
          1. 7.9.8.1.1 I2C Timing Requirements
          2. 7.9.8.1.2 I2C Switching Characteristics
      9. 7.9.9  Enhanced PWM Modules (ePWM1/2/3/4/5/6/7)
        1. 7.9.9.1 ePWM Electrical Data/Timing
          1. 7.9.9.1.1 ePWM Timing Requirements
          2. 7.9.9.1.2 ePWM Switching Characteristics
        2. 7.9.9.2 Trip-Zone Input Timing
          1. 7.9.9.2.1 Trip-Zone Input Timing Requirements
      10. 7.9.10 High-Resolution PWM (HRPWM)
        1. 7.9.10.1 HRPWM Electrical Data/Timing
          1. 7.9.10.1.1 High-Resolution PWM Characteristics
      11. 7.9.11 Enhanced Capture Module (eCAP1)
        1. 7.9.11.1 eCAP Electrical Data/Timing
          1. 7.9.11.1.1 Enhanced Capture (eCAP) Timing Requirement
          2. 7.9.11.1.2 eCAP Switching Characteristics
      12. 7.9.12 High-Resolution Capture (HRCAP) Module
        1. 7.9.12.1 HRCAP Electrical Data/Timing
          1. 7.9.12.1.1 High-Resolution Capture (HRCAP) Timing Requirements
      13. 7.9.13 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.9.13.1 eQEP Electrical Data/Timing
          1. 7.9.13.1.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
          2. 7.9.13.1.2 eQEP Switching Characteristics
      14. 7.9.14 JTAG Port
      15. 7.9.15 General-Purpose Input/Output (GPIO) MUX
        1. 7.9.15.1 GPIO Electrical Data/Timing
          1. 7.9.15.1.1 GPIO - Output Timing
            1. 7.9.15.1.1.1 General-Purpose Output Switching Characteristics
          2. 7.9.15.1.2 GPIO - Input Timing
            1. 7.9.15.1.2.1 General-Purpose Input Timing Requirements
          3. 7.9.15.1.3 Sampling Window Width for Input Signals
          4. 7.9.15.1.4 Low-Power Mode Wakeup Timing
            1. 7.9.15.1.4.1 IDLE Mode Timing Requirements
            2. 7.9.15.1.4.2 IDLE Mode Switching Characteristics
            3. 7.9.15.1.4.3 STANDBY Mode Timing Requirements
            4. 7.9.15.1.4.4 STANDBY Mode Switching Characteristics
            5. 7.9.15.1.4.5 HALT Mode Timing Requirements
            6. 7.9.15.1.4.6 HALT Mode Switching Characteristics
  9. 8 Applications, Implementation, and Layout
    1. 8.1 TI Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device and Development Support Tool Nomenclature
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.9.15 General-Purpose Input/Output (GPIO) MUX

The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging I/O capability.

The device supports 45 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 7-39 shows the GPIO register mapping.

Table 7-39 GPIO Registers
NAMEADDRESSSIZE (x16)DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL0x6F802GPIO A Control Register (GPIO0 to 31)
GPAQSEL10x6F822GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL20x6F842GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX10x6F862GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX20x6F882GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR0x6F8A2GPIO A Direction Register (GPIO0 to 31)
GPAPUD0x6F8C2GPIO A Pullup Disable Register (GPIO0 to 31)
GPBCTRL0x6F902GPIO B Control Register (GPIO32 to 44)
GPBQSEL10x6F922GPIO B Qualifier Select 1 Register (GPIO32 to 44)
GPBMUX10x6F962GPIO B MUX 1 Register (GPIO32 to 44)
GPBDIR0x6F9A2GPIO B Direction Register (GPIO32 to 44)
GPBPUD0x6F9C2GPIO B Pullup Disable Register (GPIO32 to 44)
AIOMUX10x6FB62Analog, I/O mux 1 register (AIO0 to AIO15)
AIODIR0x6FBA2Analog, I/O Direction Register (AIO0 to AIO15)
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT0x6FC02GPIO A Data Register (GPIO0 to 31)
GPASET0x6FC22GPIO A Data Set Register (GPIO0 to 31)
GPACLEAR0x6FC42GPIO A Data Clear Register (GPIO0 to 31)
GPATOGGLE0x6FC62GPIO A Data Toggle Register (GPIO0 to 31)
GPBDAT0x6FC82GPIO B Data Register (GPIO32 to 44)
GPBSET0x6FCA2GPIO B Data Set Register (GPIO32 to 44)
GPBCLEAR0x6FCC2GPIO B Data Clear Register (GPIO32 to 44)
GPBTOGGLE0x6FCE2GPIO B Data Toggle Register (GPIO32 to 44)
AIODAT0x6FD82Analog I/O Data Register (AIO0 to AIO15)
AIOSET0x6FDA2Analog I/O Data Set Register (AIO0 to AIO15)
AIOCLEAR0x6FDC2Analog I/O Data Clear Register (AIO0 to AIO15)
AIOTOGGLE0x6FDE2Analog I/O Data Toggle Register (AIO0 to AIO15)
GPIO INTERRUPT AND LOW-POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL0x6FE01XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL0x6FE11XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT3SEL0x6FE21XINT3 GPIO Input Select Register (GPIO0 to 31)
GPIOLPMSEL0x6FE82LPM GPIO Select Register (GPIO0 to 31)
Note:

There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn and GPxQSELn registers occurs to when the action is valid.

Table 7-40 GPIOA MUX
DEFAULT AT RESET
PRIMARY I/O FUNCTION		PERIPHERAL
SELECTION 1(1)(2)		PERIPHERAL
SELECTION 2(1)(2)		PERIPHERAL
SELECTION 3(1)(2)
GPAMUX1 REGISTER BITS(GPAMUX1 BITS = 00)(GPAMUX1 BITS = 01)(GPAMUX1 BITS = 10)(GPAMUX1 BITS = 11)
1-0GPIO0EPWM1A (O)ReservedReserved
3-2GPIO1EPWM1B (O)ReservedCOMP1OUT (O)
5-4GPIO2EPWM2A (O)ReservedReserved
7-6GPIO3EPWM2B (O)SPISOMIA (I/O)COMP2OUT (O)
9-8GPIO4EPWM3A (O)ReservedReserved
11-10GPIO5EPWM3B (O)SPISIMOA (I/O)ECAP1 (I/O)
13-12GPIO6EPWM4A (O)EPWMSYNCI (I)EPWMSYNCO (O)
15-14GPIO7EPWM4B (O)SCIRXDA (I)Reserved
17-16GPIO8EPWM5A (O)ReservedADCSOCAO (O)
19-18GPIO9EPWM5B (O)LINTXA (O)HRCAP1 (I)
21-20GPIO10EPWM6A (O)ReservedADCSOCBO (O)
23-22GPIO11EPWM6B (O)LINRXA (I)HRCAP2 (I)
25-24GPIO12TZ1 (I)SCITXDA (O)SPISIMOB (I/O)
27-26GPIO13(3)TZ2 (I)ReservedSPISOMIB (I/O)
29-28GPIO14(3)TZ3 (I)LINTXA (O)SPICLKB (I/O)
31-30GPIO15(3)TZ1 (I)LINRXA (I)SPISTEB (I/O)
GPAMUX2 REGISTER BITS(GPAMUX2 BITS = 00)(GPAMUX2 BITS = 01)(GPAMUX2 BITS = 10)(GPAMUX2 BITS = 11)
1-0GPIO16SPISIMOA (I/O)ReservedTZ2 (I)
3-2GPIO17SPISOMIA (I/O)ReservedTZ3 (I)
5-4GPIO18SPICLKA (I/O)LINTXA (O)XCLKOUT (O)
7-6GPIO19/XCLKINSPISTEA (I/O)LINRXA (I)ECAP1 (I/O)
9-8GPIO20EQEP1A (I)ReservedCOMP1OUT (O)
11-10GPIO21EQEP1B (I)ReservedCOMP2OUT (O)
13-12GPIO22EQEP1S (I/O)ReservedLINTXA (O)
15-14GPIO23EQEP1I (I/O)ReservedLINRXA (I)
17-16GPIO24ECAP1 (I/O)ReservedSPISIMOB (I/O)
19-18GPIO25(3)ReservedReservedSPISOMIB (I/O)
21-20GPIO26(3)HRCAP1 (I)ReservedSPICLKB (I/O)
23-22GPIO27(3)HRCAP2 (I)ReservedSPISTEB (I/O)
25-24GPIO28SCIRXDA (I)SDAA (I/OD) TZ2 (I)
27-26GPIO29SCITXDA (O)SCLA (I/OD) TZ3 (I)
29-28GPIO30CANRXA (I)ReservedReserved
31-30GPIO31CANTXA (O)ReservedReserved
(1) The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
(2) I = Input, O = Output, OD = Open Drain
(3) These pins are not available in the 64-pin package.
Table 7-41 GPIOB MUX
DEFAULT AT RESET
PRIMARY I/O FUNCTION		PERIPHERAL SELECTION 1(1)PERIPHERAL SELECTION 2(1)PERIPHERAL SELECTION 3(1)
GPBMUX1 REGISTER BITS(GPBMUX1 BITS = 00)(GPBMUX1 BITS = 01)(GPBMUX1 BITS = 10)(GPBMUX1 BITS = 11)
1-0GPIO32SDAA (I/OD)EPWMSYNCI (I)ADCSOCAO (O)
3-2GPIO33SCLA (I/OD)EPWMSYNCO (O)ADCSOCBO (O)
5-4GPIO34COMP2OUT (O)ReservedCOMP3OUT (O)
7-6GPIO35 (TDI)ReservedReservedReserved
9-8GPIO36 (TMS)ReservedReservedReserved
11-10GPIO37 (TDO)ReservedReservedReserved
13-12GPIO38/XCLKIN (TCK)ReservedReservedReserved
15-14GPIO39(2)ReservedReservedReserved
17-16GPIO40(2)EPWM7A (O)ReservedReserved
19-18GPIO41(2)EPWM7B (O)ReservedReserved
21-20GPIO42(2)ReservedReservedCOMP1OUT (O)
23-22GPIO43(2)ReservedReservedCOMP2OUT (O)
25-24GPIO44(2)ReservedReservedReserved
27-26ReservedReservedReservedReserved
29-28ReservedReservedReservedReserved
31-30ReservedReservedReservedReserved
(1) I = Input, O = Output, OD = Open Drain
(2) These pins are not available in the 64-pin package.
Table 7-42 Analog MUX for 80-Pin PN Package
DEFAULT AT RESET
AIOx AND PERIPHERAL SELECTION 1(1)PERIPHERAL SELECTION 2 AND PERIPHERAL SELECTION 3(1)
AIOMUX1 REGISTER BITSAIOMUX1 BITS = 0,xAIOMUX1 BITS = 1,x
1-0ADCINA0 (I)ADCINA0 (I)
3-2ADCINA1 (I)ADCINA1 (I)
5-4AIO2 (I/O)ADCINA2 (I), COMP1A (I)
7-6ADCINA3 (I)ADCINA3 (I)
9-8AIO4 (I/O)ADCINA4 (I), COMP2A (I)
11-10ADCINA5 (I)ADCINA5 (I)
13-12AIO6 (I/O)ADCINA6 (I), COMP3A (I)
15-14ADCINA7 (I)ADCINA7 (I)
17-16ADCINB0 (I)ADCINB0 (I)
19-18ADCINB1 (I)ADCINB1 (I)
21-20AIO10 (I/O)ADCINB2 (I), COMP1B (I)
23-22ADCINB3 (I)ADCINB3 (I)
25-24AIO12 (I/O)ADCINB4 (I), COMP2B (I)
27-26ADCINB5 (I)ADCINB5 (I)
29-28AIO14 (I/O)ADCINB6 (I), COMP3B (I)
31-30ADCINB7 (I)ADCINB7 (I)
(1) I = Input, O = Output
Table 7-43 Analog MUX for 56-Pin RSH and 64-Pin PAG Packages
DEFAULT AT RESET
AIOx AND PERIPHERAL SELECTION 1(1)PERIPHERAL SELECTION 2 AND PERIPHERAL SELECTION 3(1)
AIOMUX1 REGISTER BITSAIOMUX1 BITS = 0,xAIOMUX1 BITS = 1,x
1-0ADCINA0 (I), VREFHI (I)ADCINA0 (I), VREFHI (I)
3-2ADCINA1 (I)ADCINA1 (I)
5-4AIO2 (I/O)ADCINA2 (I), COMP1A (I)
7-6ADCINA3 (I)ADCINA3 (I)
9-8AIO4 (I/O)ADCINA4 (I), COMP2A (I)
11-10––
13-12AIO6 (I/O)ADCINA6 (I), COMP3A (I)
15-14ADCINA7 (I)ADCINA7 (I)
17-16ADCINB0 (I)ADCINB0 (I)
19-18ADCINB1 (I)ADCINB1 (I)
21-20AIO10 (I/O)ADCINB2 (I), COMP1B (I)
23-22ADCINB3 (I)ADCINB3 (I)
25-24AIO12 (I/O)ADCINB4 (I), COMP2B (I)
27-26––
29-28AIO14 (I/O)ADCINB6 (I), COMP3B (I)
31-30ADCINB7 (I)ADCINB7 (I)
(1) I = Input, O = Output

The user can select the type of input qualification for each GPIO pin through the GPxQSEL1/2 registers from four choices:

  • Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
  • Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the input is allowed to change.
  • The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the same (all 0s or all 1s) as shown in Figure 7-47 (for 6 sample mode).
  • No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not required (synchronization is performed within the peripheral).

Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral.

GUID-320A2369-6DAF-4055-B5B4-0FEBB6F0F859-low.gif
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. For pin-specific variations, see the System Control chapter in the TMS320F2803x Real-Time Microcontrollers Technical Reference Manual.
Figure 7-45 GPIO Multiplexing