SPRSP25A June   2018  – July 2018 TMS320F28035-EP

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Signal Descriptions
      1. Table 3-1 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Power-On Hours (POH) Limits
    4. 4.4  Recommended Operating Conditions
    5. 4.5  Power Consumption Summary
      1. Table 4-1 TMS320F2803x Current Consumption at 60-MHz SYSCLKOUT
      2. 4.5.1      Reducing Current Consumption
      3. 4.5.2      Current Consumption Graphs (VREG Enabled)
    6. 4.6  Electrical Characteristics
    7. 4.7  Thermal Resistance Characteristics
    8. 4.8  Thermal Design Considerations
    9. 4.9  Emulator Connection Without Signal Buffering for the MCU
    10. 4.10 Parameter Information
      1. 4.10.1 Timing Parameter Symbology
      2. 4.10.2 General Notes on Timing Parameters
    11. 4.11 Test Load Circuit
    12. 4.12 Power Sequencing
      1. Table 4-4 Reset (XRS) Timing Requirements
      2. Table 4-5 Reset (XRS) Switching Characteristics
    13. 4.13 Clock Specifications
      1. 4.13.1 Device Clock Table
        1. Table 4-6 2803x Clock Table and Nomenclature (60-MHz Devices)
        2. Table 4-7 Device Clocking Requirements/Characteristics
        3. Table 4-8 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 4.13.2 Clock Requirements and Characteristics
        1. Table 4-9   XCLKIN Timing Requirements – PLL Enabled
        2. Table 4-10 XCLKIN Timing Requirements – PLL Disabled
        3. Table 4-11 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 4.14 Flash Timing
      1. Table 4-12 Flash/OTP Endurance
      2. Table 4-13 Flash Parameters at 60-MHz SYSCLKOUT
      3. Table 4-14 Flash/OTP Access Timing
      4. Table 4-15 Flash Data Retention Duration
  5. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1  CPU
      2. 5.1.2  Control Law Accelerator (CLA)
      3. 5.1.3  Memory Bus (Harvard Bus Architecture)
      4. 5.1.4  Peripheral Bus
      5. 5.1.5  Real-Time JTAG and Analysis
      6. 5.1.6  Flash
      7. 5.1.7  M0, M1 SARAMs
      8. 5.1.8  L0 SARAM, and L1, L2, and L3 DPSARAMs
      9. 5.1.9  Boot ROM
        1. 5.1.9.1 Emulation Boot
        2. 5.1.9.2 GetMode
        3. 5.1.9.3 Peripheral Pins Used by the Bootloader
      10. 5.1.10 Security
      11. 5.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 5.1.12 External Interrupts (XINT1–XINT3)
      13. 5.1.13 Internal Zero Pin Oscillators, Oscillator, and PLL
      14. 5.1.14 Watchdog
      15. 5.1.15 Peripheral Clocking
      16. 5.1.16 Low-power Modes
      17. 5.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 5.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 5.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 5.1.20 Control Peripherals
      21. 5.1.21 Serial Port Peripherals
    2. 5.2 Memory Maps
    3. 5.3 Register Maps
    4. 5.4 Device Emulation Registers
    5. 5.5 VREG/BOR/POR
      1. 5.5.1 On-chip Voltage Regulator (VREG)
        1. 5.5.1.1 Using the On-chip VREG
        2. 5.5.1.2 Disabling the On-chip VREG
      2. 5.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
    6. 5.6 System Control
      1. 5.6.1 Internal Zero Pin Oscillators
      2. 5.6.2 Crystal Oscillator Option
      3. 5.6.3 PLL-Based Clock Module
      4. 5.6.4 Loss of Input Clock (NMI Watchdog Function)
      5. 5.6.5 CPU-Watchdog Module
    7. 5.7 Low-Power Modes Block
    8. 5.8 Interrupts
      1. 5.8.1 External Interrupts
        1. 5.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 5-20 External Interrupt Timing Requirements
          2. Table 5-21 External Interrupt Switching Characteristics
    9. 5.9 Peripherals
      1. 5.9.1  Control Law Accelerator (CLA) Overview
      2. 5.9.2  Analog Block
        1. 5.9.2.1 Analog-to-Digital Converter (ADC)
          1. 5.9.2.1.1 Features
          2. 5.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. Table 5-26 External ADC Start-of-Conversion Switching Characteristics
          3. 5.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. Table 5-27 ADC Electrical Characteristics
            2. Table 5-28 ADC Power Modes
            3. 5.9.2.1.3.1 Internal Temperature Sensor
              1. Table 5-29 Temperature Sensor Coefficient
            4. 5.9.2.1.3.2 ADC Power-Up Control Bit Timing
              1. Table 5-30 ADC Power-Up Delays
            5. 5.9.2.1.3.3 ADC Sequential and Simultaneous Timings
        2. 5.9.2.2 ADC MUX
        3. 5.9.2.3 Comparator Block
          1. 5.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. Table 5-32 Electrical Characteristics of the Comparator/DAC
      3. 5.9.3  Detailed Descriptions
      4. 5.9.4  Serial Peripheral Interface (SPI) Module
        1. 5.9.4.1 SPI Master Mode Electrical Data/Timing
          1. Table 5-35 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 5-36 SPI Master Mode External Timing (Clock Phase = 1)
        2. 5.9.4.2 SPI Slave Mode Electrical Data/Timing
          1. Table 5-37 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 5-38 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 5.9.5  Serial Communications Interface (SCI) Module
      6. 5.9.6  Local Interconnect Network (LIN)
      7. 5.9.7  Enhanced Controller Area Network (eCAN) Module
      8. 5.9.8  Inter-Integrated Circuit (I2C)
        1. 5.9.8.1 I2C Electrical Data/Timing
          1. Table 5-44 I2C Timing Requirements
          2. Table 5-45 I2C Switching Characteristics
      9. 5.9.9  Enhanced PWM Modules (ePWM1/2/3/4/5/6/7)
        1. 5.9.9.1 ePWM Electrical Data/Timing
          1. Table 5-48 ePWM Timing Requirements
          2. Table 5-49 ePWM Switching Characteristics
        2. 5.9.9.2 Trip-Zone Input Timing
          1. Table 5-50 Trip-Zone Input Timing Requirements
      10. 5.9.10 High-Resolution PWM (HRPWM)
        1. 5.9.10.1 HRPWM Electrical Data/Timing
          1. Table 5-51 High-Resolution PWM Characteristics
      11. 5.9.11 Enhanced Capture Module (eCAP1)
        1. 5.9.11.1 eCAP Electrical Data/Timing
          1. Table 5-53 Enhanced Capture (eCAP) Timing Requirement
          2. Table 5-54 eCAP Switching Characteristics
      12. 5.9.12 High-Resolution Capture (HRCAP) Module
        1. 5.9.12.1 HRCAP Electrical Data/Timing
          1. Table 5-56 High-Resolution Capture (HRCAP) Timing Requirements
      13. 5.9.13 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 5.9.13.1 eQEP Electrical Data/Timing
          1. Table 5-58 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
          2. Table 5-59 eQEP Switching Characteristics
      14. 5.9.14 JTAG Port
      15. 5.9.15 General-Purpose Input/Output (GPIO) MUX
        1. 5.9.15.1 GPIO Electrical Data/Timing
          1. 5.9.15.1.1 GPIO - Output Timing
            1. Table 5-63 General-Purpose Output Switching Characteristics
          2. 5.9.15.1.2 GPIO - Input Timing
            1. Table 5-64 General-Purpose Input Timing Requirements
          3. 5.9.15.1.3 Sampling Window Width for Input Signals
          4. 5.9.15.1.4 Low-Power Mode Wakeup Timing
            1. Table 5-65 IDLE Mode Timing Requirements
            2. Table 5-66 IDLE Mode Switching Characteristics
            3. Table 5-67 STANDBY Mode Timing Requirements
            4. Table 5-68 STANDBY Mode Switching Characteristics
            5. Table 5-69 HALT Mode Timing Requirements
            6. Table 5-70 HALT Mode Switching Characteristics
  6. 6Applications, Implementation, and Layout
    1. 6.1 TI Design or Reference Design
  7. 7Device and Documentation Support
    1. 7.1 Getting Started
    2. 7.2 Device and Development Support Tool Nomenclature
    3. 7.3 Tools and Software
    4. 7.4 Documentation Support
    5. 7.5 Community Resources
    6. 7.6 Trademarks
    7. 7.7 Electrostatic Discharge Caution
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information
    1. 8.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3 Register Maps

The devices contain four peripheral register spaces. The spaces are categorized as follows:

Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See  Table 5-6.
Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See  Table 5-7.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See  Table 5-8.
Peripheral Frame 3: These are peripherals that are mapped to the 32-bit peripheral bus and are accessible by the CLA. See Table 5-9.

Table 5-6 Peripheral Frame 0 Registers(1)

NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED(2)
Device Emulation Registers 0x00 0880 to 0x00 0984 261 Yes
System Power Control Registers 0x00 0985 to 0x00 0987 3 Yes
FLASH Registers(3) 0x00 0A80 to 0x00 0ADF 96 Yes
Code Security Module Registers 0x00 0AE0 to 0x00 0AEF 16 Yes
ADC registers (0 wait read only) 0x00 0B00 to 0x00 0B0F 16 No
CPU–TIMER0/1/2 Registers 0x00 0C00 to 0x00 0C3F 64 No
PIE Registers 0x00 0CE0 to 0x00 0CFF 32 No
PIE Vector Table 0x00 0D00 to 0x00 0DFF 256 No
CLA Registers 0x00 1400 to 0x00 147F 128 Yes
CLA to CPU Message RAM (CPU writes ignored) 0x00 1480 to 0x00 14FF 128 NA
CPU to CLA Message RAM (CLA writes ignored) 0x00 1500 to 0x00 157F 128 NA
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).

Table 5-7 Peripheral Frame 1 Registers

NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
eCAN-A registers 0x00 6000 to 0x00 61FF 512  (1)
eCAP1 registers 0x00 6A00 to 0x00 6A1F 32 No
HRCAP1 registers 0x00 6AC0 to 0x00 6ADF 32 (1)
HRCAP2 registers 0x00 6AE0 to 0x00 6AFF 32 (1)
eQEP1 registers 0x00 6B00 to 0x00 6B3F 64  (1)
LIN-A registers 0x00 6C00 to 0x00 6C7F 128  (1)
GPIO registers 0x00 6F80 to 0x00 6FFF 128  (1)
(1) Some registers are EALLOW protected. See the module reference guide for more information.

Table 5-8 Peripheral Frame 2 Registers

NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
System Control Registers 0x00 7010 to 0x00 702F 32 Yes
SPI-A Registers 0x00 7040 to 0x00 704F 16 No
SCI-A Registers 0x00 7050 to 0x00 705F 16 No
NMI Watchdog Interrupt Registers 0x00 7060 to 0x00 706F 16 Yes
External Interrupt Registers 0x00 7070 to 0x00 707F 16 Yes
ADC Registers 0x00 7100 to 0x00 717F 128  (1)
I2C-A Registers 0x00 7900 to 0x00 793F 64  (1)
SPI-B Registers 0x00 7740 to 0x00 774F 16 No
(1) Some registers are EALLOW protected. See the module reference guide for more information.

Table 5-9 Peripheral Frame 3 Registers

NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
Comparator 1 registers 0x00 6400 to 0x00 641F 32 (1)
Comparator 2 registers 0x00 6420 to 0x00 643F 32 (1)
Comparator 3 registers 0x00 6440 to 0x00 645F 32 (1)
ePWM1 + HRPWM1 registers 0x00 6800 to 0x00 683F 64 (1)
ePWM2 + HRPWM2 registers 0x00 6840 to 0x00 687F 64 (1)
ePWM3 + HRPWM3 registers 0x00 6880 to 0x00 68BF 64 (1)
ePWM4 + HRPWM4 registers 0x00 68C0 to 0x00 68FF 64 (1)
ePWM5 + HRPWM5 registers 0x00 6900 to 0x00 693F 64 (1)
ePWM6 + HRPWM6 registers 0x00 6940 to 0x00 697F 64 (1)
ePWM7 + HRPWM7 registers 0x00 6980 to 0x00 69BF 64 (1)
(1) Some registers are EALLOW protected. See the module reference guide for more information.