SPRSP25A June   2018  – July 2018 TMS320F28035-EP

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Signal Descriptions
      1. Table 3-1 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Power-On Hours (POH) Limits
    4. 4.4  Recommended Operating Conditions
    5. 4.5  Power Consumption Summary
      1. Table 4-1 TMS320F2803x Current Consumption at 60-MHz SYSCLKOUT
      2. 4.5.1      Reducing Current Consumption
      3. 4.5.2      Current Consumption Graphs (VREG Enabled)
    6. 4.6  Electrical Characteristics
    7. 4.7  Thermal Resistance Characteristics
    8. 4.8  Thermal Design Considerations
    9. 4.9  Emulator Connection Without Signal Buffering for the MCU
    10. 4.10 Parameter Information
      1. 4.10.1 Timing Parameter Symbology
      2. 4.10.2 General Notes on Timing Parameters
    11. 4.11 Test Load Circuit
    12. 4.12 Power Sequencing
      1. Table 4-4 Reset (XRS) Timing Requirements
      2. Table 4-5 Reset (XRS) Switching Characteristics
    13. 4.13 Clock Specifications
      1. 4.13.1 Device Clock Table
        1. Table 4-6 2803x Clock Table and Nomenclature (60-MHz Devices)
        2. Table 4-7 Device Clocking Requirements/Characteristics
        3. Table 4-8 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 4.13.2 Clock Requirements and Characteristics
        1. Table 4-9   XCLKIN Timing Requirements – PLL Enabled
        2. Table 4-10 XCLKIN Timing Requirements – PLL Disabled
        3. Table 4-11 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 4.14 Flash Timing
      1. Table 4-12 Flash/OTP Endurance
      2. Table 4-13 Flash Parameters at 60-MHz SYSCLKOUT
      3. Table 4-14 Flash/OTP Access Timing
      4. Table 4-15 Flash Data Retention Duration
  5. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1  CPU
      2. 5.1.2  Control Law Accelerator (CLA)
      3. 5.1.3  Memory Bus (Harvard Bus Architecture)
      4. 5.1.4  Peripheral Bus
      5. 5.1.5  Real-Time JTAG and Analysis
      6. 5.1.6  Flash
      7. 5.1.7  M0, M1 SARAMs
      8. 5.1.8  L0 SARAM, and L1, L2, and L3 DPSARAMs
      9. 5.1.9  Boot ROM
        1. 5.1.9.1 Emulation Boot
        2. 5.1.9.2 GetMode
        3. 5.1.9.3 Peripheral Pins Used by the Bootloader
      10. 5.1.10 Security
      11. 5.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 5.1.12 External Interrupts (XINT1–XINT3)
      13. 5.1.13 Internal Zero Pin Oscillators, Oscillator, and PLL
      14. 5.1.14 Watchdog
      15. 5.1.15 Peripheral Clocking
      16. 5.1.16 Low-power Modes
      17. 5.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 5.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 5.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 5.1.20 Control Peripherals
      21. 5.1.21 Serial Port Peripherals
    2. 5.2 Memory Maps
    3. 5.3 Register Maps
    4. 5.4 Device Emulation Registers
    5. 5.5 VREG/BOR/POR
      1. 5.5.1 On-chip Voltage Regulator (VREG)
        1. 5.5.1.1 Using the On-chip VREG
        2. 5.5.1.2 Disabling the On-chip VREG
      2. 5.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
    6. 5.6 System Control
      1. 5.6.1 Internal Zero Pin Oscillators
      2. 5.6.2 Crystal Oscillator Option
      3. 5.6.3 PLL-Based Clock Module
      4. 5.6.4 Loss of Input Clock (NMI Watchdog Function)
      5. 5.6.5 CPU-Watchdog Module
    7. 5.7 Low-Power Modes Block
    8. 5.8 Interrupts
      1. 5.8.1 External Interrupts
        1. 5.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 5-20 External Interrupt Timing Requirements
          2. Table 5-21 External Interrupt Switching Characteristics
    9. 5.9 Peripherals
      1. 5.9.1  Control Law Accelerator (CLA) Overview
      2. 5.9.2  Analog Block
        1. 5.9.2.1 Analog-to-Digital Converter (ADC)
          1. 5.9.2.1.1 Features
          2. 5.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. Table 5-26 External ADC Start-of-Conversion Switching Characteristics
          3. 5.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. Table 5-27 ADC Electrical Characteristics
            2. Table 5-28 ADC Power Modes
            3. 5.9.2.1.3.1 Internal Temperature Sensor
              1. Table 5-29 Temperature Sensor Coefficient
            4. 5.9.2.1.3.2 ADC Power-Up Control Bit Timing
              1. Table 5-30 ADC Power-Up Delays
            5. 5.9.2.1.3.3 ADC Sequential and Simultaneous Timings
        2. 5.9.2.2 ADC MUX
        3. 5.9.2.3 Comparator Block
          1. 5.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. Table 5-32 Electrical Characteristics of the Comparator/DAC
      3. 5.9.3  Detailed Descriptions
      4. 5.9.4  Serial Peripheral Interface (SPI) Module
        1. 5.9.4.1 SPI Master Mode Electrical Data/Timing
          1. Table 5-35 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 5-36 SPI Master Mode External Timing (Clock Phase = 1)
        2. 5.9.4.2 SPI Slave Mode Electrical Data/Timing
          1. Table 5-37 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 5-38 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 5.9.5  Serial Communications Interface (SCI) Module
      6. 5.9.6  Local Interconnect Network (LIN)
      7. 5.9.7  Enhanced Controller Area Network (eCAN) Module
      8. 5.9.8  Inter-Integrated Circuit (I2C)
        1. 5.9.8.1 I2C Electrical Data/Timing
          1. Table 5-44 I2C Timing Requirements
          2. Table 5-45 I2C Switching Characteristics
      9. 5.9.9  Enhanced PWM Modules (ePWM1/2/3/4/5/6/7)
        1. 5.9.9.1 ePWM Electrical Data/Timing
          1. Table 5-48 ePWM Timing Requirements
          2. Table 5-49 ePWM Switching Characteristics
        2. 5.9.9.2 Trip-Zone Input Timing
          1. Table 5-50 Trip-Zone Input Timing Requirements
      10. 5.9.10 High-Resolution PWM (HRPWM)
        1. 5.9.10.1 HRPWM Electrical Data/Timing
          1. Table 5-51 High-Resolution PWM Characteristics
      11. 5.9.11 Enhanced Capture Module (eCAP1)
        1. 5.9.11.1 eCAP Electrical Data/Timing
          1. Table 5-53 Enhanced Capture (eCAP) Timing Requirement
          2. Table 5-54 eCAP Switching Characteristics
      12. 5.9.12 High-Resolution Capture (HRCAP) Module
        1. 5.9.12.1 HRCAP Electrical Data/Timing
          1. Table 5-56 High-Resolution Capture (HRCAP) Timing Requirements
      13. 5.9.13 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 5.9.13.1 eQEP Electrical Data/Timing
          1. Table 5-58 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
          2. Table 5-59 eQEP Switching Characteristics
      14. 5.9.14 JTAG Port
      15. 5.9.15 General-Purpose Input/Output (GPIO) MUX
        1. 5.9.15.1 GPIO Electrical Data/Timing
          1. 5.9.15.1.1 GPIO - Output Timing
            1. Table 5-63 General-Purpose Output Switching Characteristics
          2. 5.9.15.1.2 GPIO - Input Timing
            1. Table 5-64 General-Purpose Input Timing Requirements
          3. 5.9.15.1.3 Sampling Window Width for Input Signals
          4. 5.9.15.1.4 Low-Power Mode Wakeup Timing
            1. Table 5-65 IDLE Mode Timing Requirements
            2. Table 5-66 IDLE Mode Switching Characteristics
            3. Table 5-67 STANDBY Mode Timing Requirements
            4. Table 5-68 STANDBY Mode Switching Characteristics
            5. Table 5-69 HALT Mode Timing Requirements
            6. Table 5-70 HALT Mode Switching Characteristics
  6. 6Applications, Implementation, and Layout
    1. 6.1 TI Design or Reference Design
  7. 7Device and Documentation Support
    1. 7.1 Getting Started
    2. 7.2 Device and Development Support Tool Nomenclature
    3. 7.3 Tools and Software
    4. 7.4 Documentation Support
    5. 7.5 Community Resources
    6. 7.6 Trademarks
    7. 7.7 Electrostatic Discharge Caution
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information
    1. 8.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3.2 Signal Descriptions

Table 3-1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. Inputs are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do not have an internal pullup.

NOTE

When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 pins could glitch during power up. This potential glitch will finish before the boot mode pins are read and will not affect boot behavior. If glitching is unacceptable in an application, 1.8 V could be supplied externally. Alternatively, adding a current-limiting resistor (for example, 470 Ω) in series with these pins and any external driver could be considered to limit the potential for degradation to the pin and/or external circuitry. There is no power-sequencing requirement when using an external 1.8-V supply. However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered before the 1.8-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins before or with the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V.

Table 3-1 Signal Descriptions(1)

TERMINAL I/O/Z DESCRIPTION
NAME PN
PIN NO.
JTAG
TRST 10 I JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE:TRST is an active high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Because this is application-specific, TI recommends validating each target board for proper operation of the debugger and the application. (↓)
TCK See GPIO38 I See GPIO38. JTAG test clock with internal pullup. (↑)
TMS See GPIO36 I See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (↑)
TDI See GPIO35 I See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (↑)
TDO See GPIO37 O/Z See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (8 mA drive)
FLASH
TEST2 38 I/O Test Pin. Reserved for TI. Must be left unconnected.
CLOCK
XCLKOUT See GPIO18 O/Z See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.
XCLKIN See GPIO19 and GPIO38 I See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to GND and the on-chip crystal oscillator must be disabled through bit 14 in the CLKCTL register. If a crystal/resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register.
NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock for normal device operation may need to incorporate some hooks to disable this path during debug using the JTAG connector. This is to prevent contention with the TCK signal, which is active during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to clock the device.
X1 52 I On-chip 1.8-V crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to GND. (I)
X2 51 O On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, it must be left unconnected. (O)
RESET
XRS 9 I/O Device Reset (in) and Watchdog Reset (out). Piccolo devices have a built-in power-on reset (POR) and brown-out reset (BOR) circuitry. During a power-on or brown-out condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is placed between XRS and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. Regardless of the source, a device reset causes the device to terminate execution. The program counter points to the address contained at the location 0x3F FFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain device with an internal pullup. (↑) If this pin is driven by an external device, TI recommends using an open-drain device.
ADC, COMPARATOR, ANALOG I/O
ADCINA7 11 I ADC Group A, Channel 7 input
ADCINA6 12 I ADC Group A, Channel 6 input
COMP3A I Comparator Input 3A
AIO6 I/O Digital AIO 6
ADCINA5 13 I ADC Group A, Channel 5 input
ADCINA4 14 I ADC Group A, Channel 4 input
COMP2A I Comparator Input 2A
AIO4 I/O Digital AIO 4
ADCINA3 15 I ADC Group A, Channel 3 input
ADCINA2 16 I ADC Group A, Channel 2 input
COMP1A I Comparator Input 1A
AIO2 I/O Digital AIO 2
ADCINA1 17 I ADC Group A, Channel 1 input
ADCINA0 18 I ADC Group A, Channel 0 input.
NOTE: VREFHI and ADCINA0 share the same pin on the 64-pin PAG device and their use is mutually exclusive to one another.
NOTE: VREFHI and ADCINA0 share the same pin on the 56-pin RSH device and their use is mutually exclusive to one another.
VREFHI 19 I ADC External Reference High – only used when in ADC external reference mode. See Section 5.9.2.1, ADC.
NOTE: VREFHI and ADCINA0 share the same pin on the 64-pin PAG device and their use is mutually exclusive to one another.
NOTE: VREFHI and ADCINA0 share the same pin on the 56-pin RSH device and their use is mutually exclusive to one another.
ADCINB7 30 I ADC Group B, Channel 7 input
ADCINB6 29 I ADC Group B, Channel 6 input
COMP3B I Comparator Input 3B
AIO14 I/O Digital AIO 14
ADCINB5 28 I ADC Group B, Channel 5 input
ADCINB4 27 I ADC Group B, Channel 4 input
COMP2B I Comparator Input 2B
AIO12 I/O Digital AIO12
ADCINB3 26 I ADC Group B, Channel 3 input
ADCINB2 25 I ADC Group B, Channel 2 input
COMP1B I Comparator Input 1B
AIO10 I/O Digital AIO 10
ADCINB1 24 I ADC Group B, Channel 1 input
ADCINB0 23 I ADC Group B, Channel 0 input
VREFLO 22 I ADC External Reference Low.
NOTE: VREFLO is always connected to VSSA on the 64-pin PAG device and on the 56-pin RSH device.
CPU AND I/O POWER
VDDA 20 Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin.
VSSA 21 Analog Ground Pin.
NOTE: VREFLO is always connected to VSSA on the 64-pin PAG device and on the 56-pin RSH device.
VDD 7 CPU and Logic Digital Power Pins. When using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground. Higher value capacitors may be used.
54
72
VDDIO 36 Digital I/O Buffers and Flash Memory Power Pin. Single supply source when VREG is enabled. Place a decoupling capacitor on each pin. The exact value should be determined by the system voltage regulation solution.
70
VSS 8 Digital Ground Pins
35
53
71
VOLTAGE REGULATOR CONTROL SIGNAL
VREGENZ 73 I Internal VREG Enable/Disable – pull low to enable VREG, pull high to disable VREG
GPIO AND PERIPHERAL SIGNALS(2)
GPIO0 69 I/O/Z General-purpose input/output 0
EPWM1A O Enhanced PWM1 Output A and HRPWM channel
– – –
– – –
GPIO1 68 I/O/Z General-purpose input/output 1
EPWM1B O Enhanced PWM1 Output B
– –
COMP1OUT O Direct output of Comparator 1
GPIO2 67 I/O/Z General-purpose input/output 2
EPWM2A O Enhanced PWM2 Output A and HRPWM channel
– –
– –
GPIO3 66 I/O/Z General-purpose input/output 3
EPWM2B O Enhanced PWM2 Output B
SPISOMIA I/O SPI-A slave out, master in
COMP2OUT O Direct output of Comparator 2
GPIO4 63 I/O/Z General-purpose input/output 4
EPWM3A O Enhanced PWM3 output A and HRPWM channel
– –
– –
GPIO5 62 I/O/Z General-purpose input/output 5
EPWM3B O Enhanced PWM3 output B
SPISIMOA I/O SPI-A slave in, master out
ECAP1 I/O Enhanced Capture input/output 1
GPIO6 50 I/O/Z General-purpose input/output 6
EPWM4A O Enhanced PWM4 output A and HRPWM channel
EPWMSYNCI I External ePWM sync pulse input
EPWMSYNCO O External ePWM sync pulse output
GPIO7 49 I/O/Z General-purpose input/output 7
EPWM4B O Enhanced PWM4 output B
SCIRXDA I SCI-A receive data
– –
GPIO8 43 I/O/Z General-purpose input/output 8
EPWM5A O Enhanced PWM5 output A and HRPWM channel
– –
ADCSOCAO O ADC start-of-conversion A
GPIO9 39 I/O/Z General-purpose input/output 9
EPWM5B O Enhanced PWM5 output B
LINTXA O LIN transmit A
HRCAP1 I High-resolution input capture 1
GPIO10 65 I/O/Z General-purpose input/output 10
EPWM6A O Enhanced PWM6 output A and HRPWM channel
– –
ADCSOCBO O ADC start-of-conversion B
GPIO11 61 I/O/Z General-purpose input/output 11
EPWM6B O Enhanced PWM6 output B
LINRXA I LIN receive A
HRCAP2 I High-resolution input capture 2
GPIO12 47 I/O/Z General-purpose input/output 12
TZ1 I Trip Zone input 1
SCITXDA O SCI-A transmit data
SPISIMOB I/O SPI-B slave in, master out.
NOTE: SPI-B is available only in the PN package.
GPIO13 76 I/O/Z General-purpose input/output 13
TZ2 I Trip Zone input 2
– –
SPISOMIB I/O SPI-B slave out, master in
GPIO14 77 I/O/Z General-purpose input/output 14
TZ3 I Trip zone input 3
LINTXA O LIN transmit
SPICLKB I/O SPI-B clock input/output
GPIO15 75 I/O/Z General-purpose input/output 15
TZ1 I Trip zone input 1
LINRXA I LIN receive
SPISTEB I/O SPI-B slave transmit enable input/output
GPIO16 46 I/O/Z General-purpose input/output 16
SPISIMOA I/O SPI-A slave in, master out
– –
TZ2 I Trip Zone input 2
GPIO17 42 I/O/Z General-purpose input/output 17
SPISOMIA I/O SPI-A slave out, master in
– –
TZ3 I Trip zone input 3
GPIO18 41 I/O/Z General-purpose input/output 18
SPICLKA I/O SPI-A clock input/output
LINTXA O LIN transmit
XCLKOUT O/Z Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.
GPIO19 55 I/O/Z General-purpose input/output 19
XCLKIN External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken not to enable this path for clocking if it is being used for the other periperhal functions
SPISTEA I/O SPI-A slave transmit enable input/output
LINRXA I LIN receive
ECAP1 I/O Enhanced Capture input/output 1
GPIO20 78 I/O/Z General-purpose input/output 20
EQEP1A I Enhanced QEP1 input A
– –
COMP1OUT O Direct output of Comparator 1
GPIO21 79 I/O/Z General-purpose input/output 21
EQEP1B I Enhanced QEP1 input B
– –
COMP2OUT O Direct output of Comparator 2
GPIO22 1 I/O/Z General-purpose input/output 22
EQEP1S I/O Enhanced QEP1 strobe
– –
LINTXA O LIN transmit
GPIO23 4 I/O/Z General-purpose input/output 23
EQEP1I I/O Enhanced QEP1 index
– –
LINRXA I LIN receive
GPIO24 80 I/O/Z General-purpose input/output 24
ECAP1 I/O Enhanced Capture input/output 1
– –
SPISIMOB I/O SPI-B slave in, master out.
NOTE: SPI-B is available only in the PN and RSH packages.
GPIO25 44 I/O/Z General-purpose input/output 25
– –
– –
SPISOMIB I/O SPI-B slave out, master in
GPIO26 37 I/O/Z General-purpose input/output 26
HRCAP1 I High-resolution input capture 1
– –
SPICLKB I/O SPI-B clock input/output
GPIO27 31 I/O/Z General-purpose input/output 27
HRCAP2 I High-resolution input capture 2
– –
SPISTEB I/O SPI-B slave transmit enable input/output
GPIO28 40 I/O/Z General-purpose input/output 28
SCIRXDA I SCI receive data
SDAA I/OD I2C data open-drain bidirectional port
TZ2 I Trip zone input 2
GPIO29 34 I/O/Z General-purpose input/output 29
SCITXDA O SCI transmit data
SCLA I/OD I2C clock open-drain bidirectional port
TZ3 I Trip zone input 3
GPIO30 33 I/O/Z General-purpose input/output 30
CANRXA I CAN receive
– –
– –
GPIO31 32 I/O/Z General-purpose input/output 31
CANTXA O CAN transmit
– –
– –
GPIO32 2 I/O/Z General-purpose input/output 32
SDAA I/OD I2C data open-drain bidirectional port
EPWMSYNCI I Enhanced PWM external sync pulse input
ADCSOCAO O ADC start-of-conversion A
GPIO33 3 I/O/Z General-Purpose Input/Output 33
SCLA I/OD I2C clock open-drain bidirectional port
EPWMSYNCO O Enhanced PWM external synch pulse output
ADCSOCBO O ADC start-of-conversion B
GPIO34 74 I/O/Z General-Purpose Input/Output 34
COMP2OUT O Direct output of Comparator 2
– –
COMP3OUT O Direct output of Comparator 3
GPIO35 59 I/O/Z General-Purpose Input/Output 35
TDI I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK
GPIO36 60 I/O/Z General-Purpose Input/Output 36
TMS I JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK.
GPIO37 58 I/O/Z General-Purpose Input/Output 37
TDO O/Z JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive)
GPIO38 57 I/O/Z General-Purpose Input/Output 38
TCK I JTAG test clock with internal pullup
XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken to not enable this path for clocking if it is being used for the other functions.
– –
GPIO39 56 I/O/Z General-Purpose Input/Output 39
– –
– –
– –
GPIO40 64 I/O/Z General-Purpose Input/Output 40
EPWM7A O Enhanced PWM7 output A and HRPWM channel
– –
– –
GPIO41 48 I/O/Z General-Purpose Input/Output 41
EPWM7B O Enhanced PWM7 output B
– –
– –
GPIO42 5 I/O/Z General-Purpose Input/Output 42
– –
– –
COMP1OUT O Direct output of Comparator 1
GPIO43 6 I/O/Z General-Purpose Input/Output 43
– –
– –
COMP2OUT O Direct output of Comparator 2
GPIO44 45 I/O/Z General-Purpose Input/Output 44
– –
– –
– –
(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown
(2) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the GPIO block and the path to the JTAG block from a pin is enabled/disabled based on the condition of the TRST signal. See the TMS320F2803x Piccolo System Control and Interrupts Reference Guide for details.