SPRS357D August   2006  – June 2020 TMS320F28044

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
      1. Table 5-1 TMS320F28044 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
      2. 5.4.1     Reducing Current Consumption
    5. 5.5  Electrical Characteristics
    6. 5.6  Thermal Resistance Characteristics for F28044 100-Ball GGM Package
    7. 5.7  Thermal Resistance Characteristics for F28044 100-Pin PZ Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  Timing and Switching Characteristics
      1. 5.9.1 Timing Parameter Symbology
        1. 5.9.1.1 General Notes on Timing Parameters
        2. 5.9.1.2 Test Load Circuit
        3. 5.9.1.3 Device Clock Table
          1. Table 5-3 TMS320x280x Clock Table and Nomenclature
      2. 5.9.2 Power Sequencing
        1. 5.9.2.1   Power Management and Supervisory Circuit Solutions
        2. Table 5-5 Reset (XRS) Timing Requirements
      3. 5.9.3 Clock Requirements and Characteristics
        1. Table 5-6 Input Clock Frequency
        2. Table 5-7 XCLKIN Timing Requirements - PLL Enabled
        3. Table 5-8 XCLKIN Timing Requirements - PLL Disabled
        4. Table 5-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      4. 5.9.4 Peripherals
        1. 5.9.4.1 General-Purpose Input/Output (GPIO)
          1. 5.9.4.1.1 GPIO - Output Timing
            1. Table 5-10 General-Purpose Output Switching Characteristics
          2. 5.9.4.1.2 GPIO - Input Timing
            1. Table 5-11 General-Purpose Input Timing Requirements
          3. 5.9.4.1.3 Sampling Window Width for Input Signals
          4. 5.9.4.1.4 Low-Power Mode Wakeup Timing
            1. Table 5-12 IDLE Mode Timing Requirements
            2. Table 5-13 IDLE Mode Switching Characteristics
            3. Table 5-14 STANDBY Mode Timing Requirements
            4. Table 5-15 STANDBY Mode Switching Characteristics
            5. Table 5-16 HALT Mode Timing Requirements
            6. Table 5-17 HALT Mode Switching Characteristics
        2. 5.9.4.2 Enhanced Control Peripherals
          1. 5.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. Table 5-18 ePWM Timing Requirements
            2. Table 5-19 ePWM Switching Characteristics
          2. 5.9.4.2.2 Trip-Zone Input Timing
            1. Table 5-20 Trip-Zone input Timing Requirements
          3. 5.9.4.2.3 High-Resolution PWM Timing
            1. Table 5-21 High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
          4. 5.9.4.2.4 ADC Start-of-Conversion Timing
            1. Table 5-22 External ADC Start-of-Conversion Switching Characteristics
        3. 5.9.4.3 External Interrupt Timing
          1. Table 5-23 External Interrupt Timing Requirements
          2. Table 5-24 External Interrupt Switching Characteristics
        4. 5.9.4.4 I2C Electrical Specification and Timing
          1. Table 5-25 I2C Timing
        5. 5.9.4.5 Serial Peripheral Interface (SPI) Master Mode Timing
          1. Table 5-26 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 5-27 SPI Master Mode External Timing (Clock Phase = 1)
        6. 5.9.4.6 SPI Slave Mode Timing
          1. Table 5-28 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 5-29 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 5.9.5 JTAG Debug Probe Connection Without Signal Buffering for the DSP
      6. 5.9.6 Flash Timing
        1. Table 5-30 Flash Endurance for A Temperature Material
        2. Table 5-31 Flash Parameters at 100-MHz SYSCLKOUT
        3. Table 5-32 Flash/OTP Access Timing
        4. Table 5-33 Flash Data Retention Duration
    10. 5.10 On-Chip Analog-to-Digital Converter
      1. Table 5-35 ADC Electrical Characteristics (over recommended operating conditions)
      2. 5.10.1     ADC Power-Up Control Bit Timing
        1. Table 5-36 ADC Power-Up Delays
        2. Table 5-37 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
      3. 5.10.2     Definitions
      4. 5.10.3     Sequential Sampling Mode (Single-Channel) (SMODE = 0)
        1. Table 5-38 Sequential Sampling Mode Timing
      5. 5.10.4     Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
        1. Table 5-39 Simultaneous Sampling Mode Timing
      6. 5.10.5     Detailed Descriptions
  6. 6Detailed Description
    1. 6.1 Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  Flash
      6. 6.1.6  M0, M1 SARAMs
      7. 6.1.7  L0, L1 SARAMs
      8. 6.1.8  Boot ROM
      9. 6.1.9  Security
      10. 6.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 6.1.11 External Interrupts (XINT1, XINT2, XNMI)
      12. 6.1.12 Oscillator and PLL
      13. 6.1.13 Watchdog
      14. 6.1.14 Peripheral Clocking
      15. 6.1.15 Low-Power Modes
      16. 6.1.16 Peripheral Frames 0, 1, 2 (PFn)
      17. 6.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 6.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 6.1.19 Control Peripherals
      20. 6.1.20 Serial Port Peripherals
    2. 6.2 Peripherals
      1. 6.2.1 32-Bit CPU-Timers 0/1/2
      2. 6.2.2 Enhanced PWM Modules (ePWM1–16)
      3. 6.2.3 Hi-Resolution PWM (HRPWM)
      4. 6.2.4 Enhanced Analog-to-Digital Converter (ADC) Module
        1. 6.2.4.1 ADC Connections if the ADC Is Not Used
        2. 6.2.4.2 ADC Registers
      5. 6.2.5 Serial Communications Interface (SCI) Module (SCI-A)
      6. 6.2.6 Serial Peripheral Interface (SPI) Module (SPI-A)
      7. 6.2.7 Inter-Integrated Circuit (I2C)
      8. 6.2.8 GPIO MUX
    3. 6.3 Memory Map
    4. 6.4 Register Map
      1. 6.4.1 Device Emulation Registers
    5. 6.5 Interrupts
      1. 6.5.1 External Interrupts
    6. 6.6 System Control
      1. 6.6.1 OSC and PLL Block
        1. 6.6.1.1 External Reference Oscillator Clock Option
        2. 6.6.1.2 PLL-Based Clock Module
        3. 6.6.1.3 Loss of Input Clock
      2. 6.6.2 Watchdog Block
    7. 6.7 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device and Development Support Tool Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZ|100
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Interrupts

Figure 6-14 shows how the various interrupt sources are multiplexed within the F28044 device.

Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. On the F28044 device, 43 of these are used by peripherals as shown in Table 6-20.

The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.

When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the vector from INT2.1 and so forth.

TMS320F28044 int_pie_prs357.gifFigure 6-14 External and PIE Interrupt Sources
TMS320F28044 muxint_prs357.gifFigure 6-15 Multiplexing of Interrupts Using the PIE Block

Table 6-20 PIE Peripheral Interrupts(1)

CPU
INTERRUPTS		 PIE INTERRUPTS
INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
INT1 WAKEINT
(LPM/WD)		 TINT0
(TIMER 0)		 ADCINT
(ADC)		 XINT2 XINT1 Reserved SEQ2INT
(ADC)		 SEQ1INT
(ADC)
INT2 EPWM8_TZINT
(ePWM8)		 EPWM7_TZINT
(ePWM7)		 EPWM6_TZINT
(ePWM6)		 EPWM5_TZINT
(ePWM5)		 EPWM4_TZINT
(ePWM4)		 EPWM3_TZINT
(ePWM3)		 EPWM2_TZINT
(ePWM2)		 EPWM1_TZINT
(ePWM1)
INT3 EPWM8_INT
(ePWM8)		 EPWM7_INT
(ePWM7)
EPWM6T_INTn
(ePWM6)		 EPWM5_INT
(ePWM5)		 EPWM4_INT
(ePWM4)		 EPWM3_INT
(ePWM3)		 EPWM2_INT
(ePWM2)		 EPWM1_INT
(ePWM1)
INT4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
INT5 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
INT6 Reserved Reserved Reserved Reserved Reserved Reserved SPITXINTA
(SPI-A)		 SPIRXINTA
(SPI-A)
INT7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
INT8 Reserved Reserved Reserved Reserved Reserved Reserved I2CINT2A
(I2C-A)		 I2CINT1A
(I2C-A)
INT9 Reserved Reserved Reserved Reserved Reserved Reserved SCITXINTA
(SCI-A)		 SCIRXINTA
(SCI-A)
INT10 EPWM16_TZINT
(ePWM16)		 EPWM15_TZINT
(ePWM15)		 EPWM14_TZINT
(ePWM14)		 EPWM13_TZINT
(ePWM13)		 EPWM12_TZINT
(ePWM12)		 EPWM11_TZINT
(ePWM11)		 EPWM10_TZINT
(ePWM10)		 EPWM9_TZINT
(ePWM9)
INT11 EPWM16_INT
(ePWM16)		 EPWM15_INT
(ePWM15)		 EPWM14_INT
(ePWM14)		 EPWM13_INT
(ePWM13)		 EPWM12_INT
(ePWM12)		 EPWM11_INT
(ePWM11)		 EPWM10_INT
(ePWM10)		 EPWM9_INT
(ePWM9)
INT12 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
(1) Out of the 96 possible interrupts, 43 interrupts are currently used. The remaining interrupts are reserved for future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
  1. No peripheral within the group is asserting interrupts.
  2. No peripheral interrupts are assigned to the group (example PIE group 12).

Table 6-21 PIE Configuration and Control Registers

NAME ADDRESS SIZE (x16) DESCRIPTION(1)
PIECTRL 0x0CE0 1 PIE, Control Register
PIEACK 0x0CE1 1 PIE, Acknowledge Register
PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register
PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register
PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register
PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register
PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register
PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register
PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register
PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register
PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register
PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register
PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register
PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register
PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register
PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register
PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register
PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register
PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register
PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register
PIEIER10 0x0CF4 1 PIE, INT10 Group Enable Register
PIEIFR10 0x0CF5 1 PIE, INT10 Group Flag Register
PIEIER11 0x0CF6 1 PIE, INT11 Group Enable Register
PIEIFR11 0x0CF7 1 PIE, INT11 Group Flag Register
PIEIER12 0x0CF8 1 PIE, INT12 Group Enable Register
PIEIFR12 0x0CF9 1 PIE, INT12 Group Flag Register
Reserved 0x0CFA –
0x0CFF		 6 Reserved
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.