SPRS357D August   2006  – June 2020 TMS320F28044

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
      1. Table 5-1 TMS320F28044 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
      2. 5.4.1     Reducing Current Consumption
    5. 5.5  Electrical Characteristics
    6. 5.6  Thermal Resistance Characteristics for F28044 100-Ball GGM Package
    7. 5.7  Thermal Resistance Characteristics for F28044 100-Pin PZ Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  Timing and Switching Characteristics
      1. 5.9.1 Timing Parameter Symbology
        1. 5.9.1.1 General Notes on Timing Parameters
        2. 5.9.1.2 Test Load Circuit
        3. 5.9.1.3 Device Clock Table
          1. Table 5-3 TMS320x280x Clock Table and Nomenclature
      2. 5.9.2 Power Sequencing
        1. 5.9.2.1   Power Management and Supervisory Circuit Solutions
        2. Table 5-5 Reset (XRS) Timing Requirements
      3. 5.9.3 Clock Requirements and Characteristics
        1. Table 5-6 Input Clock Frequency
        2. Table 5-7 XCLKIN Timing Requirements - PLL Enabled
        3. Table 5-8 XCLKIN Timing Requirements - PLL Disabled
        4. Table 5-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      4. 5.9.4 Peripherals
        1. 5.9.4.1 General-Purpose Input/Output (GPIO)
          1. 5.9.4.1.1 GPIO - Output Timing
            1. Table 5-10 General-Purpose Output Switching Characteristics
          2. 5.9.4.1.2 GPIO - Input Timing
            1. Table 5-11 General-Purpose Input Timing Requirements
          3. 5.9.4.1.3 Sampling Window Width for Input Signals
          4. 5.9.4.1.4 Low-Power Mode Wakeup Timing
            1. Table 5-12 IDLE Mode Timing Requirements
            2. Table 5-13 IDLE Mode Switching Characteristics
            3. Table 5-14 STANDBY Mode Timing Requirements
            4. Table 5-15 STANDBY Mode Switching Characteristics
            5. Table 5-16 HALT Mode Timing Requirements
            6. Table 5-17 HALT Mode Switching Characteristics
        2. 5.9.4.2 Enhanced Control Peripherals
          1. 5.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. Table 5-18 ePWM Timing Requirements
            2. Table 5-19 ePWM Switching Characteristics
          2. 5.9.4.2.2 Trip-Zone Input Timing
            1. Table 5-20 Trip-Zone input Timing Requirements
          3. 5.9.4.2.3 High-Resolution PWM Timing
            1. Table 5-21 High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
          4. 5.9.4.2.4 ADC Start-of-Conversion Timing
            1. Table 5-22 External ADC Start-of-Conversion Switching Characteristics
        3. 5.9.4.3 External Interrupt Timing
          1. Table 5-23 External Interrupt Timing Requirements
          2. Table 5-24 External Interrupt Switching Characteristics
        4. 5.9.4.4 I2C Electrical Specification and Timing
          1. Table 5-25 I2C Timing
        5. 5.9.4.5 Serial Peripheral Interface (SPI) Master Mode Timing
          1. Table 5-26 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 5-27 SPI Master Mode External Timing (Clock Phase = 1)
        6. 5.9.4.6 SPI Slave Mode Timing
          1. Table 5-28 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 5-29 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 5.9.5 JTAG Debug Probe Connection Without Signal Buffering for the DSP
      6. 5.9.6 Flash Timing
        1. Table 5-30 Flash Endurance for A Temperature Material
        2. Table 5-31 Flash Parameters at 100-MHz SYSCLKOUT
        3. Table 5-32 Flash/OTP Access Timing
        4. Table 5-33 Flash Data Retention Duration
    10. 5.10 On-Chip Analog-to-Digital Converter
      1. Table 5-35 ADC Electrical Characteristics (over recommended operating conditions)
      2. 5.10.1     ADC Power-Up Control Bit Timing
        1. Table 5-36 ADC Power-Up Delays
        2. Table 5-37 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
      3. 5.10.2     Definitions
      4. 5.10.3     Sequential Sampling Mode (Single-Channel) (SMODE = 0)
        1. Table 5-38 Sequential Sampling Mode Timing
      5. 5.10.4     Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
        1. Table 5-39 Simultaneous Sampling Mode Timing
      6. 5.10.5     Detailed Descriptions
  6. 6Detailed Description
    1. 6.1 Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  Flash
      6. 6.1.6  M0, M1 SARAMs
      7. 6.1.7  L0, L1 SARAMs
      8. 6.1.8  Boot ROM
      9. 6.1.9  Security
      10. 6.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 6.1.11 External Interrupts (XINT1, XINT2, XNMI)
      12. 6.1.12 Oscillator and PLL
      13. 6.1.13 Watchdog
      14. 6.1.14 Peripheral Clocking
      15. 6.1.15 Low-Power Modes
      16. 6.1.16 Peripheral Frames 0, 1, 2 (PFn)
      17. 6.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 6.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 6.1.19 Control Peripherals
      20. 6.1.20 Serial Port Peripherals
    2. 6.2 Peripherals
      1. 6.2.1 32-Bit CPU-Timers 0/1/2
      2. 6.2.2 Enhanced PWM Modules (ePWM1–16)
      3. 6.2.3 Hi-Resolution PWM (HRPWM)
      4. 6.2.4 Enhanced Analog-to-Digital Converter (ADC) Module
        1. 6.2.4.1 ADC Connections if the ADC Is Not Used
        2. 6.2.4.2 ADC Registers
      5. 6.2.5 Serial Communications Interface (SCI) Module (SCI-A)
      6. 6.2.6 Serial Peripheral Interface (SPI) Module (SPI-A)
      7. 6.2.7 Inter-Integrated Circuit (I2C)
      8. 6.2.8 GPIO MUX
    3. 6.3 Memory Map
    4. 6.4 Register Map
      1. 6.4.1 Device Emulation Registers
    5. 6.5 Interrupts
      1. 6.5.1 External Interrupts
    6. 6.6 System Control
      1. 6.6.1 OSC and PLL Block
        1. 6.6.1.1 External Reference Oscillator Clock Option
        2. 6.6.1.2 PLL-Based Clock Module
        3. 6.6.1.3 Loss of Input Clock
      2. 6.6.2 Watchdog Block
    7. 6.7 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device and Development Support Tool Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZ|100
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.2 Signal Descriptions

Table 4-1 describes the signals on the F28044 device. All digital inputs are TTL-compatible. All outputs are 3.3 V with CMOS levels. Inputs are not 5-V tolerant.

Table 4-1 Signal Descriptions

NAME PIN NO. DESCRIPTION (1)
PZ
PIN #		 GGM/
ZGM
BALL #
JTAG
TRST 84 A6 JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. (I, ↓)
TCK 75 A10 JTAG test clock with internal pullup (I, ↑)
TMS 74 B10 JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (I, ↑)
TDI 73 C9 JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (I, ↑)
TDO 76 B9 JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
EMU0 80 A8 Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the JTAG debug probe system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application.
EMU1 81 B7 Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the JTAG debug probe system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application.
FLASH
VDD3VFL 96 C4 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. On the ROM parts (C280x), this pin should be connected to VDDIO.
TEST1 97 A3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
TEST2 98 B3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
CLOCK
XCLKOUT 66 E8 Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during a reset. (O/Z, 8 mA drive).
XCLKIN 90 B5 External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case, the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.8-V oscillator is used to feed clock to X1 pin), this pin must be tied to GND. (I)
X1 88 E6 Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to GND. (I)
X2 86 C6 Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and X2. If X2 is not used it must be left unconnected. (O)
RESET
XRS 78 B8 Device Reset (in) and Watchdog Reset (out).
 
Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑)

The output buffer of this pin is an open-drain with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device.
ADC SIGNALS
ADCINA7 16 F3 ADC Group A, Channel 7 input (I)
ADCINA6 17 F4 ADC Group A, Channel 6 input (I)
ADCINA5 18 G4 ADC Group A, Channel 5 input (I)
ADCINA4 19 G1 ADC Group A, Channel 4 input (I)
ADCINA3 20 G2 ADC Group A, Channel 3 input (I)
ADCINA2 21 G3 ADC Group A, Channel 2 input (I)
ADCINA1 22 H1 ADC Group A, Channel 1 input (I)
ADCINA0 23 H2 ADC Group A, Channel 0 input (I)
ADCINB7 34 K5 ADC Group B, Channel 7 input (I)
ADCINB6 33 H4 ADC Group B, Channel 6 input (I)
ADCINB5 32 K4 ADC Group B, Channel 5 input (I)
ADCINB4 31 J4 ADC Group B, Channel 4 input (I)
ADCINB3 30 K3 ADC Group B, Channel 3 input (I)
ADCINB2 29 H3 ADC Group B, Channel 2 input (I)
ADCINB1 28 J3 ADC Group B, Channel 1 input (I)
ADCINB0 27 K2 ADC Group B, Channel 0 input (I)
ADCLO 24 J1 Low Reference (connect to analog ground) (I)
ADCRESEXT 38 F5 ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.
ADCREFIN 35 J5 External reference input (I)
ADCREFP 37 G5 Internal Reference Positive Output. Requires a low ESR (50 mΩ – 1.5 Ω) ceramic bypass capacitor of 2.2 μF to analog ground. (O)
ADCREFM 36 H5 Internal Reference Medium Output. Requires a low ESR (50 mΩ – 1.5 Ω) ceramic bypass capacitor of 2.2 μF to analog ground. (O)
CPU AND I/O POWER PINS
VDDA2 15 F2 ADC Analog Power Pin (3.3 V)
VSSA2 14 F1 ADC Analog Ground Pin
VDDAIO 26 J2 ADC Analog I/O Power Pin (3.3 V)
VSSAIO 25 K1 ADC Analog I/O Ground Pin
VDD1A18 12 E4 ADC Analog Power Pin (1.8 V)
VSS1AGND 13 E5 ADC Analog Ground Pin
VDD2A18 40 J6 ADC Analog Power Pin (1.8 V)
VSS2AGND 39 K6 ADC Analog Ground Pin
VDD 10 E2 CPU and Logic Digital Power Pins (1.8 V)
VDD 42 G6
VDD 59 F10
VDD 68 D7
VDD 85 B6
VDD 93 D4
VDDIO 3 C2 Digital I/O Power Pin (3.3 V)
VDDIO 46 H7
VDDIO 65 E9
VDDIO 82 A7
VSS 2 B1 Digital Ground Pins
VSS 11 E3
VSS 41 H6
VSS 49 K9
VSS 55 H10
VSS 62 F7
VSS 69 D10
VSS 77 A9
VSS 87 D6
VSS 89 A5
VSS 94 A4
GPIOA AND PERIPHERAL SIGNALS(2)
GPIO0
EPWM1A
-
-		 47 K8 General purpose input/output 0 (I/O/Z) (3)
Enhanced PWM1 Output and HRPWM channel (O)
-
-
GPIO1
EPWM2A
-
-		 44 K7 General purpose input/output 1 (I/O/Z)(3)
Enhanced PWM2 Output A and HRPWM channel (O)
-
-
GPIO2
EPWM3A
-
-		 45 J7 General purpose input/output 2 (I/O/Z)(3)
Enhanced PWM3 Output A and HRPWM channel (O)
-
-
GPIO3
EPWM4A
-
-		 48 J8 General purpose input/output 3 (I/O/Z)(3)
Enhanced PWM4 Output A and HRPWM channel (O)
-
-
GPIO4
EPWM5A
-
-		 51 J9 General purpose input/output 4 (I/O/Z)(3)
Enhanced PWM5 output A and HRPWM channel (O)
-
-
GPIO5
EPWM6A
-
- 		53 H9 General purpose input/output 5 (I/O/Z)(3)
Enhanced PWM6 Output A and HRPWM channel (O)
-
-
GPIO6
EPWM7A
EPWMSYNCI
EPWMSYNCO 		56 G9 General purpose input/output 6 (I/O/Z)(3)
Enhanced PWM7 output A and HRPWM channel (O)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
GPIO7
EPWM8A
-		 58 G8 General purpose input/output 7 (I/O/Z)(3)
Enhanced PWM8 Output A and HRPWM channel (O)
-
GPIO8
EPWM9A
-
ADCSOCAO 		60 F9 General purpose input/output 8 (I/O/Z)(3)
Enhanced PWM9 output A(O)
-
ADC start-of-conversion A (O)
GPIO9
EPWM10A
-		 61 F8 General purpose input/output 9 (I/O/Z)(3)
Enhanced PWM10 Output A and HRPWM channel (O)
-
GPIO10
EPWM11A
-
ADCSOCBO 		64 E10 General purpose input/output 10 (I/O/Z)(3)
Enhanced PWM11 Output A and HRPWM channel (O)
-
ADC start-of-conversion B (O)
GPIO11
EPWM12A
-		 70 D9 General purpose input/output 11 (I/O/Z)(3)
Enhanced PWM12 Output A and HRPWM channel (O)
-
GPIO12
TZ1
EPWM13A
-		 1 B2 General purpose input/output 12 (I/O/Z)(4)
Trip Zone input 1 (I)
Enhanced PWM13 Output A and HRPWM channel (O)
-
GPIO13
TZ2
EPWM14A
-		 95 B4 General purpose input/output 13 (I/O/Z)(4)
Trip zone input 2 (I)
Enhanced PWM14 Output A and HRPWM channel (O)
-
GPIO14
TZ3
EPWM15A
-		 8 D3 General purpose input/output 14 (I/O/Z)(4)
Trip zone input 3 (I)
Enhanced PWM15 Output A and HRPWM channel (O)
-
GPIO15
TZ4
EPWM16A
-		 9 E1 General purpose input/output 15 (I/O/Z)(4)
Trip zone input 4 (I)
Enhanced PWM16 Output A and HRPWM channel (O)
-
GPIO16
SPISIMOA
-
TZ5 		50 K10 General purpose input/output 16 (I/O/Z)(4)
SPI-A slave in, master out (I/O)
-
Trip zone input 5 (I)
GPIO17
SPISOMIA
-
TZ6 		52 J10 General purpose input/output 17 (I/O/Z)(4)
SPI-A slave out, master in (I/O)
-
Trip zone input 6(I)
GPIO18
SPICLKA
-
TZ1 		54 H8 General purpose input/output 18 (I/O/Z)(4)
SPI-A clock input/output (I/O)
-
Trip zone input 1 (I)
GPIO19
SPISTEA
-
TZ2 		57 G10 General purpose input/output 19 (I/O/Z)(4)
SPI-A slave transmit enable input/output (I/O)
-
Trip zone input 2 (I)
GPIO20
-
-
-		 63 F6 General purpose input/output 20 (I/O/Z)(4)
-
-
-
GPIO21
-
-
-		 67 E7 General purpose input/output 21 (I/O/Z)(4)
-
-
-
GPIO22
-
-
-		 71 D8 General purpose input/output 22 (I/O/Z)(4)
-
-
-
GPIO23
-
-
-		 72 C10 General purpose input/output 23 (I/O/Z)(4)
-
-
-
GPIO24
-
-
-		 83 C7 General purpose input/output 24 (I/O/Z)(4)
-
-
-
GPIO25
-
-
-		 91 C5 General purpose input/output 25 (I/O/Z)(4)
-
-
-
GPIO26
-
-
-		 99 A2 General purpose input/output 26 (I/O/Z)(4)
-
-
-
GPIO27
-
-
-		 79 C8 General purpose input/output 27 (I/O/Z)(4)
-
-
-
GPIO28
SCIRXDA
-
TZ5 		92 D5 General purpose input/output 28. This pin has an 8-mA (typical) output buffer. (I/O/Z)(4)
SCI receive data (I)
-
Trip zone 5 (I)
GPIO29
SCITXDA
-
TZ6 		4 C3 General purpose input/output 29. This pin has an 8-mA (typical) output buffer. (I/O/Z)(4)
SCI transmit data (O)
-
Trip zone 6 (I)
GPIO30
-
-
TZ3 		6 D2 General purpose input/output 30. This pin has an 8-mA (typical) output buffer. (I/O/Z)(4)
-
-
Trip zone input 3 (I)
GPIO31
-
-
TZ4 		7 D1 General purpose input/output 31. This pin has an 8-mA (typical) output buffer. (I/O/Z)(4)
-
-
Trip zone input 4 (I)
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO 		100 A1 General purpose input/output 32 (I/O/Z)(4)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion (O)
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO 		5 C1 General-Purpose Input/Output 33 (I/O/Z)(4)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion (O)
GPIO34
-
-
-		 43 G7 General-Purpose Input/Output 34 (I/O/Z)(4)
-
-
-
(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown
(2) All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.
(3) The pullups on GPIO0–GPIO15 pins are not enabled at reset.
(4) The pullups on GPIO16–GPIO34 are enabled upon reset.