SPRS698J November 2010 – September 2021 TMS320F28062 , TMS320F28062F , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28067 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069F , TMS320F28069M
PRODUCTION DATA
The device contains an enhanced capture (eCAP) module. Figure 8-51 shows a functional block diagram of a module.
The eCAP module is clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for low-power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
NAME | eCAP1 | eCAP2 | eCAP3 | SIZE (×16) | EALLOW PROTECTED | DESCRIPTION |
---|---|---|---|---|---|---|
TSCTR | 0x6A00 | 0x6A20 | 0x6A40 | 2 | No | Timestamp Counter |
CTRPHS | 0x6A02 | 0x6A22 | 0x6A42 | 2 | No | Counter Phase Offset Value Register |
CAP1 | 0x6A04 | 0x6A24 | 0x6A44 | 2 | No | Capture 1 Register |
CAP2 | 0x6A06 | 0x6A26 | 0x6A46 | 2 | No | Capture 2 Register |
CAP3 | 0x6A08 | 0x6A28 | 0x6A48 | 2 | No | Capture 3 Register |
CAP4 | 0x6A0A | 0x6A2A | 0x6A4A | 2 | No | Capture 4 Register |
Reserved | 0x6A0C to 0x6A12 | 0x6A2C to 0x6A32 | 0x6A4C to 0x6A52 | 8 | No | Reserved |
ECCTL1 | 0x6A14 | 0x6A34 | 0x6A54 | 1 | No | Capture Control Register 1 |
ECCTL2 | 0x6A15 | 0x6A35 | 0x6A55 | 1 | No | Capture Control Register 2 |
ECEINT | 0x6A16 | 0x6A36 | 0x6A56 | 1 | No | Capture Interrupt Enable Register |
ECFLG | 0x6A17 | 0x6A37 | 0x6A57 | 1 | No | Capture Interrupt Flag Register |
ECCLR | 0x6A18 | 0x6A38 | 0x6A58 | 1 | No | Capture Interrupt Clear Register |
ECFRC | 0x6A19 | 0x6A39 | 0x6A59 | 1 | No | Capture Interrupt Force Register |
Reserved | 0x6A1A to 0x6A1F | 0x6A3A to 0x6A3F | 0x6A5A to 0x6A5F | 6 | No | Reserved |