SPRS902K October   2014  – February 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Signal Descriptions
      1. 5.2.1 Signal Descriptions
    3. 5.3 Pins With Internal Pullup and Pulldown
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Input X-BAR
      3. 5.4.3 Output X-BAR and ePWM X-BAR
      4. 5.4.4 USB Pin Muxing
      5. 5.4.5 High-Speed SPI Pin Muxing
    5. 5.5 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 Device Current Consumption at 120-MHz SYSCLK
      2. 6.5.2 Device Current Consumption at 120-MHz SYSCLK With the Internal VREG Enabled
      3. 6.5.3 Current Consumption Graphs
      4. 6.5.4 Reducing Current Consumption
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics
      1. 6.7.1 PTP Package
      2. 6.7.2 PZP Package
    8. 6.8  Thermal Design Considerations
    9. 6.9  System
      1. 6.9.1  Power Management
        1. 6.9.1.1 Internal 1.2-V VREG
        2. 6.9.1.2 Power Sequencing
          1. 6.9.1.2.1 Signal Pin Requirements
          2. 6.9.1.2.2 VDDIO, VDDA, VDD3VFL, and VDDOSC Requirements
          3. 6.9.1.2.3 VDD Requirements
          4. 6.9.1.2.4 Supply Ramp Rate
            1. 6.9.1.2.4.1 Supply Ramp Rate
          5. 6.9.1.2.5 Supply Supervision
      2. 6.9.2  Reset Timing
        1. 6.9.2.1 Reset Sources
        2. 6.9.2.2 Reset Electrical Data and Timing
          1. 6.9.2.2.1 Reset ( XRS) Timing Requirements
          2. 6.9.2.2.2 Reset ( XRS) Switching Characteristics
      3. 6.9.3  Clock Specifications
        1. 6.9.3.1 Clock Sources
        2. 6.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.9.3.2.1.1 Input Clock Frequency
            2. 6.9.3.2.1.2 X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
            3. 6.9.3.2.1.3 XTAL Oscillator Characteristics
            4. 6.9.3.2.1.4 X1 Timing Requirements
            5. 6.9.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.9.3.2.1.6 PLL Lock Times
          2. 6.9.3.2.2 Internal Clock Frequencies
            1. 6.9.3.2.2.1 Internal Clock Frequencies
          3. 6.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. 6.9.3.2.3.1 Output Clock Frequency
            2. 6.9.3.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        3. 6.9.3.3 Input Clocks and PLLs
        4. 6.9.3.4 XTAL Oscillator
          1. 6.9.3.4.1 Introduction
          2. 6.9.3.4.2 Overview
            1. 6.9.3.4.2.1 Electrical Oscillator
              1. 6.9.3.4.2.1.1 Modes of Operation
                1. 6.9.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.9.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.9.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.9.3.4.2.2 Quartz Crystal
          3. 6.9.3.4.3 Functional Operation
            1. 6.9.3.4.3.1 ESR – Effective Series Resistance
            2. 6.9.3.4.3.2 Rneg – Negative Resistance
            3. 6.9.3.4.3.3 Start-up Time
            4. 6.9.3.4.3.4 DL – Drive Level
          4. 6.9.3.4.4 How to Choose a Crystal
          5. 6.9.3.4.5 Testing
          6. 6.9.3.4.6 Common Problems and Debug Tips
          7. 6.9.3.4.7 Crystal Oscillator Specifications
            1. 6.9.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.9.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
        5. 6.9.3.5 Internal Oscillators
          1. 6.9.3.5.1 Internal Oscillator Electrical Characteristics
      4. 6.9.4  Flash Parameters
        1. 6.9.4.1 Flash Parameters
      5. 6.9.5  RAM Specifications
      6. 6.9.6  ROM Specifications
      7. 6.9.7  Emulation/JTAG
        1. 6.9.7.1 JTAG Electrical Data and Timing
          1. 6.9.7.1.1 JTAG Timing Requirements
          2. 6.9.7.1.2 JTAG Switching Characteristics
      8. 6.9.8  GPIO Electrical Data and Timing
        1. 6.9.8.1 GPIO - Output Timing
          1. 6.9.8.1.1 General-Purpose Output Switching Characteristics
        2. 6.9.8.2 GPIO - Input Timing
          1. 6.9.8.2.1 General-Purpose Input Timing Requirements
        3. 6.9.8.3 Sampling Window Width for Input Signals
      9. 6.9.9  Interrupts
        1. 6.9.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.9.9.1.1 External Interrupt Timing Requirements
          2. 6.9.9.1.2 External Interrupt Switching Characteristics
      10. 6.9.10 Low-Power Modes
        1. 6.9.10.1 Clock-Gating Low-Power Modes
        2. 6.9.10.2 Power-Gating Low-Power Modes
        3. 6.9.10.3 Low-Power Mode Wakeup Timing
          1. 6.9.10.3.1 IDLE Mode Timing Requirements
          2. 6.9.10.3.2 IDLE Mode Switching Characteristics
          3. 6.9.10.3.3 STANDBY Mode Timing Requirements
          4. 6.9.10.3.4 STANDBY Mode Switching Characteristics
          5. 6.9.10.3.5 HALT Mode Timing Requirements
          6. 6.9.10.3.6 HALT Mode Switching Characteristics
          7. 6.9.10.3.7 HIBERNATE Mode Timing Requirements
          8. 6.9.10.3.8 HIBERNATE Mode Switching Characteristics
      11. 6.9.11 External Memory Interface (EMIF)
        1. 6.9.11.1 Asynchronous Memory Support
        2. 6.9.11.2 Synchronous DRAM Support
        3. 6.9.11.3 EMIF Electrical Data and Timing
          1. 6.9.11.3.1 Asynchronous RAM
            1. 6.9.11.3.1.1 EMIF Asynchronous Memory Timing Requirements
            2. 6.9.11.3.1.2 EMIF Asynchronous Memory Switching Characteristics
          2. 6.9.11.3.2 Synchronous RAM
            1. 6.9.11.3.2.1 EMIF Synchronous Memory Timing Requirements
            2. 6.9.11.3.2.2 EMIF Synchronous Memory Switching Characteristics
    10. 6.10 Analog Peripherals
      1. 6.10.1 Analog-to-Digital Converter (ADC)
        1. 6.10.1.1 ADC Configurability
          1. 6.10.1.1.1 Signal Mode
        2. 6.10.1.2 ADC Electrical Data and Timing
          1. 6.10.1.2.1 ADC Operating Conditions
          2. 6.10.1.2.2 ADC Characteristics
          3. 6.10.1.2.3 ADCEXTSOC Timing Requirements
          4. 6.10.1.2.4 ADC Input Model
            1. 6.10.1.2.4.1 Single-Ended Input Model Parameters
          5. 6.10.1.2.5 ADC Timing Diagrams
            1. 6.10.1.2.5.1 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
        3. 6.10.1.3 Temperature Sensor Electrical Data and Timing
          1. 6.10.1.3.1 Temperature Sensor Electrical Characteristics
      2. 6.10.2 Comparator Subsystem (CMPSS)
        1. 6.10.2.1 CMPSS Electrical Data and Timing
          1. 6.10.2.1.1 Comparator Electrical Characteristics
          2. 6.10.2.1.2 CMPSS DAC Static Electrical Characteristics
      3. 6.10.3 Buffered Digital-to-Analog Converter (DAC)
        1. 6.10.3.1 Buffered DAC Electrical Data and Timing
          1. 6.10.3.1.1 Buffered DAC Electrical Characteristics
        2. 6.10.3.2 CMPSS DAC Dynamic Error
    11. 6.11 Control Peripherals
      1. 6.11.1 Enhanced Capture (eCAP)
        1. 6.11.1.1 eCAP Electrical Data and Timing
          1. 6.11.1.1.1 eCAP Timing Requirement
          2. 6.11.1.1.2 eCAP Switching Characteristics
      2. 6.11.2 Enhanced Pulse Width Modulator (ePWM)
        1. 6.11.2.1 Control Peripherals Synchronization
        2. 6.11.2.2 ePWM Electrical Data and Timing
          1. 6.11.2.2.1 ePWM Timing Requirements
          2. 6.11.2.2.2 ePWM Switching Characteristics
          3. 6.11.2.2.3 Trip-Zone Input Timing
            1. 6.11.2.2.3.1 Trip-Zone Input Timing Requirements
        3. 6.11.2.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 6.11.2.3.1 External ADC Start-of-Conversion Switching Characteristics
      3. 6.11.3 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.11.3.1 eQEP Electrical Data and Timing
          1. 6.11.3.1.1 eQEP Timing Requirements
          2. 6.11.3.1.2 eQEP Switching Characteristics
      4. 6.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.11.4.1 HRPWM Electrical Data and Timing
          1. 6.11.4.1.1 High-Resolution PWM Timing Requirements
          2. 6.11.4.1.2 High-Resolution PWM Characteristics
      5. 6.11.5 Sigma-Delta Filter Module (SDFM)
        1. 6.11.5.1 SDFM Electrical Data and Timing (Using ASYNC)
          1. 6.11.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
        2. 6.11.5.2 SDFM Electrical Data and Timing (Using 3-Sample GPIO Input Qualification)
          1. 6.11.5.2.1 SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window) Option
    12. 6.12 Communications Peripherals
      1. 6.12.1 Controller Area Network (CAN)
      2. 6.12.2 Inter-Integrated Circuit (I2C)
        1. 6.12.2.1 I2C Electrical Data and Timing
          1. 6.12.2.1.1 I2C Timing Requirements
          2. 6.12.2.1.2 I2C Switching Characteristics
          3. 6.12.2.1.3 I2C Timing Diagram
      3. 6.12.3 Multichannel Buffered Serial Port (McBSP)
        1. 6.12.3.1 McBSP Electrical Data and Timing
          1. 6.12.3.1.1 McBSP Transmit and Receive Timing
            1. 6.12.3.1.1.1 McBSP Timing Requirements
            2. 6.12.3.1.1.2 McBSP Switching Characteristics
          2. 6.12.3.1.2 McBSP as SPI Master or Slave Timing
            1. 6.12.3.1.2.1 McBSP as SPI Master Timing Requirements
            2. 6.12.3.1.2.2 McBSP as SPI Master Switching Characteristics
            3. 6.12.3.1.2.3 McBSP as SPI Slave Timing Requirements
            4. 6.12.3.1.2.4 McBSP as SPI Slave Switching Characteristics
      4. 6.12.4 Serial Communications Interface (SCI)
      5. 6.12.5 Serial Peripheral Interface (SPI)
        1. 6.12.5.1 SPI Electrical Data and Timing
          1. 6.12.5.1.1 SPI Master Mode Timings
            1. 6.12.5.1.1.1 SPI Master Mode Timing Requirements
            2. 6.12.5.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            3. 6.12.5.1.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
          2. 6.12.5.1.2 SPI Slave Mode Timings
            1. 6.12.5.1.2.1 SPI Slave Mode Timing Requirements
            2. 6.12.5.1.2.2 SPI Slave Mode Switching Characteristics
      6. 6.12.6 Universal Serial Bus (USB) Controller
        1. 6.12.6.1 USB Electrical Data and Timing
          1. 6.12.6.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.12.6.1.2 USB Output Ports DP and DM Switching Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 C28x Memory Map
      2. 7.3.2 Flash Memory Map
      3. 7.3.3 EMIF Chip Select Memory Map
      4. 7.3.4 Peripheral Registers Memory Map
      5. 7.3.5 Memory Types
        1. 7.3.5.1 Dedicated RAM (Mx and Dx RAM)
        2. 7.3.5.2 Local Shared RAM (LSx RAM)
        3. 7.3.5.3 Global Shared RAM (GSx RAM)
        4. 7.3.5.4 CLA Message RAM (CLA MSGRAM)
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit
      2. 7.6.2 Trigonometric Math Unit
    7. 7.7  Control Law Accelerator
    8. 7.8  Direct Memory Access
    9. 7.9  Boot ROM and Peripheral Booting
      1. 7.9.1 EMU Boot or Emulation Boot
      2. 7.9.2 WAIT Boot Mode
      3. 7.9.3 Get Mode
      4. 7.9.4 Peripheral Pins Used by Bootloaders
    10. 7.10 Dual Code Security Module
    11. 7.11 Timers
    12. 7.12 Nonmaskable Interrupt With Watchdog Timer (NMIWD)
    13. 7.13 Watchdog
    14. 7.14 Configurable Logic Block (CLB)
    15. 7.15 Functional Safety
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 Servo Drive Control Module
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Servo Drive Control Module Resources
        2. 8.3.1.2 Solar Micro Inverter
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 Solar Micro Inverter Resources
        3. 8.3.1.3 On-Board Charger (OBC)
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 OBC Resources
        4. 8.3.1.4 EV Charging Station Power Module
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 EV Charging Station Power Module Resources
        5. 8.3.1.5 High-Voltage Traction Inverter
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 High-Voltage Traction Inverter Resources
        6. 8.3.1.6 Single-Phase Online UPS
          1. 8.3.1.6.1 System Block Diagram
          2. 8.3.1.6.2 Single-Phase Online UPS Resources
  10. 9 Device and Documentation Support
    1. 9.1 Device and Development Support Tool Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZP|100
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.2.1 Signal Descriptions

Table 5-1 Signal Descriptions
TERMINALI/O/Z(1)DESCRIPTION
NAMEMUX POSITIONPTP
PIN
NO.		PZP
PIN
NO.
ADC, DAC, AND COMPARATOR SIGNALS
VREFHIA3719IADC-A high reference. This voltage must be driven into the pin from external circuitry. Place at least a 1-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHIA and VREFLOA pins.
NOTE: Do not load this pin externally.
VREFHIB5337IADC-B high reference. This voltage must be driven into the pin from external circuitry. Place at least a 1-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHIB and VREFLOB pins.
NOTE: Do not load this pin externally.
VREFHID55–IADC-D high reference. This voltage must be driven into the pin from external circuitry. Place at least a 1-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHID and VREFLOD pins.
NOTE: Do not load this pin externally.
VREFLOA3317IADC-A low reference.
On the PZP package, pin 17 is double-bonded to VSSA and VREFLOA. On the PZP package, pin 17 must be connected to VSSA on the system board.
VREFLOB5034IADC-B low reference
VREFLOD51–IADC-D low reference
ADCIN144426IInput 14 to all ADCs. This pin can be used as a general-purpose ADCIN pin or it can be used to calibrate all ADCs together from an external reference.
CMPIN4PIComparator 4 positive input
ADCIN154527IInput 15 to all ADCs. This pin can be used as a general-purpose ADCIN pin or it can be used to calibrate all ADCs together from an external reference.
CMPIN4NIComparator 4 negative input
ADCINA04325IADC-A input 0. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled.
DACOUTAODAC-A output
ADCINA14224IADC-A input 1. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled.
DACOUTBODAC-B output
ADCINA24123IADC-A input 2
CMPIN1PIComparator 1 positive input
ADCINA34022IADC-A input 3
CMPIN1NIComparator 1 negative input
ADCINA43921IADC-A input 4
CMPIN2PIComparator 2 positive input
ADCINA53820IADC-A input 5
CMPIN2NIComparator 2 negative input
ADCINB04628IADC-B input 0. There is a 100-pF capacitor to VSSA on this pin in both ADC input or DAC reference mode which cannot be disabled. If this pin is being used as a reference for the on-chip DACs, place at least a 1-µF capacitor on this pin.
VDACIOptional external reference voltage for on-chip DACs. There is a 100-pF capacitor to VSSA on this pin in both ADC input or DAC reference mode which cannot be disabled. If this pin is being used as a reference for the on-chip DACs, place at least a 1-µF capacitor on this pin.
ADCINB14729IADC-B input 1. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled.
DACOUTCODAC-C output
ADCINB24830IADC-B input 2
CMPIN3PIComparator 3 positive input
ADCINB34931IADC-B input 3
CMPIN3NIComparator 3 negative input
ADCINB4–32IADC-B input 4
ADCINB5–33IADC-B input 5
CMPIN6P31–IComparator 6 positive input
CMPIN6N30–IComparator 6 negative input
CMPIN5P29–IComparator 5 positive input
ADCIND056–IADC-D input 0
CMPIN7PIComparator 7 positive input
ADCIND157–IADC-D input 1
CMPIN7NIComparator 7 negative input
ADCIND258–IADC-D input 2
CMPIN8PIComparator 8 positive input
ADCIND359–IADC-D input 3
CMPIN8NIComparator 8 negative input
ADCIND460–IADC-D input 4
GPIO AND PERIPHERAL SIGNALS
GPIO00, 4, 8, 12160–I/OGeneral-purpose input/output 0
EPWM1A1OEnhanced PWM1 output A (HRPWM-capable)
SDAA6I/ODI2C-A data open-drain bidirectional port
GPIO10, 4, 8, 12161–I/OGeneral-purpose input/output 1
EPWM1B1OEnhanced PWM1 output B (HRPWM-capable)
MFSRB3I/OMcBSP-B receive frame synch
SCLA6I/ODI2C-A clock open-drain bidirectional port
GPIO20, 4, 8, 1216291I/OGeneral-purpose input/output 2
EPWM2A1OEnhanced PWM2 output A (HRPWM-capable)
OUTPUTXBAR15OOutput 1 of the output XBAR
SDAB6I/ODI2C-B data open-drain bidirectional port
GPIO30, 4, 8, 1216392I/OGeneral-purpose input/output 3
EPWM2B1OEnhanced PWM2 output B (HRPWM-capable)
OUTPUTXBAR22OOutput 2 of the output XBAR
MCLKRB3I/OMcBSP-B receive clock
OUTPUTXBAR25OOutput 2 of the output XBAR
SCLB6I/ODI2C-B clock open-drain bidirectional port
GPIO40, 4, 8, 1216493I/OGeneral-purpose input/output 4
EPWM3A1OEnhanced PWM3 output A (HRPWM-capable)
OUTPUTXBAR35OOutput 3 of the output XBAR
CANTXA6OCAN-A transmit
GPIO50, 4, 8, 12165–I/OGeneral-purpose input/output 5
EPWM3B1OEnhanced PWM3 output B (HRPWM-capable)
MFSRA2I/OMcBSP-A receive frame synch
OUTPUTXBAR33OOutput 3 of the output XBAR
CANRXA6ICAN-A receive
GPIO60, 4, 8, 12166–I/OGeneral-purpose input/output 6
EPWM4A1OEnhanced PWM4 output A (HRPWM-capable)
OUTPUTXBAR42OOutput 4 of the output XBAR
EXTSYNCOUT3OExternal ePWM synch pulse output
EQEP3A5IEnhanced QEP3 input A
CANTXB6OCAN-B transmit
GPIO70, 4, 8, 12167–I/OGeneral-purpose input/output 7
EPWM4B1OEnhanced PWM4 output B (HRPWM-capable)
MCLKRA2I/OMcBSP-A receive clock
OUTPUTXBAR53OOutput 5 of the output XBAR
EQEP3B5IEnhanced QEP3 input B
CANRXB6ICAN-B receive
GPIO80, 4, 8, 1218–I/OGeneral-purpose input/output 8
EPWM5A1OEnhanced PWM5 output A (HRPWM-capable)
CANTXB2OCAN-B transmit
ADCSOCAO3OADC start-of-conversion A output for external ADC
EQEP3S5I/OEnhanced QEP3 strobe
SCITXDA6OSCI-A transmit data
GPIO90, 4, 8, 1219–I/OGeneral-purpose input/output 9
EPWM5B1OEnhanced PWM5 output B (HRPWM-capable)
SCITXDB2OSCI-B transmit data
OUTPUTXBAR63OOutput 6 of the output XBAR
EQEP3I5I/OEnhanced QEP3 index
SCIRXDA6ISCI-A receive data
GPIO100, 4, 8, 121100I/OGeneral-purpose input/output 10
EPWM6A1OEnhanced PWM6 output A (HRPWM-capable)
CANRXB2ICAN-B receive
ADCSOCBO3OADC start-of-conversion B output for external ADC
EQEP1A5IEnhanced QEP1 input A
SCITXDB6OSCI-B transmit data
GPIO110, 4, 8, 1221I/OGeneral-purpose input/output 11
EPWM6B1OEnhanced PWM6 output B (HRPWM-capable)
SCIRXDB2, 6ISCI-B receive data
OUTPUTXBAR73OOutput 7 of the output XBAR
EQEP1B5IEnhanced QEP1 input B
GPIO120, 4, 8, 1243I/OGeneral-purpose input/output 12
EPWM7A1OEnhanced PWM7 output A (HRPWM-capable)
CANTXB2OCAN-B transmit
MDXB3OMcBSP-B transmit serial data
EQEP1S5I/OEnhanced QEP1 strobe
SCITXDC6OSCI-C transmit data
GPIO130, 4, 8, 1254I/OGeneral-purpose input/output 13
EPWM7B1OEnhanced PWM7 output B (HRPWM-capable)
CANRXB2ICAN-B receive
MDRB3IMcBSP-B receive serial data
EQEP1I5I/OEnhanced QEP1 index
SCIRXDC6ISCI-C receive data
GPIO140, 4, 8, 1265I/OGeneral-purpose input/output 14
EPWM8A1OEnhanced PWM8 output A (HRPWM-capable)
SCITXDB2OSCI-B transmit data
MCLKXB3I/OMcBSP-B transmit clock
OUTPUTXBAR36OOutput 3 of the output XBAR
GPIO150, 4, 8, 1276I/OGeneral-purpose input/output 15
EPWM8B1OEnhanced PWM8 output B (HRPWM-capable)
SCIRXDB2ISCI-B receive data
MFSXB3I/OMcBSP-B transmit frame synch
OUTPUTXBAR46OOutput 4 of the output XBAR
GPIO160, 4, 8, 1287I/OGeneral-purpose input/output 16
SPISIMOA1I/OSPI-A slave in, master out
CANTXB2OCAN-B transmit
OUTPUTXBAR73OOutput 7 of the output XBAR
EPWM9A5OEnhanced PWM9 output A
SD1_D17ISigma-Delta 1 channel 1 data input
GPIO170, 4, 8, 1298I/OGeneral-purpose input/output 17
SPISOMIA1I/OSPI-A slave out, master in
CANRXB2ICAN-B receive
OUTPUTXBAR83OOutput 8 of the output XBAR
EPWM9B5OEnhanced PWM9 output B
SD1_C17ISigma-Delta 1 channel 1 clock input
GPIO180, 4, 8, 12109I/OGeneral-purpose input/output 18
SPICLKA1I/OSPI-A clock
SCITXDB2OSCI-B transmit data
CANRXA3ICAN-A receive
EPWM10A5OEnhanced PWM10 output A
SD1_D27ISigma-Delta 1 channel 2 data input
GPIO190, 4, 8, 121211I/OGeneral-purpose input/output 19
SPISTEA1I/OSPI-A slave transmit enable
SCIRXDB2ISCI-B receive data
CANTXA3OCAN-A transmit
EPWM10B5OEnhanced PWM10 output B
SD1_C27ISigma-Delta 1 channel 2 clock input
GPIO200, 4, 8, 121312I/OGeneral-purpose input/output 20
EQEP1A1IEnhanced QEP1 input A
MDXA2OMcBSP-A transmit serial data
CANTXB3OCAN-B transmit
EPWM11A5OEnhanced PWM11 output A
SD1_D37ISigma-Delta 1 channel 3 data input
GPIO210, 4, 8, 121413I/OGeneral-purpose input/output 21
EQEP1B1IEnhanced QEP1 input B
MDRA2IMcBSP-A receive serial data
CANRXB3ICAN-B receive
EPWM11B5OEnhanced PWM11 output B
SD1_C37ISigma-Delta 1 channel 3 clock input
GPIO220, 4, 8, 1222–I/OGeneral-purpose input/output 22
EQEP1S1I/OEnhanced QEP1 strobe
MCLKXA2I/OMcBSP-A transmit clock
SCITXDB3OSCI-B transmit data
EPWM12A5OEnhanced PWM12 output A
SPICLKB6I/OSPI-B clock
SD1_D47ISigma-Delta 1 channel 4 data input
GPIO230, 4, 8, 1223–I/OGeneral-purpose input/output 23
EQEP1I1I/OEnhanced QEP1 index
MFSXA2I/OMcBSP-A transmit frame synch
SCIRXDB3ISCI-B receive data
EPWM12B5OEnhanced PWM12 output B
SPISTEB6I/OSPI-B slave transmit enable
SD1_C47ISigma-Delta 1 channel 4 clock input
GPIO240, 4, 8, 1224–I/OGeneral-purpose input/output 24
OUTPUTXBAR11OOutput 1 of the output XBAR
EQEP2A2IEnhanced QEP2 input A
MDXB3OMcBSP-B transmit serial data
SPISIMOB6I/OSPI-B slave in, master out
SD2_D17ISigma-Delta 2 channel 1 data input
GPIO250, 4, 8, 1225–I/OGeneral-purpose input/output 25
OUTPUTXBAR21OOutput 2 of the output XBAR
EQEP2B2IEnhanced QEP2 input B
MDRB3IMcBSP-B receive serial data
SPISOMIB6I/OSPI-B slave out, master in
SD2_C17ISigma-Delta 2 channel 1 clock input
GPIO260, 4, 8, 1227–I/OGeneral-purpose input/output 26
OUTPUTXBAR31OOutput 3 of the output XBAR
EQEP2I2I/OEnhanced QEP2 index
MCLKXB3I/OMcBSP-B transmit clock
OUTPUTXBAR35OOutput 3 of the output XBAR
SPICLKB6I/OSPI-B clock
SD2_D27ISigma-Delta 2 channel 2 data input
GPIO270, 4, 8, 1228–I/OGeneral-purpose input/output 27
OUTPUTXBAR41OOutput 4 of the output XBAR
EQEP2S2I/OEnhanced QEP2 strobe
MFSXB3I/OMcBSP-B transmit frame synch
OUTPUTXBAR45OOutput 4 of the output XBAR
SPISTEB6I/OSPI-B slave transmit enable
SD2_C27ISigma-Delta 2 channel 2 clock input
GPIO280, 4, 8, 1264–I/OGeneral-purpose input/output 28
SCIRXDA1ISCI-A receive data
EM1CS42OExternal memory interface 1 chip select 4
OUTPUTXBAR55OOutput 5 of the output XBAR
EQEP3A6IEnhanced QEP3 input A
SD2_D37ISigma-Delta 2 channel 3 data input
GPIO290, 4, 8, 1265–I/OGeneral-purpose input/output 29
SCITXDA1OSCI-A transmit data
EM1SDCKE2OExternal memory interface 1 SDRAM clock enable
OUTPUTXBAR65OOutput 6 of the output XBAR
EQEP3B6IEnhanced QEP3 input B
SD2_C37ISigma-Delta 2 channel 3 clock input
GPIO300, 4, 8, 1263–I/OGeneral-purpose input/output 30
CANRXA1ICAN-A receive
EM1CLK2OExternal memory interface 1 clock
OUTPUTXBAR75OOutput 7 of the output XBAR
EQEP3S6I/OEnhanced QEP3 strobe
SD2_D47ISigma-Delta 2 channel 4 data input
GPIO310, 4, 8, 1266–I/OGeneral-purpose input/output 31
CANTXA1OCAN-A transmit
EM1WE2OExternal memory interface 1 write enable
OUTPUTXBAR85OOutput 8 of the output XBAR
EQEP3I6I/OEnhanced QEP3 index
SD2_C47ISigma-Delta 2 channel 4 clock input
GPIO320, 4, 8, 1267–I/OGeneral-purpose input/output 32
SDAA1I/ODI2C-A data open-drain bidirectional port
EM1CS02OExternal memory interface 1 chip select 0
GPIO330, 4, 8, 1269–I/OGeneral-purpose input/output 33
SCLA1I/ODI2C-A clock open-drain bidirectional port
EM1RNW2OExternal memory interface 1 read not write
GPIO340, 4, 8, 1270–I/OGeneral-purpose input/output 34
OUTPUTXBAR11OOutput 1 of the output XBAR
EM1CS22OExternal memory interface 1 chip select 2
SDAB6I/ODI2C-B data open-drain bidirectional port
GPIO350, 4, 8, 1271–I/OGeneral-purpose input/output 35
SCIRXDA1ISCI-A receive data
EM1CS32OExternal memory interface 1 chip select 3
SCLB6I/ODI2C-B clock open-drain bidirectional port
GPIO360, 4, 8, 1283–I/OGeneral-purpose input/output 36
SCITXDA1OSCI-A transmit data
EM1WAIT2IExternal memory interface 1 Asynchronous SRAM WAIT
CANRXA6ICAN-A receive
GPIO370, 4, 8, 1284–I/OGeneral-purpose input/output 37
OUTPUTXBAR21OOutput 2 of the output XBAR
EM1OE2OExternal memory interface 1 output enable
CANTXA6OCAN-A transmit
GPIO380, 4, 8, 1285–I/OGeneral-purpose input/output 38
EM1A02OExternal memory interface 1 address line 0
SCITXDC5OSCI-C transmit data
CANTXB6OCAN-B transmit
GPIO390, 4, 8, 1286–I/OGeneral-purpose input/output 39
EM1A12OExternal memory interface 1 address line 1
SCIRXDC5ISCI-C receive data
CANRXB6ICAN-B receive
GPIO400, 4, 8, 1287–I/OGeneral-purpose input/output 40
EM1A22OExternal memory interface 1 address line 2
SDAB6I/ODI2C-B data open-drain bidirectional port
GPIO410, 4, 8, 128951I/OGeneral-purpose input/output 41. For applications using the Hibernate low-power mode, this pin serves as the GPIOHIBWAKE signal. For details, see the Low Power Modes section of the System Control chapter in the TMS320F2807x Real-Time Microcontrollers Technical Reference Manual.
EM1A32OExternal memory interface 1 address line 3
SCLB6I/ODI2C-B clock open-drain bidirectional port
GPIO420, 4, 8, 1213073I/OGeneral-purpose input/output 42
SDAA6I/ODI2C-A data open-drain bidirectional port
SCITXDA15OSCI-A transmit data
USB0DMAnalogI/OUSB PHY differential data
GPIO430, 4, 8, 1213174I/OGeneral-purpose input/output 43
SCLA6I/ODI2C-A clock open-drain bidirectional port
SCIRXDA15ISCI-A receive data
USB0DPAnalogI/OUSB PHY differential data
GPIO440, 4, 8, 12113–I/OGeneral-purpose input/output 44
EM1A42OExternal memory interface 1 address line 4
GPIO450, 4, 8, 12115–I/OGeneral-purpose input/output 45
EM1A52OExternal memory interface 1 address line 5
GPIO460, 4, 8, 12128–I/OGeneral-purpose input/output 46
EM1A62OExternal memory interface 1 address line 6
SCIRXDD6ISCI-D receive data
GPIO470, 4, 8, 12129–I/OGeneral-purpose input/output 47
EM1A72OExternal memory interface 1 address line 7
SCITXDD6OSCI-D transmit data
GPIO480, 4, 8, 1290–I/OGeneral-purpose input/output 48
OUTPUTXBAR31OOutput 3 of the output XBAR
EM1A82OExternal memory interface 1 address line 8
SCITXDA6OSCI-A transmit data
SD1_D17ISigma-Delta 1 channel 1 data input
GPIO490, 4, 8, 1293–I/OGeneral-purpose input/output 49
OUTPUTXBAR41OOutput 4 of the output XBAR
EM1A92OExternal memory interface 1 address line 9
SCIRXDA6ISCI-A receive data
SD1_C17ISigma-Delta 1 channel 1 clock input
GPIO500, 4, 8, 1294–I/OGeneral-purpose input/output 50
EQEP1A1IEnhanced QEP1 input A
EM1A102OExternal memory interface 1 address line 10
SPISIMOC6I/OSPI-C slave in, master out
SD1_D27ISigma-Delta 1 channel 2 data input
GPIO510, 4, 8, 1295–I/OGeneral-purpose input/output 51
EQEP1B1IEnhanced QEP1 input B
EM1A112OExternal memory interface 1 address line 11
SPISOMIC6I/OSPI-C slave out, master in
SD1_C27ISigma-Delta 1 channel 2 clock input
GPIO520, 4, 8, 1296–I/OGeneral-purpose input/output 52
EQEP1S1I/OEnhanced QEP1 strobe
EM1A122OExternal memory interface 1 address line 12
SPICLKC6I/OSPI-C clock
SD1_D37ISigma-Delta 1 channel 3 data input
GPIO530, 4, 8, 1297–I/OGeneral-purpose input/output 53
EQEP1I1I/OEnhanced QEP1 index
EM1D312I/OExternal memory interface 1 data line 31
SPISTEC6I/OSPI-C slave transmit enable
SD1_C37ISigma-Delta 1 channel 3 clock input
GPIO540, 4, 8, 1298–I/OGeneral-purpose input/output 54
SPISIMOA1I/OSPI-A slave in, master out
EM1D302I/OExternal memory interface 1 data line 30
EQEP2A5IEnhanced QEP2 input A
SCITXDB6OSCI-B transmit data
SD1_D47ISigma-Delta 1 channel 4 data input
GPIO550, 4, 8, 12100–I/OGeneral-purpose input/output 55
SPISOMIA1I/OSPI-A slave out, master in
EM1D292I/OExternal memory interface 1 data line 29
EQEP2B5IEnhanced QEP2 input B
SCIRXDB6ISCI-B receive data
SD1_C47ISigma-Delta 1 channel 4 clock input
GPIO560, 4, 8, 12101–I/OGeneral-purpose input/output 56
SPICLKA1I/OSPI-A clock
EM1D282I/OExternal memory interface 1 data line 28
EQEP2S5I/OEnhanced QEP2 strobe
SCITXDC6OSCI-C transmit data
SD2_D17ISigma-Delta 2 channel 1 data input
GPIO570, 4, 8, 12102–I/OGeneral-purpose input/output 57
SPISTEA1I/OSPI-A slave transmit enable
EM1D272I/OExternal memory interface 1 data line 27
EQEP2I5I/OEnhanced QEP2 index
SCIRXDC6ISCI-C receive data
SD2_C17ISigma-Delta 2 channel 1 clock input
GPIO580, 4, 8, 1210352I/OGeneral-purpose input/output 58
MCLKRA1I/OMcBSP-A receive clock
EM1D262I/OExternal memory interface 1 data line 26
OUTPUTXBAR15OOutput 1 of the output XBAR
SPICLKB6I/OSPI-B clock
SD2_D27ISigma-Delta 2 channel 2 data input
SPISIMOA15I/OSPI-A slave in, master out(2)
GPIO590, 4, 8, 1210453I/OGeneral-purpose input/output 59(3)
MFSRA1I/OMcBSP-A receive frame synch
EM1D252I/OExternal memory interface 1 data line 25
OUTPUTXBAR25OOutput 2 of the output XBAR
SPISTEB6I/OSPI-B slave transmit enable
SD2_C27ISigma-Delta 2 channel 2 clock input
SPISOMIA15I/OSPI-A slave out, master in(2)
GPIO600, 4, 8, 1210554I/OGeneral-purpose input/output 60
MCLKRB1I/OMcBSP-B receive clock
EM1D242I/OExternal memory interface 1 data line 24
OUTPUTXBAR35OOutput 3 of the output XBAR
SPISIMOB6I/OSPI-B slave in, master out
SD2_D37ISigma-Delta 2 channel 3 data input
SPICLKA15I/OSPI-A clock(2)
GPIO610, 4, 8, 1210756I/OGeneral-purpose input/output 61(3)
MFSRB1I/OMcBSP-B receive frame synch
EM1D232I/OExternal memory interface 1 data line 23
OUTPUTXBAR45OOutput 4 of the output XBAR
SPISOMIB6I/OSPI-B slave out, master in
SD2_C37ISigma-Delta 2 channel 3 clock input
SPISTEA15I/OSPI-A slave transmit enable(2)
GPIO620, 4, 8, 1210857I/OGeneral-purpose input/output 62
SCIRXDC1ISCI-C receive data
EM1D222I/OExternal memory interface 1 data line 22
EQEP3A5IEnhanced QEP3 input A
CANRXA6ICAN-A receive
SD2_D47ISigma-Delta 2 channel 4 data input
GPIO630, 4, 8, 1210958I/OGeneral-purpose input/output 63
SCITXDC1OSCI-C transmit data
EM1D212I/OExternal memory interface 1 data line 21
EQEP3B5IEnhanced QEP3 input B
CANTXA6OCAN-A transmit
SD2_C47ISigma-Delta 2 channel 4 clock input
SPISIMOB15I/OSPI-B slave in, master out(2)
GPIO640, 4, 8, 1211059I/OGeneral-purpose input/output 64(3)
EM1D202I/OExternal memory interface 1 data line 20
EQEP3S5I/OEnhanced QEP3 strobe
SCIRXDA6ISCI-A receive data
SPISOMIB15I/OSPI-B slave out, master in(2)
GPIO650, 4, 8, 1211160I/OGeneral-purpose input/output 65
EM1D192I/OExternal memory interface 1 data line 19
EQEP3I5I/OEnhanced QEP3 index
SCITXDA6OSCI-A transmit data
SPICLKB15I/OSPI-B clock(2)
GPIO660, 4, 8, 1211261I/OGeneral-purpose input/output 66(3)
EM1D182I/OExternal memory interface 1 data line 18
SDAB6I/ODI2C-B data open-drain bidirectional port
SPISTEB15I/OSPI-B slave transmit enable(2)
GPIO670, 4, 8, 12132–I/OGeneral-purpose input/output 67
EM1D172I/OExternal memory interface 1 data line 17
GPIO680, 4, 8, 12133–I/OGeneral-purpose input/output 68
EM1D162I/OExternal memory interface 1 data line 16
GPIO690, 4, 8, 1213475I/OGeneral-purpose input/output 69
EM1D152I/OExternal memory interface 1 data line 15
SCLB6I/ODI2C-B clock open-drain bidirectional port
SPISIMOC15I/OSPI-C slave in, master out(2)
GPIO700, 4, 8, 1213576I/OGeneral-purpose input/output 70(3)
EM1D142I/OExternal memory interface 1 data line 14
CANRXA5ICAN-A receive
SCITXDB6OSCI-B transmit data
SPISOMIC15I/OSPI-C slave out, master in(2)
GPIO710, 4, 8, 1213677I/OGeneral-purpose input/output 71
EM1D132I/OExternal memory interface 1 data line 13
CANTXA5OCAN-A transmit
SCIRXDB6ISCI-B receive data
SPICLKC15I/OSPI-C clock(2)
GPIO720, 4, 8, 1213980I/OGeneral-purpose input/output 72.(3) This is the factory default boot mode select pin 1.
EM1D122I/OExternal memory interface 1 data line 12
CANTXB5OCAN-B transmit
SCITXDC6OSCI-C transmit data
SPISTEC15I/OSPI-C slave transmit enable(2)
GPIO730, 4, 8, 1214081I/OGeneral-purpose input/output 73
EM1D112I/OExternal memory interface 1 data line 11
XCLKOUT3O/ZExternal clock output. This pin outputs a divided-down version of a chosen clock signal from within the device. The clock signal is chosen using the CLKSRCCTL3.XCLKOUTSEL bit field while the divide ratio is chosen using the XCLKOUTDIVSEL.XCLKOUTDIV bit field.
CANRXB5ICAN-B receive
SCIRXDC6ISCI-C receive
GPIO740, 4, 8, 12141–I/OGeneral-purpose input/output 74
EM1D102I/OExternal memory interface 1 data line 10
GPIO750, 4, 8, 12142–I/OGeneral-purpose input/output 75
EM1D92I/OExternal memory interface 1 data line 9
GPIO760, 4, 8, 12143–I/OGeneral-purpose input/output 76
EM1D82I/OExternal memory interface 1 data line 8
SCITXDD6OSCI-D transmit data
GPIO770, 4, 8, 12144–I/OGeneral-purpose input/output 77
EM1D72I/OExternal memory interface 1 data line 7
SCIRXDD6ISCI-D receive data
GPIO780, 4, 8, 1214582I/OGeneral-purpose input/output 78
EM1D62I/OExternal memory interface 1 data line 6
EQEP2A6IEnhanced QEP2 input A
GPIO790, 4, 8, 12146–I/OGeneral-purpose input/output 79
EM1D52I/OExternal memory interface 1 data line 5
EQEP2B6IEnhanced QEP2 input B
GPIO800, 4, 8, 12148–I/OGeneral-purpose input/output 80
EM1D42I/OExternal memory interface 1 data line 4
EQEP2S6I/OEnhanced QEP2 strobe
GPIO810, 4, 8, 12149–I/OGeneral-purpose input/output 81
EM1D32I/OExternal memory interface 1 data line 3
EQEP2I6I/OEnhanced QEP2 index
GPIO820, 4, 8, 12150–I/OGeneral-purpose input/output 82
EM1D22I/OExternal memory interface 1 data line 2
GPIO830, 4, 8, 12151–I/OGeneral-purpose input/output 83
EM1D12I/OExternal memory interface 1 data line 1
GPIO840, 4, 8, 1215485I/OGeneral-purpose input/output 84. This is the factory default boot mode select pin 0.
SCITXDA5OSCI-A transmit data
MDXB6OMcBSP-B transmit serial data
MDXA15OMcBSP-A transmit serial data
GPIO850, 4, 8, 1215586I/OGeneral-purpose input/output 85
EM1D02I/OExternal memory interface 1 data line 0
SCIRXDA5ISCI-A receive data
MDRB6IMcBSP-B receive serial data
MDRA15IMcBSP-A receive serial data
GPIO860, 4, 8, 1215687I/OGeneral-purpose input/output 86
EM1A132OExternal memory interface 1 address line 13
EM1CAS3OExternal memory interface 1 column address strobe
SCITXDB5OSCI-B transmit data
MCLKXB6I/OMcBSP-B transmit clock
MCLKXA15I/OMcBSP-A transmit clock
GPIO870, 4, 8, 1215788I/OGeneral-purpose input/output 87
EM1A142OExternal memory interface 1 address line 14
EM1RAS3OExternal memory interface 1 row address strobe
SCIRXDB5ISCI-B receive data
MFSXB6I/OMcBSP-B transmit frame synch
MFSXA15I/OMcBSP-A transmit frame synch
GPIO880, 4, 8, 12170–I/OGeneral-purpose input/output 88
EM1A152OExternal memory interface 1 address line 15
EM1DQM03OExternal memory interface 1 Input/output mask for byte 0
GPIO890, 4, 8, 1217196I/OGeneral-purpose input/output 89
EM1A162OExternal memory interface 1 address line 16
EM1DQM13OExternal memory interface 1 Input/output mask for byte 1
SCITXDC6OSCI-C transmit data
GPIO900, 4, 8, 1217297I/OGeneral-purpose input/output 90
EM1A172OExternal memory interface 1 address line 17
EM1DQM23OExternal memory interface 1 Input/output mask for byte 2
SCIRXDC6ISCI-C receive data
GPIO910, 4, 8, 1217398I/OGeneral-purpose input/output 91
EM1A182OExternal memory interface 1 address line 18
EM1DQM33OExternal memory interface 1 Input/output mask for byte 3
SDAA6I/ODI2C-A data open-drain bidirectional port
GPIO920, 4, 8, 1217499I/OGeneral-purpose input/output 92
EM1A192OExternal memory interface 1 address line 19
EM1BA13OExternal memory interface 1 bank address 1
SCLA6I/ODI2C-A clock open-drain bidirectional port
GPIO930, 4, 8, 12175–I/OGeneral-purpose input/output 93
EM1BA03OExternal memory interface 1 bank address 0
SCITXDD6OSCI-D transmit data
GPIO940, 4, 8, 12176–I/OGeneral-purpose input/output 94
SCIRXDD6ISCI-D receive data
GPIO990, 4, 8, 121714I/OGeneral-purpose input/output 99
EQEP1I5I/OEnhanced QEP1 index
GPIO133/AUXCLKIN0, 4, 8, 12118–I/OGeneral-purpose input/output 133. The AUXCLKIN function of this GPIO pin could be used to provide a single-ended 3.3-V level clock signal to the Auxiliary Phase-Locked Loop (AUXPLL), whose output is used for the USB module. The AUXCLKIN clock may also be used for the CAN module.
SD2_C27ISigma-Delta 2 channel 2 clock input
RESET
XRS12469I/ODDevice Reset (in) and Watchdog Reset (out). The devices have a built-in power-on reset (POR) circuit. During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset or NMI watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is placed between XRS and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. The output buffer of this pin is an open drain with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device.
CLOCKS
X112368IOn-chip crystal-oscillator input. To use this oscillator, a quartz crystal must be connected across X1 and X2. If this pin is not used, it must be tied to GND.
This pin can also be used to feed a single-ended 3.3-V level clock. In this case, X2 is a No Connect (NC).
X212166OOn-chip crystal-oscillator output. A quartz crystal may be connected across X1 and X2. If X2 is not used, it must be left unconnected.
JTAG
TCK8150IJTAG test clock with internal pullup (see Section 6.6)
TDI7746IJTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.
TDO7847O/ZJTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK.(3)
TMS8049IJTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK.
TRST7948IJTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST must be maintained low at all times during normal device operation, so an external pulldown resistor is required on this pin for protection against noise spikes. The value of this resistor should be as small as possible, so long as the JTAG debug probe is still able to drive the TRST pin high. A resistor between 2.2-kΩ and 10-kΩ generally offers adequate protection. Since the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debug probe and the application. This pin has an internal 50-ns (nominal) glitch filter.
INTERNAL VOLTAGE REGULATOR CONTROL
VREGENZ11964IInternal voltage regulator enable with internal pulldown. To enable the 1.2-V VREG, tie directly to VSS. To disable and use an external supply for the 1.2-V rail, tie directly to VDDIO.
ANALOG, DIGITAL, AND I/O POWER
VDD16161.2-V digital logic power pins. There are two options for placing the decoupling capacitors.
  • Option 1 - Even Distribution: Distribute decoupling capacitance evenly across each VDD pin with a minimum total capacitance of approximately:
    • 12uF to 26 uF for internal VREG
    • 20uF for externally supplied VDD
    If the internal VREG is used, it is not required to have an external net connecting all VDD pins.
  • Option 2 - Bulk Capacitance: Place a 1uF capacitor near each VDD pin and place the remainder of the minimum total:
    • 12uF to 26uF for internal VREG
    • 20uF for externally supplied VDD
    capacitance as bulk capacitance on the VDD net
If the internal VREG is used, this option requires a common VDD net so that the bulk capacitance is available to all pins. The exact value of the decoupling capacitance for the external supply option should be determined by your system voltage regulation solution.
2139
6145
7663
11771
12678
13784
15389
15895
169–
VDD3VFL72413.3-V Flash power pin. Place a minimum 0.1-µF decoupling capacitor on each pin.
VDDA35183.3-V analog power pins. Place a minimum 2.2-µF decoupling capacitor to VSSA on each pin.
3638
54–
VDDIO323.3-V digital I/O power pins. Place a minimum 0.1-µF decoupling capacitor on each pin. The exact value of the decoupling capacitance should be determined by your system voltage regulation solution.
1110
1515
2040
2644
6255
6862
7572
8279
8883
9190
9994
106–
114–
116–
127–
138–
147–
152–
159–
168–
VDDOSC12065Power pins for the 3.3-V on-chip crystal oscillator (X1 and X2) and the two zero-pin internal oscillators (INTOSC). Place a 0.1-μF (minimum) decoupling capacitor on each pin.
12570
VSSPWR
PAD
(177)		PWR
PAD
(101)		Device ground. For Quad Flatpacks (QFPs), the PowerPAD on the bottom of the package must be soldered to the ground plane of the PCB.
VSSOSC12267Crystal oscillator (X1 and X2) ground pin. When using an external crystal, do not connect this pin to the board ground. Instead, connect it to the ground reference of the external crystal oscillator circuit.
If an external crystal is not used, this pin may be connected to the board ground.
VSSA3217Analog ground.
On the PZP package, pin 17 is double-bonded to VSSA and VREFLOA. This pin must be connect to VSSA.
3435
5236
SPECIAL FUNCTIONS
ERRORSTS92–OError status output. This pin has an internal pulldown.
TEST PINS
FLT17342I/OFlash test pin 1. Reserved for TI. Must be left unconnected.
FLT27443I/OFlash test pin 2. Reserved for TI. Must be left unconnected.
(1) I = Input, O = Output, OD = Open Drain, Z = High Impedance
(2) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1 in SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR).
(3) This pin has output impedance that can be as low as 22 Ω. This output could have fast edges and ringing depending on the system PCB characteristics. If this is a concern, the user should take precautions such as adding a 39Ω (10% tolerance) series termination resistor or implement some other termination scheme. It is also recommended that a system-level signal integrity analysis be performed with the provided IBIS models. The termination is not required if this pin is used for input function.