SPRS439Q June   2007  – August 2022 TMS320F28232 , TMS320F28232-Q1 , TMS320F28234 , TMS320F28234-Q1 , TMS320F28235 , TMS320F28235-Q1 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335 , TMS320F28335-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Automotive
    3. 7.3  ESD Ratings – Commercial
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 TMS320F28335/F28235 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
      2. 7.5.2 TMS320F28334/F28234 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
      3. 7.5.3 Reducing Current Consumption
      4. 7.5.4 Current Consumption Graphs
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics
      1. 7.7.1 PGF Package
      2. 7.7.2 PTP Package
      3. 7.7.3 ZHH Package
      4. 7.7.4 ZAY Package
      5. 7.7.5 ZJZ Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  Timing and Switching Characteristics
      1. 7.9.1 Timing Parameter Symbology
        1. 7.9.1.1 General Notes on Timing Parameters
        2. 7.9.1.2 Test Load Circuit
        3. 7.9.1.3 Device Clock Table
          1. 7.9.1.3.1 Clocking and Nomenclature (150-MHz Devices)
          2. 7.9.1.3.2 Clocking and Nomenclature (100-MHz Devices)
      2. 7.9.2 Power Sequencing
        1. 7.9.2.1 Power Management and Supervisory Circuit Solutions
        2. 7.9.2.2 Reset (XRS) Timing Requirements
      3. 7.9.3 Clock Requirements and Characteristics
        1. 7.9.3.1 Input Clock Frequency
        2. 7.9.3.2 XCLKIN Timing Requirements – PLL Enabled
        3. 7.9.3.3 XCLKIN Timing Requirements – PLL Disabled
        4. 7.9.3.4 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        5. 7.9.3.5 Timing Diagram
      4. 7.9.4 Peripherals
        1. 7.9.4.1 General-Purpose Input/Output (GPIO)
          1. 7.9.4.1.1 GPIO - Output Timing
            1. 7.9.4.1.1.1 General-Purpose Output Switching Characteristics
          2. 7.9.4.1.2 GPIO - Input Timing
            1. 7.9.4.1.2.1 General-Purpose Input Timing Requirements
          3. 7.9.4.1.3 Sampling Window Width for Input Signals
          4. 7.9.4.1.4 Low-Power Mode Wakeup Timing
            1. 7.9.4.1.4.1 IDLE Mode Timing Requirements
            2. 7.9.4.1.4.2 IDLE Mode Switching Characteristics
            3. 7.9.4.1.4.3 IDLE Mode Timing Diagram
            4. 7.9.4.1.4.4 STANDBY Mode Timing Requirements
            5. 7.9.4.1.4.5 STANDBY Mode Switching Characteristics
            6. 7.9.4.1.4.6 STANDBY Mode Timing Diagram
            7. 7.9.4.1.4.7 HALT Mode Timing Requirements
            8. 7.9.4.1.4.8 HALT Mode Switching Characteristics
            9. 7.9.4.1.4.9 HALT Mode Timing Diagram
        2. 7.9.4.2 Enhanced Control Peripherals
          1. 7.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. 7.9.4.2.1.1 ePWM Timing Requirements
            2. 7.9.4.2.1.2 ePWM Switching Characteristics
          2. 7.9.4.2.2 Trip-Zone Input Timing
            1. 7.9.4.2.2.1 Trip-Zone Input Timing Requirements
          3. 7.9.4.2.3 High-Resolution PWM Timing
            1. 7.9.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
          4. 7.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. 7.9.4.2.4.1 Enhanced Capture (eCAP) Timing Requirements
            2. 7.9.4.2.4.2 eCAP Switching Characteristics
          5. 7.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. 7.9.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
            2. 7.9.4.2.5.2 eQEP Switching Characteristics
          6. 7.9.4.2.6 ADC Start-of-Conversion Timing
            1. 7.9.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
            2. 7.9.4.2.6.2 ADCSOCAO or ADCSOCBO Timing
        3. 7.9.4.3 External Interrupt Timing
          1. 7.9.4.3.1 External Interrupt Timing Requirements
          2. 7.9.4.3.2 External Interrupt Switching Characteristics
          3. 7.9.4.3.3 External Interrupt Timing Diagram
        4. 7.9.4.4 I2C Electrical Specification and Timing
          1. 7.9.4.4.1 I2C Timing
        5. 7.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 7.9.4.5.1 Master Mode Timing
            1. 7.9.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0)
            2. 7.9.4.5.1.2 SPI Master Mode External Timing (Clock Phase = 1)
          2. 7.9.4.5.2 Slave Mode Timing
            1. 7.9.4.5.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
            2. 7.9.4.5.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
        6. 7.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 7.9.4.6.1 McBSP Transmit and Receive Timing
            1. 7.9.4.6.1.1 McBSP Timing Requirements
            2. 7.9.4.6.1.2 McBSP Switching Characteristics
          2. 7.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. 7.9.4.6.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. 7.9.4.6.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. 7.9.4.6.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. 7.9.4.6.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. 7.9.4.6.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. 7.9.4.6.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. 7.9.4.6.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. 7.9.4.6.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      5. 7.9.5 JTAG Debug Probe Connection Without Signal Buffering for the MCU
      6. 7.9.6 External Interface (XINTF) Timing
        1. 7.9.6.1 USEREADY = 0
        2. 7.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 7.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 7.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 7.9.6.5 External Interface Read Timing
          1. 7.9.6.5.1 External Interface Read Timing Requirements
          2. 7.9.6.5.2 External Interface Read Switching Characteristics
        6. 7.9.6.6 External Interface Write Timing
          1. 7.9.6.6.1 External Interface Write Switching Characteristics
        7. 7.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. 7.9.6.7.1 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. 7.9.6.7.2 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. 7.9.6.7.3 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
          4. 7.9.6.7.4 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 7.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. 7.9.6.8.1 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. 7.9.6.8.2 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
          3. 7.9.6.8.3 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
        9. 7.9.6.9 XHOLD and XHOLDA Timing
          1. 7.9.6.9.1 XHOLD/ XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
          2. 7.9.6.9.2 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
      7. 7.9.7 Flash Timing
        1. 7.9.7.1 Flash Endurance for A and S Temperature Material
        2. 7.9.7.2 Flash Endurance for Q Temperature Material
        3. 7.9.7.3 Flash Parameters at 150-MHz SYSCLKOUT
        4. 7.9.7.4 Flash/OTP Access Timing
        5. 7.9.7.5 Flash Data Retention Duration
    10. 7.10 On-Chip Analog-to-Digital Converter
      1. 7.10.1 ADC Electrical Characteristics (over recommended operating conditions)
      2. 7.10.2 ADC Power-Up Control Bit Timing
        1. 7.10.2.1 ADC Power-Up Delays
        2. 7.10.2.2 Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
      3. 7.10.3 Definitions
      4. 7.10.4 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
        1. 7.10.4.1 Sequential Sampling Mode Timing
      5. 7.10.5 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
        1. 7.10.5.1 Simultaneous Sampling Mode Timing
      6. 7.10.6 Detailed Descriptions
    11. 7.11 Migrating Between F2833x Devices and F2823x Devices
  8. 8 Detailed Description
    1. 8.1 Brief Descriptions
      1. 8.1.1  C28x CPU
      2. 8.1.2  Memory Bus (Harvard Bus Architecture)
      3. 8.1.3  Peripheral Bus
      4. 8.1.4  Real-Time JTAG and Analysis
      5. 8.1.5  External Interface (XINTF)
      6. 8.1.6  Flash
      7. 8.1.7  M0, M1 SARAMs
      8. 8.1.8  L0, L1, L2, L3, L4, L5, L6, L7 SARAMs
      9. 8.1.9  Boot ROM
        1. 8.1.9.1 Peripheral Pins Used by the Bootloader
      10. 8.1.10 Security
      11. 8.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 8.1.12 External Interrupts (XINT1–XINT7, XNMI)
      13. 8.1.13 Oscillator and PLL
      14. 8.1.14 Watchdog
      15. 8.1.15 Peripheral Clocking
      16. 8.1.16 Low-Power Modes
      17. 8.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 8.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 8.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 8.1.20 Control Peripherals
      21. 8.1.21 Serial Port Peripherals
    2. 8.2 Peripherals
      1. 8.2.1  DMA Overview
      2. 8.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 8.2.3  Enhanced PWM Modules
      4. 8.2.4  High-Resolution PWM (HRPWM)
      5. 8.2.5  Enhanced CAP Modules
      6. 8.2.6  Enhanced QEP Modules
      7. 8.2.7  Analog-to-Digital Converter (ADC) Module
        1. 8.2.7.1 ADC Connections if the ADC Is Not Used
        2. 8.2.7.2 ADC Registers
        3. 8.2.7.3 ADC Calibration
      8. 8.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 8.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 8.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 8.2.11 Serial Peripheral Interface (SPI) Module (SPI-A)
      12. 8.2.12 Inter-Integrated Circuit (I2C)
      13. 8.2.13 GPIO MUX
      14. 8.2.14 External Interface (XINTF)
    3. 8.3 Memory Maps
    4. 8.4 Register Map
      1. 8.4.1 Device Emulation Registers
    5. 8.5 Interrupts
      1. 8.5.1 External Interrupts
    6. 8.6 System Control
      1. 8.6.1 OSC and PLL Block
        1. 8.6.1.1 External Reference Oscillator Clock Option
        2. 8.6.1.2 PLL-Based Clock Module
        3. 8.6.1.3 Loss of Input Clock
      2. 8.6.2 Watchdog Block
    7. 8.7 Low-Power Modes Block
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Redesign Details
    2. 11.2 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZJZ|176
  • ZAY|179
  • PGF|176
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.2 Signal Descriptions

Table 6-1 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 5-1 and Table 5-2 for details. Inputs are not 5-V tolerant. All pins capable of producing an XINTF output function have a drive strength of 8 mA (typical). This is true even if the pin is not configured for XINTF functionality. All other pins have a drive strength of 4-mA drive typical (unless otherwise indicated). All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on GPIO0–GPIO11 pins are not enabled at reset. The pullups on GPIO12–GPIO87 are enabled upon reset.

Table 6-1 Signal Descriptions
NAMEPIN NO.DESCRIPTION (1)
PGF,
PTP
PIN #		ZHH,
ZAY
BALL #		ZJZ
BALL #
JTAG
TRST78M10L11JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Because this is application-specific, TI recommends validating each target board for proper operation of the debugger and the application. (I, ↓)
TCK87N12M14JTAG test clock with internal pullup (I, ↑)
TMS79P10M12JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (I, ↑)
TDI76M9N12JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (I, ↑)
TDO77K9N13JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
EMU085L11N7Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the JTAG debug probe system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Because this is application-specific, TI recommends validating each target board for proper operation of the debugger and the application.
EMU186P12P8Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the JTAG debug probe system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Because this is application-specific, TI recommends validating each target board for proper operation of the debugger and the application.
FLASH
VDD3VFL84M11L93.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.
TEST181K10M7Test Pin. Reserved for TI. Must be left unconnected. (I/O)
TEST282P11L7Test Pin. Reserved for TI. Must be left unconnected. (I/O)
CLOCK
XCLKOUT138C11A10Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 18:16 (XTIMCLK) and bit 2 (CLKMODE) in the XINTCNF2 register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during a reset. (O/Z, 8 mA drive).
XCLKIN105J14G13External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case, the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.9-V oscillator is used to feed clock to X1 pin), this pin must be tied to GND. (I)
X1104J13G14Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.9-V/1.8-V core digital power supply. A 1.9-V/1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to GND. (I)
X2102J11H14Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and X2. If X2 is not used, it must be left unconnected. (O)
RESET
XRS80L10M13Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This pin is driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑)
The output buffer of this pin is an open drain with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device.
An external R-C circuit may be used on the pin, taking care that the timing requirements during power down are still met.
ADC SIGNALS
ADCINA735K4K1ADC Group A, Channel 7 input (I)
ADCINA636J5K2ADC Group A, Channel 6 input (I)
ADCINA537L1L1ADC Group A, Channel 5 input (I)
ADCINA438L2L2ADC Group A, Channel 4 input (I)
ADCINA339L3L3ADC Group A, Channel 3 input (I)
ADCINA240M1M1ADC Group A, Channel 2 input (I)
ADCINA141N1M2ADC Group A, Channel 1 input (I)
ADCINA042M3M3ADC Group A, Channel 0 input (I)
ADCINB753K5N6ADC Group B, Channel 7 input (I)
ADCINB652P4M6ADC Group B, Channel 6 input (I)
ADCINB551N4N5ADC Group B, Channel 5 input (I)
ADCINB450M4M5ADC Group B, Channel 4 input (I)
ADCINB349L4N4ADC Group B, Channel 3 input (I)
ADCINB248P3M4ADC Group B, Channel 2 input (I)
ADCINB147N3N3ADC Group B, Channel 1 input (I)
ADCINB046P2P3ADC Group B, Channel 0 input (I)
ADCLO43M2N2Low Reference (connect to analog ground) (I)
ADCRESEXT57M5P6ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.
ADCREFIN54L5P7External reference input (I)
ADCREFP56P5P5Internal Reference Positive Output. Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of 2.2 μF to analog ground. (O)
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is used in the system.
ADCREFM55N5P4Internal Reference Medium Output. Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of 2.2 μF to analog ground. (O)
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is used in the system.
CPU AND I/O POWER PINS
VDDA234K2K4ADC Analog Power Pin
VSSA233K3P1ADC Analog Ground Pin
VDDAIO45N2L5ADC Analog I/O Power Pin
VSSAIO44P1N1ADC Analog I/O Ground Pin
VDD1A1831J4K3ADC Analog Power Pin
VSS1AGND32K1L4ADC Analog Ground Pin
VDD2A1859M6L6ADC Analog Power Pin
VSS2AGND58K6P2ADC Analog Ground Pin
VDD4B1D4CPU and Logic Digital Power Pins
VDD15B5D5
VDD23B11D8
VDD29C8D9
VDD61D13E11
VDD101E9F4
VDD109F3F11
VDD117F13H4
VDD126H1J4
VDD139H12J11
VDD146J2K11
VDD154K14L8
VDD167N6
VDDIO9A4A13Digital I/O Power Pin
VDDIO71B10B1
VDDIO93E7D7
VDDIO107E12D11
VDDIO121F5E4
VDDIO143L8G4
VDDIO159H11G11
VDDIO170N14L10
VDDION14
VSS3A5A1Digital Ground Pins
VSS8A10A2
VSS14A11A14
VSS22B4B14
VSS30C3F6
VSS60C7F7
VSS70C9F8
VSS83D1F9
VSS92D6G6
VSS103D14G7
VSS106E8G8
VSS108E14G9
VSS118F4H6
VSS120F12H7
VSS125G1H8
VSS140H10H9
VSS144H13J6
VSS147J3J7
VSS155J10J8
VSS160J12J9
VSS166M12P13
VSS171N10P14
VSSN11
VSSP6
VSSP8
GPIO AND PERIPHERAL SIGNALS
GPIO0
EPWM1A
-
-		5C1D1General-purpose input/output 0 (I/O/Z)
Enhanced PWM1 Output A and HRPWM channel (O)
-
-
GPIO1
EPWM1B
ECAP6
MFSRB		6D3D2General-purpose input/output 1 (I/O/Z)
Enhanced PWM1 Output B (O)
Enhanced Capture 6 input/output (I/O)
McBSP-B receive frame synch (I/O)
GPIO2
EPWM2A
-
-		7D2D3General-purpose input/output 2 (I/O/Z)
Enhanced PWM2 Output A and HRPWM channel (O)
-
-
GPIO3
EPWM2B
ECAP5
MCLKRB		10E4E1General-purpose input/output 3 (I/O/Z)
Enhanced PWM2 Output B (O)
Enhanced Capture 5 input/output (I/O)
McBSP-B receive clock (I/O)
GPIO4
EPWM3A
-
-		11E2E2General-purpose input/output 4 (I/O/Z)
Enhanced PWM3 output A and HRPWM channel (O)
-
-
GPIO5
EPWM3B
MFSRA
ECAP1		12E3E3General-purpose input/output 5 (I/O/Z)
Enhanced PWM3 output B (O)
McBSP-A receive frame synch (I/O)
Enhanced Capture input/output 1 (I/O)
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO		13E1F1General-purpose input/output 6 (I/O/Z)
Enhanced PWM4 output A and HRPWM channel (O)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
GPIO7
EPWM4B
MCLKRA
ECAP2		16F2F2General-purpose input/output 7 (I/O/Z)
Enhanced PWM4 output B (O)
McBSP-A receive clock (I/O)
Enhanced capture input/output 2 (I/O)
GPIO8
EPWM5A
CANTXB
ADCSOCAO		17F1F3General-purpose Input/Output 8 (I/O/Z)
Enhanced PWM5 output A and HRPWM channel (O)
Enhanced CAN-B transmit (O)
ADC start-of-conversion A (O)
GPIO9
EPWM5B
SCITXDB
ECAP3		18G5G1General-purpose input/output 9 (I/O/Z)
Enhanced PWM5 output B (O)
SCI-B transmit data(O)
Enhanced capture input/output 3 (I/O)
GPIO10
EPWM6A
CANRXB
ADCSOCBO		19G4G2General-purpose input/output 10 (I/O/Z)
Enhanced PWM6 output A and HRPWM channel (O)
Enhanced CAN-B receive (I)
ADC start-of-conversion B (O)
GPIO11
EPWM6B
SCIRXDB
ECAP4		20G2G3General-purpose input/output 11 (I/O/Z)
Enhanced PWM6 output B (O)
SCI-B receive data (I)
Enhanced CAP Input/Output 4 (I/O)
GPIO12
TZ1
CANTXB
MDXB		21G3H1General-purpose input/output 12 (I/O/Z)
Trip Zone input 1 (I)
Enhanced CAN-B transmit (O)
McBSP-B transmit serial data (O)
GPIO13
TZ2
CANRXB
MDRB		24H3H2General-purpose input/output 13 (I/O/Z)
Trip Zone input 2 (I)
Enhanced CAN-B receive (I)
McBSP-B receive serial data (I)
GPIO1425H2H3General-purpose input/output 14 (I/O/Z)
TZ3/ XHOLDTrip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external interface (XINTF) to release the external bus and place all buses and strobes into a high-impedance state. To prevent this from happening when TZ3 signal goes active, disable this function by writing XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus will go into high impedance anytime TZ3 goes low. On the ePWM side, TZn signals are ignored by default, unless they are enabled by the code. The XINTF will release the bus when any current access is complete and there are no pending accesses on the XINTF. (I)
SCITXDBSCI-B Transmit (O)
MCLKXBMcBSP-B transmit clock (I/O)
GPIO1526H4J1General-purpose input/output 15 (I/O/Z)
TZ4/ XHOLDA Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on the direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4 function is chosen. If the pin is configured as an output, then XHOLDA function is chosen. XHOLDA is driven active (low) when the XINTF has granted an XHOLD request. All XINTF buses and strobe signals will be in a high-impedance state. XHOLDA is released when the XHOLD signal is released. External devices should only drive the external bus when XHOLDA is active (low). (I/O)
SCIRXDBSCI-B receive (I)
MFSXBMcBSP-B transmit frame synch (I/O)
GPIO16
SPISIMOA
CANTXB
TZ5		27H5J2General-purpose input/output 16 (I/O/Z)
SPI slave in, master out (I/O)
Enhanced CAN-B transmit (O)
Trip Zone input 5 (I)
GPIO17
SPISOMIA
CANRXB
TZ6		28J1J3General-purpose input/output 17 (I/O/Z)
SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (I)
Trip zone input 6 (I)
GPIO18
SPICLKA
SCITXDB
CANRXA		62L6N8General-purpose input/output 18 (I/O/Z)
SPI-A clock input/output (I/O)
SCI-B transmit (O)
Enhanced CAN-A receive (I)
GPIO19
SPISTEA
SCIRXDB
CANTXA		63K7M8General-purpose input/output 19 (I/O/Z)
SPI-A slave transmit enable input/output (I/O)
SCI-B receive (I)
Enhanced CAN-A transmit (O)
GPIO20
EQEP1A
MDXA
CANTXB		64L7P9General-purpose input/output 20 (I/O/Z)
Enhanced QEP1 input A (I)
McBSP-A transmit serial data (O)
Enhanced CAN-B transmit (O)
GPIO21
EQEP1B
MDRA
CANRXB		65P7N9General-purpose input/output 21 (I/O/Z)
Enhanced QEP1 input B (I)
McBSP-A receive serial data (I)
Enhanced CAN-B receive (I)
GPIO22
EQEP1S
MCLKXA
SCITXDB		66N7M9General-purpose input/output 22 (I/O/Z)
Enhanced QEP1 strobe (I/O)
McBSP-A transmit clock (I/O)
SCI-B transmit (O)
GPIO23
EQEP1I
MFSXA
SCIRXDB		67M7P10General-purpose input/output 23 (I/O/Z)
Enhanced QEP1 index (I/O)
McBSP-A transmit frame synch (I/O)
SCI-B receive (I)
GPIO24
ECAP1
EQEP2A
MDXB		68M8N10General-purpose input/output 24 (I/O/Z)
Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I)
McBSP-B transmit serial data (O)
GPIO25
ECAP2
EQEP2B
MDRB		69N8M10General-purpose input/output 25 (I/O/Z)
Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I)
McBSP-B receive serial data (I)
GPIO26
ECAP3
EQEP2I
MCLKXB		72K8P11General-purpose input/output 26 (I/O/Z)
Enhanced capture 3 (I/O)
Enhanced QEP2 index (I/O)
McBSP-B transmit clock (I/O)
GPIO27
ECAP4
EQEP2S
MFSXB		73L9N11General-purpose input/output 27 (I/O/Z)
Enhanced capture 4 (I/O)
Enhanced QEP2 strobe (I/O)
McBSP-B transmit frame synch (I/O)
GPIO28
SCIRXDA
XZCS6		141E10D10General-purpose input/output 28 (I/O/Z)
SCI receive data (I)
External Interface zone 6 chip select (O)
GPIO29
SCITXDA
XA19		2C2C1General-purpose input/output 29. (I/O/Z)
SCI transmit data (O)
External Interface Address Line 19 (O)
GPIO30
CANRXA
XA18		1B2C2General-purpose input/output 30 (I/O/Z)
Enhanced CAN-A receive (I)
External Interface Address Line 18 (O)
GPIO31
CANTXA
XA17		176A2B2General-purpose input/output 31 (I/O/Z)
Enhanced CAN-A transmit (O)
External Interface Address Line 17 (O)
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO		74N9M11General-purpose input/output 32 (I/O/Z)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion A (O)
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO		75P9P12General-purpose Input/Output 33 (I/O/Z)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion B (O)
GPIO34
ECAP1
XREADY		142D10A9General-purpose Input/Output 34 (I/O/Z)
Enhanced Capture input/output 1 (I/O)
External Interface Ready signal. Note that this pin is always (directly) connected to the XINTF. If an application uses this pin as a GPIO while also using the XINTF, it should configure the XINTF to ignore READY.
GPIO35
SCITXDA
XR/ W		148A9B9General-purpose Input/Output 35 (I/O/Z)
SCI-A transmit data (O)
External Interface read, not write strobe
GPIO36
SCIRXDA
XZCS0		145C10C9General-purpose Input/Output 36 (I/O/Z)
SCI receive data (I)
External Interface zone 0 chip select (O)
GPIO37
ECAP2
XZCS7		150D9B8General-purpose Input/Output 37 (I/O/Z)
Enhanced Capture input/output 2 (I/O)
External Interface zone 7 chip select (O)
GPIO38
-
XWE0		137D11C10General-purpose Input/Output 38 (I/O/Z)
-
External Interface Write Enable 0 (O)
GPIO39
-
XA16		175B3C3General-purpose Input/Output 39 (I/O/Z)
-
External Interface Address Line 16 (O)
GPIO40
-
XA0/ XWE1		151D8C8General-purpose Input/Output 40 (I/O/Z)
-
External Interface Address Line 0/External Interface Write Enable 1 (O)
GPIO41
-
XA1		152A8A7General-purpose Input/Output 41 (I/O/Z)
-
External Interface Address Line 1 (O)
GPIO42
-
XA2		153B8B7General-purpose Input/Output 42 (I/O/Z)
-
External Interface Address Line 2 (O)
GPIO43
-
XA3		156B7C7General-purpose Input/Output 43 (I/O/Z)
-
External Interface Address Line 3 (O)
GPIO44
-
XA4		157A7A6General-purpose Input/Output 44 (I/O/Z)
-
External Interface Address Line 4 (O)
GPIO45
-
XA5		158D7B6General-purpose Input/Output 45 (I/O/Z)
-
External Interface Address Line 5 (O)
GPIO46
-
XA6		161B6C6General-purpose Input/Output 46 (I/O/Z)
-
External Interface Address Line 6 (O)
GPIO47
-
XA7		162A6D6General-purpose Input/Output 47 (I/O/Z)
-
External Interface Address Line 7 (O)
GPIO48
ECAP5
XD31		88P13L14General-purpose Input/Output 48 (I/O/Z)
Enhanced Capture input/output 5 (I/O)
External Interface Data Line 31 (I/O/Z)
GPIO49
ECAP6
XD30		89N13L13General-purpose Input/Output 49 (I/O/Z)
Enhanced Capture input/output 6 (I/O)
External Interface Data Line 30 (I/O/Z)
GPIO50
EQEP1A
XD29		90P14L12General-purpose Input/Output 50 (I/O/Z)
Enhanced QEP1 input A (I)
External Interface Data Line 29 (I/O/Z)
GPIO51
EQEP1B
XD28		91M13K14General-purpose Input/Output 51 (I/O/Z)
Enhanced QEP1 input B (I)
External Interface Data Line 28 (I/O/Z)
GPIO52
EQEP1S
XD27		94M14K13General-purpose Input/Output 52 (I/O/Z)
Enhanced QEP1 Strobe (I/O)
External Interface Data Line 27 (I/O/Z)
GPIO53
EQEP1I
XD26		95L12K12General-purpose Input/Output 53 (I/O/Z)
Enhanced QEP1 lndex (I/O)
External Interface Data Line 26 (I/O/Z)
GPIO54
SPISIMOA
XD25		96L13J14General-purpose Input/Output 54 (I/O/Z)
SPI-A slave in, master out (I/O)
External Interface Data Line 25 (I/O/Z)
GPIO55
SPISOMIA
XD24		97L14J13General-purpose Input/Output 55 (I/O/Z)
SPI-A slave out, master in (I/O)
External Interface Data Line 24 (I/O/Z)
GPIO56
SPICLKA
XD23		98K11J12General-purpose Input/Output 56 (I/O/Z)
SPI-A clock (I/O)
External Interface Data Line 23 (I/O/Z)
GPIO57
SPISTEA
XD22		99K13H13General-purpose Input/Output 57 (I/O/Z)
SPI-A slave transmit enable (I/O)
External Interface Data Line 22 (I/O/Z)
GPIO58
MCLKRA
XD21		100K12H12General-purpose Input/Output 58 (I/O/Z)
McBSP-A receive clock (I/O)
External Interface Data Line 21 (I/O/Z)
GPIO59
MFSRA
XD20		110H14H11General-purpose Input/Output 59 (I/O/Z)
McBSP-A receive frame synch (I/O)
External Interface Data Line 20 (I/O/Z)
GPIO60
MCLKRB
XD19		111G14G12General-purpose Input/Output 60 (I/O/Z)
McBSP-B receive clock (I/O)
External Interface Data Line 19 (I/O/Z)
GPIO61
MFSRB
XD18		112G12F14General-purpose Input/Output 61 (I/O/Z)
McBSP-B receive frame synch (I/O)
External Interface Data Line 18 (I/O/Z)
GPIO62
SCIRXDC
XD17		113G13F13General-purpose Input/Output 62 (I/O/Z)
SCI-C receive data (I)
External Interface Data Line 17 (I/O/Z)
GPIO63
SCITXDC
XD16		114G11F12General-purpose Input/Output 63 (I/O/Z)
SCI-C transmit data (O)
External Interface Data Line 16 (I/O/Z)
GPIO64
-
XD15		115G10E14General-purpose Input/Output 64 (I/O/Z)
-
External Interface Data Line 15 (I/O/Z)
GPIO65
-
XD14		116F14E13General-purpose Input/Output 65 (I/O/Z)
-
External Interface Data Line 14 (I/O/Z)
GPIO66
-
XD13		119F11E12General-purpose Input/Output 66 (I/O/Z)
-
External Interface Data Line 13 (I/O/Z)
GPIO67
-
XD12		122E13D14General-purpose Input/Output 67 (I/O/Z)
-
External Interface Data Line 12 (I/O/Z)
GPIO68
-
XD11		123E11D13General-purpose Input/Output 68 (I/O/Z)
-
External Interface Data Line 11 (I/O/Z)
GPIO69
-
XD10		124F10D12General-purpose Input/Output 69 (I/O/Z)
-
External Interface Data Line 10 (I/O/Z)
GPIO70
-
XD9		127D12C14General-purpose Input/Output 70 (I/O/Z)
-
External Interface Data Line 9 (I/O/Z)
GPIO71
-
XD8		128C14C13General-purpose Input/Output 71 (I/O/Z)
-
External Interface Data Line 8 (I/O/Z)
GPIO72
-
XD7		129B14B13General-purpose Input/Output 72 (I/O/Z)
-
External Interface Data Line 7 (I/O/Z)
GPIO73
-
XD6		130C12A12General-purpose Input/Output 73 (I/O/Z)
-
External Interface Data Line 6 (I/O/Z)
GPIO74
-
XD5		131C13B12General-purpose Input/Output 74 (I/O/Z)
-
External Interface Data Line 5 (I/O/Z)
GPIO75
-
XD4		132A14C12General-purpose Input/Output 75 (I/O/Z)
-
External Interface Data Line 4 (I/O/Z)
GPIO76
-
XD3		133B13A11General-purpose Input/Output 76 (I/O/Z)
-
External Interface Data Line 3 (I/O/Z)
GPIO77
-
XD2		134A13B11General-purpose Input/Output 77 (I/O/Z)
-
External Interface Data Line 2 (I/O/Z)
GPIO78
-
XD1		135B12C11General-purpose Input/Output 78 (I/O/Z)
-
External Interface Data Line 1 (I/O/Z)
GPIO79
-
XD0		136A12B10General-purpose Input/Output 79 (I/O/Z)
-
External Interface Data Line 0 (I/O/Z)
GPIO80
-
XA8		163C6A5General-purpose Input/Output 80 (I/O/Z)
-
External Interface Address Line 8 (O)
GPIO81
-
XA9		164E6B5General-purpose Input/Output 81 (I/O/Z)
-
External Interface Address Line 9 (O)
GPIO82
-
XA10		165C5C5General-purpose Input/Output 82 (I/O/Z)
-
External Interface Address Line 10 (O)
GPIO83
-
XA11		168D5A4General-purpose Input/Output 83 (I/O/Z)
-
External Interface Address Line 11 (O)
GPIO84
-
XA12		169E5B4General-purpose Input/Output 84 (I/O/Z)

External Interface Address Line 12 (O)
GPIO85
-
XA13		172C4C4General-purpose Input/Output 85 (I/O/Z)
-
External Interface Address Line 13 (O)
GPIO86
-
XA14		173D4A3General-purpose Input/Output 86 (I/O/Z)
-
External Interface Address Line 14 (O)
GPIO87
-
XA15		 174 A3 B3 General-purpose Input/Output 87 (I/O/Z)
-
External Interface Address Line 15 (O)
XRD149B9A8External Interface Read Enable
(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown