SPRS439Q June 2007 – August 2022 TMS320F28232 , TMS320F28232-Q1 , TMS320F28234 , TMS320F28234-Q1 , TMS320F28235 , TMS320F28235-Q1 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335 , TMS320F28335-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 7-2 shows the relationship between the parameters configured in the XTIMING register and the duration of the pulse in terms of XTIMCLK cycles.
DESCRIPTION | DURATION (ns)(1) (2) | ||
---|---|---|---|
X2TIMING = 0 | X2TIMING = 1 | ||
LR | Lead period, read access | XRDLEAD × tc(XTIM) | (XRDLEAD × 2) × tc(XTIM) |
AR | Active period, read access | (XRDACTIVE + WS + 1) × tc(XTIM) | (XRDACTIVE × 2 + WS + 1) × tc(XTIM) |
TR | Trail period, read access | XRDTRAIL × tc(XTIM) | (XRDTRAIL × 2) × tc(XTIM) |
LW | Lead period, write access | XWRLEAD × tc(XTIM) | (XWRLEAD × 2) × tc(XTIM) |
AW | Active period, write access | (XWRACTIVE + WS + 1) × tc(XTIM) | (XWRACTIVE × 2 + WS + 1) × tc(XTIM) |
TW | Trail period, write access | XWRTRAIL × tc(XTIM) | (XWRTRAIL × 2) × tc(XTIM) |
Minimum wait-state requirements must be met when configuring each zone’s XTIMING register. These requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal device hardware is included to detect illegal settings.