SPRS880P December   2013  – February 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Signal Descriptions
      1. 5.2.1 Signal Descriptions
    3. 5.3 Pins With Internal Pullup and Pulldown
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Input X-BAR
      3. 5.4.3 Output X-BAR and ePWM X-BAR
      4. 5.4.4 USB Pin Muxing
      5. 5.4.5 High-Speed SPI Pin Muxing
    5. 5.5 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 Device Current Consumption at 200-MHz SYSCLK
      2. 6.5.2 Current Consumption Graphs
      3. 6.5.3 Reducing Current Consumption
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics
      1. 6.7.1 ZWT Package
      2. 6.7.2 PTP Package
      3. 6.7.3 PZP Package
    8. 6.8  Thermal Design Considerations
    9. 6.9  System
      1. 6.9.1  Power Sequencing
        1. 6.9.1.1 Signal Pin Requirements
        2. 6.9.1.2 VDDIO, VDDA, VDD3VFL, and VDDOSC Requirements
        3. 6.9.1.3 VDD Requirements
        4. 6.9.1.4 Supply Ramp Rate
          1. 6.9.1.4.1 Supply Ramp Rate
        5. 6.9.1.5 Supply Supervision
      2. 6.9.2  Reset Timing
        1. 6.9.2.1 Reset Sources
        2. 6.9.2.2 Reset Electrical Data and Timing
          1. 6.9.2.2.1 Reset ( XRS) Timing Requirements
          2. 6.9.2.2.2 Reset ( XRS) Switching Characteristics
      3. 6.9.3  Clock Specifications
        1. 6.9.3.1 Clock Sources
        2. 6.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.9.3.2.1.1 Input Clock Frequency
            2. 6.9.3.2.1.2 X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
            3. 6.9.3.2.1.3 XTAL Oscillator Characteristics
            4. 6.9.3.2.1.4 X1 Timing Requirements
            5. 6.9.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.9.3.2.1.6 PLL Lock Times
          2. 6.9.3.2.2 Internal Clock Frequencies
            1. 6.9.3.2.2.1 Internal Clock Frequencies
          3. 6.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. 6.9.3.2.3.1 Output Clock Frequency
            2. 6.9.3.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        3. 6.9.3.3 Input Clocks and PLLs
        4. 6.9.3.4 XTAL Oscillator
          1. 6.9.3.4.1 Introduction
          2. 6.9.3.4.2 Overview
            1. 6.9.3.4.2.1 Electrical Oscillator
              1. 6.9.3.4.2.1.1 Modes of Operation
                1. 6.9.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.9.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.9.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.9.3.4.2.2 Quartz Crystal
          3. 6.9.3.4.3 Functional Operation
            1. 6.9.3.4.3.1 ESR – Effective Series Resistance
            2. 6.9.3.4.3.2 Rneg – Negative Resistance
            3. 6.9.3.4.3.3 Start-up Time
            4. 6.9.3.4.3.4 DL – Drive Level
          4. 6.9.3.4.4 How to Choose a Crystal
          5. 6.9.3.4.5 Testing
          6. 6.9.3.4.6 Common Problems and Debug Tips
          7. 6.9.3.4.7 Crystal Oscillator Specifications
            1. 6.9.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.9.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
        5. 6.9.3.5 Internal Oscillators
          1. 6.9.3.5.1 Internal Oscillator Electrical Characteristics
      4. 6.9.4  Flash Parameters
        1. 6.9.4.1 Flash Parameters
      5. 6.9.5  RAM Specifications
      6. 6.9.6  ROM Specifications
      7. 6.9.7  Emulation/JTAG
        1. 6.9.7.1 JTAG Electrical Data and Timing
          1. 6.9.7.1.1 JTAG Timing Requirements
          2. 6.9.7.1.2 JTAG Switching Characteristics
      8. 6.9.8  GPIO Electrical Data and Timing
        1. 6.9.8.1 GPIO - Output Timing
          1. 6.9.8.1.1 General-Purpose Output Switching Characteristics
        2. 6.9.8.2 GPIO - Input Timing
          1. 6.9.8.2.1 General-Purpose Input Timing Requirements
        3. 6.9.8.3 Sampling Window Width for Input Signals
      9. 6.9.9  Interrupts
        1. 6.9.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.9.9.1.1 External Interrupt Timing Requirements
          2. 6.9.9.1.2 External Interrupt Switching Characteristics
      10. 6.9.10 Low-Power Modes
        1. 6.9.10.1 Clock-Gating Low-Power Modes
        2. 6.9.10.2 Power-Gating Low-Power Modes
        3. 6.9.10.3 Low-Power Mode Wakeup Timing
          1. 6.9.10.3.1 IDLE Mode Timing Requirements
          2. 6.9.10.3.2 IDLE Mode Switching Characteristics
          3. 6.9.10.3.3 STANDBY Mode Timing Requirements
          4. 6.9.10.3.4 STANDBY Mode Switching Characteristics
          5. 6.9.10.3.5 HALT Mode Timing Requirements
          6. 6.9.10.3.6 HALT Mode Switching Characteristics
          7. 6.9.10.3.7 HIBERNATE Mode Timing Requirements
          8. 6.9.10.3.8 HIBERNATE Mode Switching Characteristics
      11. 6.9.11 External Memory Interface (EMIF)
        1. 6.9.11.1 Asynchronous Memory Support
        2. 6.9.11.2 Synchronous DRAM Support
        3. 6.9.11.3 EMIF Electrical Data and Timing
          1. 6.9.11.3.1 Asynchronous RAM
            1. 6.9.11.3.1.1 EMIF Asynchronous Memory Timing Requirements
            2. 6.9.11.3.1.2 EMIF Asynchronous Memory Switching Characteristics
          2. 6.9.11.3.2 Synchronous RAM
            1. 6.9.11.3.2.1 EMIF Synchronous Memory Timing Requirements
            2. 6.9.11.3.2.2 EMIF Synchronous Memory Switching Characteristics
    10. 6.10 Analog Peripherals
      1. 6.10.1 Analog-to-Digital Converter (ADC)
        1. 6.10.1.1 ADC Configurability
          1. 6.10.1.1.1 Signal Mode
        2. 6.10.1.2 ADC Electrical Data and Timing
          1. 6.10.1.2.1 ADC Operating Conditions (16-Bit Differential Mode)
          2. 6.10.1.2.2 ADC Characteristics (16-Bit Differential Mode)
          3. 6.10.1.2.3 ADC Operating Conditions (12-Bit Single-Ended Mode)
          4. 6.10.1.2.4 ADC Characteristics (12-Bit Single-Ended Mode)
          5. 6.10.1.2.5 ADCEXTSOC Timing Requirements
          6. 6.10.1.2.6 ADC Input Models
            1. 6.10.1.2.6.1 Differential Input Model Parameters
            2. 6.10.1.2.6.2 Single-Ended Input Model Parameters
          7. 6.10.1.2.7 ADC Timing Diagrams
            1. 6.10.1.2.7.1 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
            2. 6.10.1.2.7.2 ADC Timings in 16-Bit Mode
        3. 6.10.1.3 Temperature Sensor Electrical Data and Timing
          1. 6.10.1.3.1 Temperature Sensor Electrical Characteristics
      2. 6.10.2 Comparator Subsystem (CMPSS)
        1. 6.10.2.1 CMPSS Electrical Data and Timing
          1. 6.10.2.1.1 Comparator Electrical Characteristics
          2. 6.10.2.1.2 CMPSS DAC Static Electrical Characteristics
      3. 6.10.3 Buffered Digital-to-Analog Converter (DAC)
        1. 6.10.3.1 Buffered DAC Electrical Data and Timing
          1. 6.10.3.1.1 Buffered DAC Electrical Characteristics
        2. 6.10.3.2 CMPSS DAC Dynamic Error
    11. 6.11 Control Peripherals
      1. 6.11.1 Enhanced Capture (eCAP)
        1. 6.11.1.1 eCAP Electrical Data and Timing
          1. 6.11.1.1.1 eCAP Timing Requirement
          2. 6.11.1.1.2 eCAP Switching Characteristics
      2. 6.11.2 Enhanced Pulse Width Modulator (ePWM)
        1. 6.11.2.1 Control Peripherals Synchronization
        2. 6.11.2.2 ePWM Electrical Data and Timing
          1. 6.11.2.2.1 ePWM Timing Requirements
          2. 6.11.2.2.2 ePWM Switching Characteristics
          3. 6.11.2.2.3 Trip-Zone Input Timing
            1. 6.11.2.2.3.1 Trip-Zone Input Timing Requirements
        3. 6.11.2.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 6.11.2.3.1 External ADC Start-of-Conversion Switching Characteristics
      3. 6.11.3 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.11.3.1 eQEP Electrical Data and Timing
          1. 6.11.3.1.1 eQEP Timing Requirements
          2. 6.11.3.1.2 eQEP Switching Characteristics
      4. 6.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.11.4.1 HRPWM Electrical Data and Timing
          1. 6.11.4.1.1 High-Resolution PWM Timing Requirements
          2. 6.11.4.1.2 High-Resolution PWM Characteristics
      5. 6.11.5 Sigma-Delta Filter Module (SDFM)
        1. 6.11.5.1 SDFM Electrical Data and Timing (Using ASYNC)
          1. 6.11.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
        2. 6.11.5.2 SDFM Electrical Data and Timing (Using 3-Sample GPIO Input Qualification)
          1. 6.11.5.2.1 SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window) Option
    12. 6.12 Communications Peripherals
      1. 6.12.1 Controller Area Network (CAN)
      2. 6.12.2 Inter-Integrated Circuit (I2C)
        1. 6.12.2.1 I2C Electrical Data and Timing
          1. 6.12.2.1.1 I2C Timing Requirements
          2. 6.12.2.1.2 I2C Switching Characteristics
          3. 6.12.2.1.3 I2C Timing Diagram
      3. 6.12.3 Multichannel Buffered Serial Port (McBSP)
        1. 6.12.3.1 McBSP Electrical Data and Timing
          1. 6.12.3.1.1 McBSP Transmit and Receive Timing
            1. 6.12.3.1.1.1 McBSP Timing Requirements
            2. 6.12.3.1.1.2 McBSP Switching Characteristics
          2. 6.12.3.1.2 McBSP as SPI Master or Slave Timing
            1. 6.12.3.1.2.1 McBSP as SPI Master Timing Requirements
            2. 6.12.3.1.2.2 McBSP as SPI Master Switching Characteristics
            3. 6.12.3.1.2.3 McBSP as SPI Slave Timing Requirements
            4. 6.12.3.1.2.4 McBSP as SPI Slave Switching Characteristics
      4. 6.12.4 Serial Communications Interface (SCI)
      5. 6.12.5 Serial Peripheral Interface (SPI)
        1. 6.12.5.1 SPI Electrical Data and Timing
          1. 6.12.5.1.1 SPI Master Mode Timings
            1. 6.12.5.1.1.1 SPI Master Mode Timing Requirements
            2. 6.12.5.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            3. 6.12.5.1.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
          2. 6.12.5.1.2 SPI Slave Mode Timings
            1. 6.12.5.1.2.1 SPI Slave Mode Timing Requirements
            2. 6.12.5.1.2.2 SPI Slave Mode Switching Characteristics
      6. 6.12.6 Universal Serial Bus (USB) Controller
        1. 6.12.6.1 USB Electrical Data and Timing
          1. 6.12.6.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.12.6.1.2 USB Output Ports DP and DM Switching Characteristics
      7. 6.12.7 Universal Parallel Port (uPP) Interface
        1. 6.12.7.1 uPP Electrical Data and Timing
          1. 6.12.7.1.1 uPP Timing Requirements
          2. 6.12.7.1.2 uPP Switching Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 C28x Memory Map
      2. 7.3.2 Flash Memory Map
      3. 7.3.3 EMIF Chip Select Memory Map
      4. 7.3.4 Peripheral Registers Memory Map
      5. 7.3.5 Memory Types
        1. 7.3.5.1 Dedicated RAM (Mx and Dx RAM)
        2. 7.3.5.2 Local Shared RAM (LSx RAM)
        3. 7.3.5.3 Global Shared RAM (GSx RAM)
        4. 7.3.5.4 CPU Message RAM (CPU MSGRAM)
        5. 7.3.5.5 CLA Message RAM (CLA MSGRAM)
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit
      2. 7.6.2 Trigonometric Math Unit
      3. 7.6.3 Viterbi, Complex Math, and CRC Unit II (VCU-II)
    7. 7.7  Control Law Accelerator
    8. 7.8  Direct Memory Access
    9. 7.9  Interprocessor Communication Module
    10. 7.10 Boot ROM and Peripheral Booting
      1. 7.10.1 EMU Boot or Emulation Boot
      2. 7.10.2 WAIT Boot Mode
      3. 7.10.3 Get Mode
      4. 7.10.4 Peripheral Pins Used by Bootloaders
    11. 7.11 Dual Code Security Module
    12. 7.12 Timers
    13. 7.13 Nonmaskable Interrupt With Watchdog Timer (NMIWD)
    14. 7.14 Watchdog
    15. 7.15 Configurable Logic Block (CLB)
    16. 7.16 Functional Safety
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 Servo Drive Control Module
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Servo Drive Control Module Resources
        2. 8.3.1.2 Solar Micro Inverter
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 Solar Micro Inverter Resources
        3. 8.3.1.3 On-Board Charger (OBC)
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 OBC Resources
        4. 8.3.1.4 EV Charging Station Power Module
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 EV Charging Station Power Module Resources
        5. 8.3.1.5 High-Voltage Traction Inverter
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 High-Voltage Traction Inverter Resources
  10. 9 Device and Documentation Support
    1. 9.1 Device and Development Support Tool Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZP|100
  • ZWT|337
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4 Peripheral Registers Memory Map

The peripheral registers memory map can be found in Table 7-5. The peripheral registers can be assigned to either the CPU1 or CPU2 subsystems except where noted in Table 7-5. Registers in the peripheral frames share a secondary master (CLA or DMA) selection with all other registers within the same peripheral frame. See the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual for details on the CPU subsystem and secondary master selection.

Note: None of the device peripherals have program bus access.
Table 7-5 Peripheral Registers Memory Map
REGISTERSSTRUCTURE NAMESTART
ADDRESS		END
ADDRESS		PROTECTED(1)CLA
ACCESS		DMA
ACCESS
AdcaResultRegsADC_RESULT_REGS0x0000 0B000x0000 0B1FYesYes
AdcbResultRegsADC_RESULT_REGS0x0000 0B200x0000 0B3FYesYes
AdccResultRegsADC_RESULT_REGS0x0000 0B400x0000 0B5FYesYes
AdcdResultRegsADC_RESULT_REGS0x0000 0B600x0000 0B7FYesYes
CpuTimer0Regs(2)CPUTIMER_REGS0x0000 0C000x0000 0C07
CpuTimer1Regs(2)CPUTIMER_REGS0x0000 0C080x0000 0C0F
CpuTimer2Regs(2)CPUTIMER_REGS0x0000 0C100x0000 0C17
PieCtrlRegs(2)(5)PIE_CTRL_REGS0x0000 0CE00x0000 0CFF
Cla1SoftIntRegs(5)CLA_SOFTINT_REGS0x0000 0CE00x0000 0CFFYes – CLA only, no CPU access
DmaRegs(2)DMA_REGS0x0000 10000x0000 11FF
Cla1Regs(2)CLA_REGS0x0000 14000x0000 147F
Clb1LogicCfgRegs CLB_LOGIC_CONFIG_REGS 0x0000 3000 0x0000 30FF Yes Yes
Clb1LogicCtrlRegs CLB_LOGIC_CONTROL_REGS 0x0000 3100 0x0000 31FF Yes Yes
Clb1DataExchRegs CLB_DATA_EXCHANGE_REGS 0x0000 3200 0x0000 33FF Yes Yes
Clb2LogicCfgRegs CLB_LOGIC_CONFIG_REGS 0x0000 3400 0x0000 34FF Yes Yes
Clb2LogicCtrlRegs CLB_LOGIC_CONTROL_REGS 0x0000 3500 0x0000 35FF Yes Yes
Clb2DataExchRegs CLB_DATA_EXCHANGE_REGS 0x0000 3600 0x0000 37FF Yes Yes
Clb3LogicCfgRegs CLB_LOGIC_CONFIG_REGS 0x0000 3800 0x0000 38FF Yes Yes
Clb3LogicCtrlRegs CLB_LOGIC_CONTROL_REGS 0x0000 3900 0x0000 39FF Yes Yes
Clb3DataExchRegs CLB_DATA_EXCHANGE_REGS 0x0000 3A00 0x0000 3BFF Yes Yes
Clb4LogicCfgRegs CLB_LOGIC_CONFIG_REGS 0x0000 3C00 0x0000 3CFF Yes Yes
Clb4LogicCtrlRegs CLB_LOGIC_CONTROL_REGS 0x0000 3D00 0x0000 3DFF Yes Yes
Clb4DataExchRegs CLB_DATA_EXCHANGE_REGS 0x0000 3E00 0x0000 3FFF Yes Yes
Peripheral Frame 1
EPwm1RegsEPWM_REGS0x0000 40000x0000 40FFYesYesYes
EPwm2RegsEPWM_REGS0x0000 41000x0000 41FFYesYesYes
EPwm3RegsEPWM_REGS0x0000 42000x0000 42FFYesYesYes
EPwm4RegsEPWM_REGS0x0000 43000x0000 43FFYesYesYes
EPwm5RegsEPWM_REGS0x0000 44000x0000 44FFYesYesYes
EPwm6RegsEPWM_REGS0x0000 45000x0000 45FFYesYesYes
EPwm7RegsEPWM_REGS0x0000 46000x0000 46FFYesYesYes
EPwm8RegsEPWM_REGS0x0000 47000x0000 47FFYesYesYes
EPwm9RegsEPWM_REGS0x0000 48000x0000 48FFYesYesYes
EPwm10RegsEPWM_REGS0x0000 49000x0000 49FFYesYesYes
EPwm11RegsEPWM_REGS0x0000 4A000x0000 4AFFYesYesYes
EPwm12RegsEPWM_REGS0x0000 4B000x0000 4BFFYesYesYes
ECap1RegsECAP_REGS0x0000 50000x0000 501FYesYesYes
ECap2RegsECAP_REGS0x0000 50200x0000 503FYesYesYes
ECap3RegsECAP_REGS0x0000 50400x0000 505FYesYesYes
ECap4RegsECAP_REGS0x0000 50600x0000 507FYesYesYes
ECap5RegsECAP_REGS0x0000 50800x0000 509FYesYesYes
ECap6RegsECAP_REGS0x0000 50A00x0000 50BFYesYesYes
EQep1RegsEQEP_REGS0x0000 51000x0000 513FYesYesYes
EQep2RegsEQEP_REGS0x0000 51400x0000 517FYesYesYes
EQep3RegsEQEP_REGS0x0000 51800x0000 51BFYesYesYes
DacaRegsDAC_REGS0x0000 5C000x0000 5C0FYesYesYes
DacbRegsDAC_REGS0x0000 5C100x0000 5C1FYesYesYes
DaccRegsDAC_REGS0x0000 5C200x0000 5C2FYesYesYes
Cmpss1RegsCMPSS_REGS0x0000 5C800x0000 5C9FYesYesYes
Cmpss2RegsCMPSS_REGS0x0000 5CA00x0000 5CBFYesYesYes
Cmpss3RegsCMPSS_REGS0x0000 5CC00x0000 5CDFYesYesYes
Cmpss4RegsCMPSS_REGS0x0000 5CE00x0000 5CFFYesYesYes
Cmpss5RegsCMPSS_REGS0x0000 5D000x0000 5D1FYesYesYes
Cmpss6RegsCMPSS_REGS0x0000 5D200x0000 5D3FYesYesYes
Cmpss7RegsCMPSS_REGS0x0000 5D400x0000 5D5FYesYesYes
Cmpss8RegsCMPSS_REGS0x0000 5D600x0000 5D7FYesYesYes
Sdfm1RegsSDFM_REGS0x0000 5E000x0000 5E7FYesYesYes
Sdfm2RegsSDFM_REGS0x0000 5E800x0000 5EFFYesYesYes
Peripheral Frame 2
McbspaRegsMCBSP_REGS0x0000 60000x0000 603FYesYesYes
McbspbRegsMCBSP_REGS0x0000 60400x0000 607FYesYesYes
SpiaRegsSPI_REGS0x0000 61000x0000 610FYesYesYes
SpibRegsSPI_REGS0x0000 61100x0000 611FYesYesYes
SpicRegsSPI_REGS0x0000 61200x0000 612FYesYesYes
UppRegs(3)UPP_REGS0x0000 62000x0000 62FFYesYesYes
 
WdRegs(2)WD_REGS0x0000 70000x0000 703FYes
NmiIntruptRegs(2)NMI_INTRUPT_REGS0x0000 70600x0000 706FYes
XintRegs(2)XINT_REGS0x0000 70700x0000 707FYes
SciaRegsSCI_REGS0x0000 72000x0000 720FYes
ScibRegsSCI_REGS0x0000 72100x0000 721FYes
ScicRegsSCI_REGS0x0000 72200x0000 722FYes
ScidRegsSCI_REGS0x0000 72300x0000 723FYes
I2caRegsI2C_REGS0x0000 73000x0000 733FYes
I2cbRegsI2C_REGS0x0000 73400x0000 737FYes
AdcaRegsADC_REGS0x0000 74000x0000 747FYesYes
AdcbRegsADC_REGS0x0000 74800x0000 74FFYesYes
AdccRegsADC_REGS0x0000 75000x0000 757FYesYes
AdcdRegsADC_REGS0x0000 75800x0000 75FFYesYes
InputXbarRegs(3)INPUT_XBAR_REGS0x0000 79000x0000 791FYes
XbarRegs(3)XBAR_REGS0x0000 79200x0000 793FYes
TrigRegs(3)TRIG_REGS0x0000 79400x0000 794FYes
DmaClaSrcSelRegs(2)DMA_CLA_SRC_SEL_REGS0x0000 79800x0000 798FYes
EPwmXbarRegs(3)EPWM_XBAR_REGS0x0000 7A000x0000 7A3FYes
OutputXbarRegs(3)OUTPUT_XBAR_REGS0x0000 7A800x0000 7ABFYes
GpioCtrlRegs(3)GPIO_CTRL_REGS0x0000 7C000x0000 7D7FYes
GpioDataRegs(2)GPIO_DATA_REGS0x0000 7F000x0000 7F2FYesYes
UsbaRegs(3)USB_REGS0x0004 00000x0004 0FFFYes
Emif1RegsEMIF_REGS0x0004 70000x0004 77FFYes
Emif2Regs(3)EMIF_REGS0x0004 78000x0004 7FFFYes
CanaRegsCAN_REGS0x0004 80000x0004 87FFYes
CanbRegsCAN_REGS0x0004 A0000x0004 A7FFYes
IpcRegs(2)IPC_REGS_CPU1
IPC_REGS_CPU2		0x0005 00000x0005 0023Yes
FlashPumpSemaphoreRegs(2)FLASH_PUMP_SEMAPHORE_REGS0x0005 00240x0005 0025Yes
DevCfgRegs(3)DEV_CFG_REGS0x0005 D0000x0005 D17FYes
AnalogSubsysRegs(3)ANALOG_SUBSYS_REGS0x0005 D1800x0005 D1FFYes
ClkCfgRegs(4)CLK_CFG_REGS0x0005 D2000x0005 D2FFYes
CpuSysRegs(2)CPU_SYS_REGS0x0005 D3000x0005 D3FFYes
RomPrefetchRegs(3)ROM_PREFETCH_REGS0x0005 E6080x0005 E60BYes
DcsmZ1Regs(2)DCSM_Z1_REGS0x0005 F0000x0005 F02FYes
DcsmZ2Regs(2)DCSM_Z2_REGS0x0005 F0400x0005 F05FYes
DcsmCommonRegs(2)DCSM_COMMON_REGS0x0005 F0700x0005 F07FYes
MemCfgRegs(2)MEM_CFG_REGS0x0005 F4000x0005 F47FYes
Emif1ConfigRegs(2)EMIF1_CONFIG_REGS0x0005 F4800x0005 F49FYes
Emif2ConfigRegs(3)EMIF2_CONFIG_REGS0x0005 F4A00x0005 F4BFYes
AccessProtectionRegs(2)ACCESS_PROTECTION_REGS0x0005 F4C00x0005 F4FFYes
MemoryErrorRegs(2)MEMORY_ERROR_REGS0x0005 F5000x0005 F53FYes
RomWaitStateRegs(3)ROM_WAIT_STATE_REGS0x0005 F5400x0005 F541Yes
Flash0CtrlRegs(2)FLASH_CTRL_REGS0x0005 F8000x0005 FAFFYes
Flash0EccRegs(2)FLASH_ECC_REGS0x0005 FB000x0005 FB3FYes
(1) The CPU (not applicable for CLA or DMA) contains a write followed by read protection mode to ensure that any read operation that follows a write operation within a protected address range is executed as written by delaying the read operation until the write is initiated.
(2) A unique copy of these registers exist on each CPU subsystem.
(3) These registers are available only on the CPU1 subsystem.
(4) These registers are mapped to either CPU1 or CPU2 based on a semaphore.
(5) The address overlap of PieCtrlRegs and Cla1SoftIntRegs is correct. Each CPU, C28x and CLA, only has access to one of the register sets.