SPRS880P December 2013 – February 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
For applications that do not need to use all functions of the device, Table 5-7 lists acceptable conditioning for any unused pins. When multiple options are listed in Table 5-7, any are acceptable. Pins not listed in Table 5-7 must be connected according to Section 5.2.1.
SIGNAL NAME | ACCEPTABLE PRACTICE |
---|---|
Analog | |
VREFHIx | Tie to VDDA |
VREFLOx | Tie to VSSA |
ADCINx |
|
Digital | |
GPIOx |
|
X1 | Tie to VSS |
X2 | No Connect |
TCK |
|
TDI |
|
TDO | No Connect |
TMS | No Connect |
TRST | Pulldown resistor (2.2 kΩ or smaller) |
VREGENZ | Tie to VDDIO. VREG is not supported. |
ERRORSTS | No Connect |
FLT1 | No Connect |
FLT2 | No Connect |
Power and Ground | |
VDD | All VDD pins must be connected per Section 5.2.1. |
VDDA | If a dedicated analog supply is not used, tie to VDDIO. |
VDDIO | All VDDIO pins must be connected per Section 5.2.1. |
VDD3VFL | Must be tied to VDDIO |
VDDOSC | Must be tied to VDDIO |
VSS | All VSS pins must be connected to board ground. |
VSSA | If a dedicated analog ground is not used, tie to VSS. |
VSSOSC | If an external crystal is not used, this pin may be connected to the board ground. |