SPRS881K August   2014  – February 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Signal Descriptions
      1. 5.2.1 Signal Descriptions
    3. 5.3 Pins With Internal Pullup and Pulldown
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Input X-BAR
      3. 5.4.3 Output X-BAR and ePWM X-BAR
      4. 5.4.4 USB Pin Muxing
      5. 5.4.5 High-Speed SPI Pin Muxing
    5. 5.5 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 Device Current Consumption at 200-MHz SYSCLK
      2. 6.5.2 Current Consumption Graphs
      3. 6.5.3 Reducing Current Consumption
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics
      1. 6.7.1 ZWT Package
      2. 6.7.2 PTP Package
      3. 6.7.3 PZP Package
    8. 6.8  Thermal Design Considerations
    9. 6.9  System
      1. 6.9.1  Power Sequencing
        1. 6.9.1.1 Signal Pin Requirements
        2. 6.9.1.2 VDDIO, VDDA, VDD3VFL, and VDDOSC Requirements
        3. 6.9.1.3 VDD Requirements
        4. 6.9.1.4 Supply Ramp Rate
          1. 6.9.1.4.1 Supply Ramp Rate
        5. 6.9.1.5 Supply Supervision
      2. 6.9.2  Reset Timing
        1. 6.9.2.1 Reset Sources
        2. 6.9.2.2 Reset Electrical Data and Timing
          1. 6.9.2.2.1 Reset ( XRS) Timing Requirements
          2. 6.9.2.2.2 Reset ( XRS) Switching Characteristics
      3. 6.9.3  Clock Specifications
        1. 6.9.3.1 Clock Sources
        2. 6.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.9.3.2.1.1 Input Clock Frequency
            2. 6.9.3.2.1.2 X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
            3. 6.9.3.2.1.3 XTAL Oscillator Characteristics
            4. 6.9.3.2.1.4 X1 Timing Requirements
            5. 6.9.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.9.3.2.1.6 PLL Lock Times
          2. 6.9.3.2.2 Internal Clock Frequencies
            1. 6.9.3.2.2.1 Internal Clock Frequencies
          3. 6.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. 6.9.3.2.3.1 Output Clock Frequency
            2. 6.9.3.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        3. 6.9.3.3 Input Clocks and PLLs
        4. 6.9.3.4 XTAL Oscillator
          1. 6.9.3.4.1 Introduction
          2. 6.9.3.4.2 Overview
            1. 6.9.3.4.2.1 Electrical Oscillator
              1. 6.9.3.4.2.1.1 Modes of Operation
                1. 6.9.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.9.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.9.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.9.3.4.2.2 Quartz Crystal
          3. 6.9.3.4.3 Functional Operation
            1. 6.9.3.4.3.1 ESR – Effective Series Resistance
            2. 6.9.3.4.3.2 Rneg – Negative Resistance
            3. 6.9.3.4.3.3 Start-up Time
            4. 6.9.3.4.3.4 DL – Drive Level
          4. 6.9.3.4.4 How to Choose a Crystal
          5. 6.9.3.4.5 Testing
          6. 6.9.3.4.6 Common Problems and Debug Tips
          7. 6.9.3.4.7 Crystal Oscillator Specifications
            1. 6.9.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.9.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
        5. 6.9.3.5 Internal Oscillators
          1. 6.9.3.5.1 Internal Oscillator Electrical Characteristics
      4. 6.9.4  Flash Parameters
        1. 6.9.4.1 Flash Parameters
      5. 6.9.5  RAM Specifications
      6. 6.9.6  ROM Specifications
      7. 6.9.7  Emulation/JTAG
        1. 6.9.7.1 JTAG Electrical Data and Timing
          1. 6.9.7.1.1 JTAG Timing Requirements
          2. 6.9.7.1.2 JTAG Switching Characteristics
      8. 6.9.8  GPIO Electrical Data and Timing
        1. 6.9.8.1 GPIO - Output Timing
          1. 6.9.8.1.1 General-Purpose Output Switching Characteristics
        2. 6.9.8.2 GPIO - Input Timing
          1. 6.9.8.2.1 General-Purpose Input Timing Requirements
        3. 6.9.8.3 Sampling Window Width for Input Signals
      9. 6.9.9  Interrupts
        1. 6.9.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.9.9.1.1 External Interrupt Timing Requirements
          2. 6.9.9.1.2 External Interrupt Switching Characteristics
      10. 6.9.10 Low-Power Modes
        1. 6.9.10.1 Clock-Gating Low-Power Modes
        2. 6.9.10.2 Power-Gating Low-Power Modes
        3. 6.9.10.3 Low-Power Mode Wakeup Timing
          1. 6.9.10.3.1 IDLE Mode Timing Requirements
          2. 6.9.10.3.2 IDLE Mode Switching Characteristics
          3. 6.9.10.3.3 STANDBY Mode Timing Requirements
          4. 6.9.10.3.4 STANDBY Mode Switching Characteristics
          5. 6.9.10.3.5 HALT Mode Timing Requirements
          6. 6.9.10.3.6 HALT Mode Switching Characteristics
          7. 6.9.10.3.7 HIBERNATE Mode Timing Requirements
          8. 6.9.10.3.8 HIBERNATE Mode Switching Characteristics
      11. 6.9.11 External Memory Interface (EMIF)
        1. 6.9.11.1 Asynchronous Memory Support
        2. 6.9.11.2 Synchronous DRAM Support
        3. 6.9.11.3 EMIF Electrical Data and Timing
          1. 6.9.11.3.1 Asynchronous RAM
            1. 6.9.11.3.1.1 EMIF Asynchronous Memory Timing Requirements
            2. 6.9.11.3.1.2 EMIF Asynchronous Memory Switching Characteristics
          2. 6.9.11.3.2 Synchronous RAM
            1. 6.9.11.3.2.1 EMIF Synchronous Memory Timing Requirements
            2. 6.9.11.3.2.2 EMIF Synchronous Memory Switching Characteristics
    10. 6.10 Analog Peripherals
      1. 6.10.1 Analog-to-Digital Converter (ADC)
        1. 6.10.1.1 ADC Configurability
          1. 6.10.1.1.1 Signal Mode
        2. 6.10.1.2 ADC Electrical Data and Timing
          1. 6.10.1.2.1 ADC Operating Conditions (16-Bit Differential Mode)
          2. 6.10.1.2.2 ADC Characteristics (16-Bit Differential Mode)
          3. 6.10.1.2.3 ADC Operating Conditions (12-Bit Single-Ended Mode)
          4. 6.10.1.2.4 ADC Characteristics (12-Bit Single-Ended Mode)
          5. 6.10.1.2.5 ADCEXTSOC Timing Requirements
          6. 6.10.1.2.6 ADC Input Models
            1. 6.10.1.2.6.1 Differential Input Model Parameters
            2. 6.10.1.2.6.2 Single-Ended Input Model Parameters
          7. 6.10.1.2.7 ADC Timing Diagrams
            1. 6.10.1.2.7.1 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
            2. 6.10.1.2.7.2 ADC Timings in 16-Bit Mode
        3. 6.10.1.3 Temperature Sensor Electrical Data and Timing
          1. 6.10.1.3.1 Temperature Sensor Electrical Characteristics
      2. 6.10.2 Comparator Subsystem (CMPSS)
        1. 6.10.2.1 CMPSS Electrical Data and Timing
          1. 6.10.2.1.1 Comparator Electrical Characteristics
          2. 6.10.2.1.2 CMPSS DAC Static Electrical Characteristics
      3. 6.10.3 Buffered Digital-to-Analog Converter (DAC)
        1. 6.10.3.1 Buffered DAC Electrical Data and Timing
          1. 6.10.3.1.1 Buffered DAC Electrical Characteristics
        2. 6.10.3.2 CMPSS DAC Dynamic Error
    11. 6.11 Control Peripherals
      1. 6.11.1 Enhanced Capture (eCAP)
        1. 6.11.1.1 eCAP Electrical Data and Timing
          1. 6.11.1.1.1 eCAP Timing Requirement
          2. 6.11.1.1.2 eCAP Switching Characteristics
      2. 6.11.2 Enhanced Pulse Width Modulator (ePWM)
        1. 6.11.2.1 Control Peripherals Synchronization
        2. 6.11.2.2 ePWM Electrical Data and Timing
          1. 6.11.2.2.1 ePWM Timing Requirements
          2. 6.11.2.2.2 ePWM Switching Characteristics
          3. 6.11.2.2.3 Trip-Zone Input Timing
            1. 6.11.2.2.3.1 Trip-Zone Input Timing Requirements
        3. 6.11.2.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 6.11.2.3.1 External ADC Start-of-Conversion Switching Characteristics
      3. 6.11.3 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.11.3.1 eQEP Electrical Data and Timing
          1. 6.11.3.1.1 eQEP Timing Requirements
          2. 6.11.3.1.2 eQEP Switching Characteristics
      4. 6.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.11.4.1 HRPWM Electrical Data and Timing
          1. 6.11.4.1.1 High-Resolution PWM Timing Requirements
          2. 6.11.4.1.2 High-Resolution PWM Characteristics
      5. 6.11.5 Sigma-Delta Filter Module (SDFM)
        1. 6.11.5.1 SDFM Electrical Data and Timing (Using ASYNC)
          1. 6.11.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
        2. 6.11.5.2 SDFM Electrical Data and Timing (Using 3-Sample GPIO Input Qualification)
          1. 6.11.5.2.1 SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window) Option
    12. 6.12 Communications Peripherals
      1. 6.12.1 Controller Area Network (CAN)
      2. 6.12.2 Inter-Integrated Circuit (I2C)
        1. 6.12.2.1 I2C Electrical Data and Timing
          1. 6.12.2.1.1 I2C Timing Requirements
          2. 6.12.2.1.2 I2C Switching Characteristics
          3. 6.12.2.1.3 I2C Timing Diagram
      3. 6.12.3 Multichannel Buffered Serial Port (McBSP)
        1. 6.12.3.1 McBSP Electrical Data and Timing
          1. 6.12.3.1.1 McBSP Transmit and Receive Timing
            1. 6.12.3.1.1.1 McBSP Timing Requirements
            2. 6.12.3.1.1.2 McBSP Switching Characteristics
          2. 6.12.3.1.2 McBSP as SPI Master or Slave Timing
            1. 6.12.3.1.2.1 McBSP as SPI Master Timing Requirements
            2. 6.12.3.1.2.2 McBSP as SPI Master Switching Characteristics
            3. 6.12.3.1.2.3 McBSP as SPI Slave Timing Requirements
            4. 6.12.3.1.2.4 McBSP as SPI Slave Switching Characteristics
      4. 6.12.4 Serial Communications Interface (SCI)
      5. 6.12.5 Serial Peripheral Interface (SPI)
        1. 6.12.5.1 SPI Electrical Data and Timing
          1. 6.12.5.1.1 SPI Master Mode Timings
            1. 6.12.5.1.1.1 SPI Master Mode Timing Requirements
            2. 6.12.5.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            3. 6.12.5.1.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
          2. 6.12.5.1.2 SPI Slave Mode Timings
            1. 6.12.5.1.2.1 SPI Slave Mode Timing Requirements
            2. 6.12.5.1.2.2 SPI Slave Mode Switching Characteristics
      6. 6.12.6 Universal Serial Bus (USB) Controller
        1. 6.12.6.1 USB Electrical Data and Timing
          1. 6.12.6.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.12.6.1.2 USB Output Ports DP and DM Switching Characteristics
      7. 6.12.7 Universal Parallel Port (uPP) Interface
        1. 6.12.7.1 uPP Electrical Data and Timing
          1. 6.12.7.1.1 uPP Timing Requirements
          2. 6.12.7.1.2 uPP Switching Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 C28x Memory Map
      2. 7.3.2 Flash Memory Map
      3. 7.3.3 EMIF Chip Select Memory Map
      4. 7.3.4 Peripheral Registers Memory Map
      5. 7.3.5 Memory Types
        1. 7.3.5.1 Dedicated RAM (Mx and Dx RAM)
        2. 7.3.5.2 Local Shared RAM (LSx RAM)
        3. 7.3.5.3 Global Shared RAM (GSx RAM)
        4. 7.3.5.4 CLA Message RAM (CLA MSGRAM)
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit
      2. 7.6.2 Trigonometric Math Unit
      3. 7.6.3 Viterbi, Complex Math, and CRC Unit II
    7. 7.7  Control Law Accelerator
    8. 7.8  Direct Memory Access
    9. 7.9  Boot ROM and Peripheral Booting
      1. 7.9.1 EMU Boot or Emulation Boot
      2. 7.9.2 WAIT Boot Mode
      3. 7.9.3 Get Mode
      4. 7.9.4 Peripheral Pins Used by Bootloaders
    10. 7.10 Dual Code Security Module
    11. 7.11 Timers
    12. 7.12 Nonmaskable Interrupt With Watchdog Timer (NMIWD)
    13. 7.13 Watchdog
    14. 7.14 Configurable Logic Block (CLB)
    15. 7.15 Functional Safety
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 Servo Drive Control Module
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Servo Drive Control Module Resources
        2. 8.3.1.2 Solar Micro Inverter
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 Solar Micro Inverter Resources
        3. 8.3.1.3 On-Board Charger (OBC)
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 OBC Resources
        4. 8.3.1.4 EV Charging Station Power Module
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 EV Charging Station Power Module Resources
        5. 8.3.1.5 High-Voltage Traction Inverter
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 High-Voltage Traction Inverter Resources
        6. 8.3.1.6 Single-Phase Online UPS
          1. 8.3.1.6.1 System Block Diagram
          2. 8.3.1.6.2 Single-Phase Online UPS Resources
  10. 9 Device and Documentation Support
    1. 9.1 Device and Development Support Tool Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZP|100
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.9.10.3.6 HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETERMINMAXUNIT
td(IDLE-XCOS)Delay time, IDLE instruction executed to XCLKOUT stop16tc(INTOSC1)cycles
td(WAKE-HALT)Delay time, external wake signal end to CPU1 program execution resumecycles
  • Wakeup from flash
    • Flash module in active state
75tc(OSCCLK)
  • Wakeup from flash
    • Flash module in sleep state
17500tc(OSCCLK) (1)
  • Wakeup from RAM
75tc(OSCCLK)
(1) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xS Real-Time Microcontrollers Technical Reference Manual. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.
GUID-0BD58B63-D624-4576-81FC-683F496CD4C1-low.gif
A. IDLE instruction is executed to put the device into HALT mode.
B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing a 1 to CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wakeup sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is now exited.
G. Normal operation resumes.
H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.
Figure 6-23 HALT Entry and Exit Timing Diagram

Section 6.9.10.3.7 shows the HIBERNATE mode timing requirements, Section 6.9.10.3.8 shows the switching characteristics, and Figure 6-24 shows the timing diagram for HIBERNATE mode.