Table 4-1 Device Current Consumption at 200-MHz SYSCLK

4.4.1 Current Consumption Graphs

Figure 4-2 and Figure 4-3 are a typical representation of the relationship between frequency and current consumption/power on the device. The operational test from Table 4-1 was run across frequency at V_max and high temperature. Actual results will vary based on the system implementation and conditions.

Figure 4-2 Operational Current Versus Frequency

Figure 4-3 Power Versus Frequency

Leakage current will increase with operating temperature in a nonlinear manner. The difference in V_DD current between TYP and MAX conditions can be seen in Figure 4-4. The current consumption in HALT mode is primarily leakage current as there is no active switching if the internal oscillator has been powered down.

Figure 4-4 shows the typical leakage current across temperature. The device was placed into HALT mode under nominal voltage conditions.

Figure 4-4 I_DD Leakage Current Versus Temperature

4.4.2 Reducing Current Consumption

The F28377D provides some methods to reduce the device current consumption:

• Any one of the four low-power modes—IDLE, STANDBY, HALT, and HIBERNATE—could be entered during idle periods in the application.
• The flash module may be powered down if the code is run from RAM.
• Disable the pullups on pins that assume an output function.
• Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be achieved by turning off the clock to any peripheral that is not used in a given application. Table 4-2 indicates the typical current reduction that may be achieved by disabling the clocks using the PCLKCRx register.

4.6.1 GWT Package

4.6.2 PTP Package

4.7.1 Power Sequencing

An external power supply must be used to supply 3.3 V to V_DDIO, V_DD3VFL, V_DDOSC, and V_DDA and to provide 1.2 V to V_DD. The internal VREG is not supported; therefore, the VREGENZ pin must be tied high to 3.3 V. The supplies should ramp to full rail within 10 ms. Table 4-3 shows the supply ramp rate.

The voltage on V_DDIO should be greater than V_DD or no less than 0.3 V below V_DD at all times. V_DDIO, V_DD3VFL, V_DDOSC, and V_DDA should be powered up together and be kept within 0.3 V of each other during operation. Before powering the device, no voltage larger than 0.3 V above V_DDIO should be applied to any digital pin, and no voltage larger than 0.3 V above V_DDA should be applied to any analog pin. The V_REFHI voltage should not exceed V_DDA at any time.

An internal power-on-reset (POR) circuit holds the device in reset and keeps the I/Os in a high-impedance state during power up. External supply voltage supervisors (SVS) can be used to monitor the voltage on the 3.3-V and 1.2-V rails and drive XRS low should supplies fall outside operational specifications.

4.7.2 Reset Timing

XRS is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on reset (POR). During power up, the POR circuit drives the XRS pin low. A watchdog or NMI watchdog reset also drives the pin low. An external circuit may drive the pin to assert a device reset.

A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and V_DDIO. A capacitor should be placed between XRS and V_SS for noise filtering; the capacitance should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to V_OL within 512 OSCCLK cycles when the watchdog reset is asserted. Figure 4-5 shows the recommended reset circuit.

Figure 4-5 Reset Circuit

4.7.2.2 Reset Electrical Data and Timing

Table 4-4 shows the reset (XRS) timing requirements. Table 4-5 shows the reset (XRS) switching characteristics. Figure 4-6 shows the power-on reset. Figure 4-7 shows the warm reset.

Table 4-4 Reset (XRS) Timing Requirements

		MIN	MAX	UNIT
th(boot-mode)	Hold time for boot-mode pins	1.5		ms
tw(RSL2)	Pulse duration, XRS low on warm reset	3.2		µs

Table 4-5 Reset (XRS) Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		MIN	TYP	MAX	UNIT
tw(RSL1)	Pulse duration, XRS driven low by device after supplies are stable		100		µs
tw(WDRS)	Pulse duration, reset pulse generated by watchdog		512tc(OSCCLK)		cycles

A. The XRS pin can be driven externally by a supervisor or an external pullup resistor, see Table 3-1. On-chip POR logic will hold this pin low until the supplies are in a valid range.

B. After reset from any source (see Section 4.7.2.1), the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled.

Figure 4-6 Power-on Reset

A. After reset from any source (see Section 4.7.2.1), the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled.

Figure 4-7 Warm Reset

4.7.3 Clock Specifications

4.7.3.1 Clock Sources

Table 4-6 lists four possible clock sources. Figure 4-8 provides an overview of the device's clocking system.

Table 4-6 Possible Reference Clock Sources

CLOCK SOURCE	MODULES CLOCKED	COMMENTS
INTOSC1	Can be used to provide clock for: Watchdog block Main PLL CPU-Timer 2	Internal oscillator 1. Zero-pin overhead 10-MHz internal oscillator.
INTOSC2(1)	Can be used to provide clock for: Main PLL Auxiliary PLL CPU-Timer 2	Internal oscillator 2. Zero-pin overhead 10-MHz internal oscillator.
XTAL	Can be used to provide clock for: Main PLL Auxiliary PLL CPU-Timer 2	External crystal or resonator connected between the X1 and X2 pins or single-ended clock connected to the X1 pin.
AUXCLKIN	Can be used to provide clock for: Auxiliary PLL CPU-Timer 2	Single-ended 3.3-V level clock source. GPIO133/AUXCLKIN pin should be used to provide the input clock.

(1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for both system PLL (OSCCLK) and auxiliary PLL (AUXOSCCLK).

Figure 4-8 Clocking System

4.7.3.3 Input Clocks and PLLs

In addition to the internal 0-pin oscillators, multiple external clock source options are available. Figure 4-9 shows the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2 (also referred to as XTAL) and AUXCLKIN.

Figure 4-9 Connecting Input Clocks to a 2837xD Device

4.7.4 Flash Parameters

The on-chip flash memory is tightly integrated to the CPU, allowing code execution directly from flash through 128-bit-wide prefetch reads and a pipeline buffer. Flash performance for sequential code is equal to execution from RAM. Factoring in discontinuities, most applications will run with an efficiency of approximately 80% relative to code executing from RAM. This flash efficiency lets designers realize a 2× improvement in performance when migrating from the previous generation Delfino MCUs.

This device also has an OTP (One-Time-Programmable) sector used for the dual code security module (DCSM), which cannot be erased after it is programmed.

Table 4-19 shows the minimum required flash wait states at different frequencies. Table 4-20 shows the flash parameters.

4.7.5 Emulation/JTAG

The JTAG port has five dedicated pins: TRST, TMS, TDI, TDO, and TCK. The TRST signal should always be pulled down through a 2.2-kΩ pulldown resistor on the board. This MCU does not support the EMU0 and EMU1 signals that are present on 14-pin and 20-pin emulation headers. These signals should always be pulled up at the emulation header through a pair of board pullup resistors ranging from 2.2 kΩ to 4.7 kΩ (depending on the drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.

See Figure 4-10 to see how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 4-11 shows how to connect to the 20-pin header. The 20-pin JTAG header terminals EMU2, EMU3, and EMU4 are not used and should be grounded.

The PD (Power Detect) terminal of the emulator header should be connected to the board 3.3-V supply. Header GND terminals should be connected to board ground. TDIS (Cable Disconnect Sense) should also be connected to board ground. The JTAG clock should be looped from the header TCK output terminal back to the RTCK input terminal of the header (to sense clock continuity by the emulator). Header terminal RESET is an open-drain output from the emulator header that enables board components to be reset through emulator commands (available only through the 20-pin header).

Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the JTAG header is smaller than 6 in (15.24 cm), and no other devices are present on the JTAG chain. Otherwise, each signal should be buffered. Additionally, for most emulator operations at 10 MHz, no series resistors are needed on the JTAG signals. However, if high emulation speeds are expected (35 MHz or so), 22-Ω resistors should be placed in series on each JTAG signal.

For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and Watchpoints for C28x in CCS.

For more information about JTAG emulation, see the XDS Target Connection Guide.

Figure 4-10 Connecting to the 14-Pin JTAG Header

Figure 4-11 Connecting to the 20-Pin JTAG Header

4.7.5.1 JTAG Electrical Data and Timing

Table 4-21 lists the JTAG timing requirements. Table 4-22 lists the JTAG switching characteristics. Figure 4-12 shows the JTAG timing.

Table 4-21 JTAG Timing Requirements

NO.			MIN	MAX	UNIT
1	tc(TCK)	Cycle time, TCK	66.66		ns
1a	tw(TCKH)	Pulse duration, TCK high (40% of tc)	26.66		ns
1b	tw(TCKL)	Pulse duration, TCK low (40% of tc)	26.66		ns
3	tsu(TDI-TCKH)	Input setup time, TDI valid to TCK high	13		ns
	tsu(TMS-TCKH)	Input setup time, TMS valid to TCK high	13		ns
4	th(TCKH-TDI)	Input hold time, TDI valid from TCK high	7		ns
	th(TCKH-TMS)	Input hold time, TMS valid from TCK high	7		ns

Table 4-22 JTAG Switching Characteristics

over recommended operating conditions (unless otherwise noted)

NO.	PARAMETER		MIN	MAX	UNIT
2	td(TCKL-TDO)	Delay time, TCK low to TDO valid	6	25	ns

Figure 4-12 JTAG Timing

4.7.6 GPIO Electrical Data and Timing

The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pins are configured as inputs. For specific inputs, the user can also select the number of input qualification cycles to filter unwanted noise glitches.

The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed to a GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an Input X-BAR which is used to route signals from any GPIO input to different IP blocks such as the ADC(s), eCAP(s), ePWM(s), and external interrupts. For more details, see the X-BAR chapter in the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual.

4.7.6.1 GPIO - Output Timing

Table 4-23 shows the general-purpose output switching characteristics. Figure 4-13 shows the general-purpose output timing.

Table 4-23 General-Purpose Output Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER			MIN	MAX	UNIT
tr(GPO)	Rise time, GPIO switching low to high	All GPIOs		8(1)	ns
tf(GPO)	Fall time, GPIO switching high to low	All GPIOs		8(1)	ns
tfGPO	Toggling frequency, GPO pins			25	MHz

(1) Rise time and fall time vary with load. These values assume a 40-pF load.

Figure 4-13 General-Purpose Output Timing

4.7.6.2 GPIO - Input Timing

Table 4-24 shows the general-purpose input timing requirements. Figure 4-14 shows the sampling mode.

Table 4-24 General-Purpose Input Timing Requirements

			MIN	MAX	UNIT
tw(SP)	Sampling period	QUALPRD = 0	1tc(SYSCLK)		cycles
		QUALPRD ≠ 0	2tc(SYSCLK) * QUALPRD		cycles
tw(IQSW)	Input qualifier sampling window		tw(SP) * (n(1) – 1)		cycles
tw(GPI) (2)	Pulse duration, GPIO low/high	Synchronous mode	2tc(SYSCLK)		cycles
		With input qualifier	tw(IQSW) + tw(SP) + 1tc(SYSCLK)		cycles

(1) "n" represents the number of qualification samples as defined by GPxQSELn register.

(2) For t_w(GPI), pulse width is measured from V_IL to V_IL for an active low signal and V_IH to V_IH for an active high signal.

A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification sampling period in 2n SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled).

B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.

C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.

D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLK cycles. This would ensure 5 sampling periods for detection to occur. Because external signals are driven asynchronously, an 13-SYSCLK-wide pulse ensures reliable recognition.

Figure 4-14 Sampling Mode

4.7.6.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier configurations.

Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.

Equation 1.

Equation 2.

Equation 3.

In Equation 1, Equation 2, and Equation 3, SYSCLK cycle indicates the time period of SYSCLK.

Sampling period = SYSCLK cycle, if QUALPRD = 0

In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the signal. This is determined by the value written to GPxQSELn register.

Case 1:

Qualification using 3 samples

Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0

Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0

Case 2:

Qualification using 6 samples

Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0

Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0

Figure 4-15 shows the general-purpose input timing.

Figure 4-15 General-Purpose Input Timing

4.7.7 Interrupts

Figure 4-16 provides a high-level view of the interrupt architecture.

As shown in Figure 4-16, the devices support five external interrupts (XINT1 to XINT5) that can be mapped onto any of the GPIO pins.

In this device, 16 ePIE block interrupts are grouped into 1 CPU interrupt. In total, there are 12 CPU interrupt groups, with 16 interrupts per group.

Figure 4-16 External and ePIE Interrupt Sources

4.7.7.1 External Interrupt (XINT) Electrical Data and Timing

Table 4-25 lists the external interrupt timing requirements. Table 4-26 lists the external interrupt switching characteristics. Figure 4-17 shows the external interrupt timing.

Table 4-25 External Interrupt Timing Requirements⁽¹⁾

			MIN	MAX	UNIT
tw(INT)	Pulse duration, INT input low/high	Synchronous	2tc(SYSCLK)		cycles
		With qualifier	tw(IQSW) + tw(SP) + 1tc(SYSCLK)		cycles

(1) For an explanation of the input qualifier parameters, see Table 4-24.

Table 4-26 External Interrupt Switching Characteristics⁽¹⁾

over recommended operating conditions (unless otherwise noted)

PARAMETER		MIN	MAX	UNIT
td(INT)	Delay time, INT low/high to interrupt-vector fetch(2)	tw(IQSW) + 14tc(SYSCLK)	tw(IQSW) + tw(SP) + 14tc(SYSCLK)	cycles

(1) For an explanation of the input qualifier parameters, see Table 4-24.

(2) This assumes that the ISR is in a single-cycle memory.

Figure 4-17 External Interrupt Timing

4.7.8 Low-Power Modes

This device has three clock-gating low-power modes and a special power-gating mode.

Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the Low Power Modes section of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual.

4.7.8.3 Low-Power Mode Wakeup Timing

Table 4-29 shows the IDLE mode timing requirements, Table 4-30 shows the switching characteristics, and Figure 4-18 shows the timing diagram for IDLE mode.

Table 4-29 IDLE Mode Timing Requirements⁽¹⁾

				MIN	MAX	UNIT
tw(WAKE)	Pulse duration, external wake-up signal		Without input qualifier	2tc(SYSCLK)		cycles
			With input qualifier	2tc(SYSCLK) + tw(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 4-24.

Table 4-30 IDLE Mode Switching Characteristics⁽¹⁾

over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
td(WAKE-IDLE)	Delay time, external wake signal to program execution resume (2)				cycles
	Wakeup from Flash Flash module in active state	Without input qualifier		40tc(SYSCLK)
		With input qualifier		40tc(SYSCLK) + tw(WAKE)
	Wakeup from Flash Flash module in sleep state	Without input qualifier		6700tc(SYSCLK)(3)
		With input qualifier		6700tc(SYSCLK)(3) + tw(WAKE)
	Wakeup from RAM	Without input qualifier		25tc(SYSCLK)
		With input qualifier		25tc(SYSCLK) + tw(WAKE)

(1) For an explanation of the input qualifier parameters, see Table 4-24.

(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the wake-up signal) involves additional latency.

(3) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.

A. WAKE can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.

Figure 4-18 IDLE Entry and Exit Timing Diagram

Table 4-31 shows the STANDBY mode timing requirements, Table 4-32 shows the switching characteristics, and Figure 4-19 shows the timing diagram for STANDBY mode.

Table 4-31 STANDBY Mode Timing Requirements

				MIN	MAX	UNIT
tw(WAKE-INT)	Pulse duration, external wake-up signal		QUALSTDBY = 0 | 2tc(OSCCLK)	3tc(OSCCLK)		cycles
			QUALSTDBY > 0 | (2 + QUALSTDBY)tc(OSCCLK)(1)	(2 + QUALSTDBY) * tc(OSCCLK)

(1) QUALSTDBY is a 6-bit field in the LPMCR register.

Table 4-32 STANDBY Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
td(IDLE-XCOS)	Delay time, IDLE instruction executed to XCLKOUT stop			16tc(INTOSC1)	cycles
td(WAKE-STBY)	Delay time, external wake signal to program execution resume(1)				cycles
	Wakeup from flash Flash module in active state			175tc(SYSCLK) + tw(WAKE-INT)
	Wakeup from flash Flash module in sleep state			6700tc(SYSCLK)(2) + tw(WAKE-INT)
	Wakeup from RAM			3tc(OSC) + 15tc(SYSCLK) + tw(WAKE-INT)

(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the wake-up signal) involves additional latency.

(2) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.

A. IDLE instruction is executed to put the device into STANDBY mode.

B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This delay enables the CPU pipeline and any other pending operations to flush properly.

C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.

D. The external wake-up signal is driven active.

E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.

F. After a latency period, the STANDBY mode is exited.

G. Normal execution resumes. The device will respond to the interrupt (if enabled).

Figure 4-19 STANDBY Entry and Exit Timing Diagram

Table 4-33 shows the HALT mode timing requirements, Table 4-34 shows the switching characteristics, and Figure 4-20 shows the timing diagram for HALT mode.

Table 4-33 HALT Mode Timing Requirements

			MIN	MAX	UNIT
tw(WAKE-GPIO)	Pulse duration, GPIO wake-up signal(1)		toscst + 2tc(OSCCLK)		cycles
tw(WAKE-XRS)	Pulse duration, XRS wake-up signal(1)		toscst + 8tc(OSCCLK)		cycles

(1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on circuit/layout external to the device. See Table 4-17 for more information. For applications using INTOSC1 or INTOSC2 for OSCCLK, see Section 4.7.3.5 for t_oscst. Oscillator start-up time does not apply to applications using a single-ended crystal on the X1 pin, as it is powered externally to the device.

Table 4-34 HALT Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		MIN	MAX	UNIT
td(IDLE-XCOS)	Delay time, IDLE instruction executed to XCLKOUT stop		16tc(INTOSC1)	cycles
td(WAKE-HALT)	Delay time, external wake signal end to CPU1 program execution resume			cycles
	Wakeup from flash Flash module in active state		75tc(OSCCLK)
	Wakeup from flash Flash module in sleep state		17500tc(OSCCLK) (1)
	Wakeup from RAM		75tc(OSCCLK)

(1) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.

A. IDLE instruction is executed to put the device into HALT mode.

B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This delay enables the CPU pipeline and any other pending operations to flush properly.

C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing a 1 to CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.

D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wakeup sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode.

E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.

F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is now exited.

G. Normal operation resumes.

H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.

Figure 4-20 HALT Entry and Exit Timing Diagram

NOTE

CPU2 should enter IDLE mode before CPU1 puts the device into HALT mode. CPU1 should verify that CPU2 has entered IDLE mode using the LPMSTAT register before calling the IDLE instruction to enter HALT.

Table 4-35 shows the HIBERNATE mode timing requirements, Table 4-36 shows the switching characteristics, and Figure 4-21 shows the timing diagram for HIBERNATE mode.

Table 4-35 HIBERNATE Mode Timing Requirements

		MIN	MAX	UNIT
tw(HIBWAKE)	Pulse duration, HIBWAKE signal	40		µs
tw(WAKEXRS)	Pulse duration, XRS wake-up signal	40		µs

Table 4-36 HIBERNATE Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		MIN	MAX	UNIT
td(IDLE-XCOS)	Delay time, IDLE instruction executed to XCLKOUT stop		30tc(SYSCLK)	cycles
td(WAKE-HIB)	Delay time, external wake signal to lORestore function start		1.5	ms

A. CPU1 does necessary application-specific context save to M0/M1 memories if required. This includes GPIO state if using I/O Isolation. Configures the LPMCR register of CPU1 for HIBERNATE mode. Powers down Flash Pump/Bank, USB-PHY, CMPSS, DAC, and ADC using their register configurations. The application should also power down the PLL and peripheral clocks before entering HIBERNATE. In dual-core applications, CPU1 should confirm that CPU2 has entered IDLE/STANDBY using the LPMSTAT register.

B. IDLE instruction is executed to put the device into HIBERNATE mode.

C. The device is now in HIBERNATE mode. If configured, I/O isolation is turned on, M0 and M1 memories are retained. CPU1 and CPU2 are powered down. Digital peripherals are powered down. The oscillators, PLLs, analog peripherals, and Flash are in their software-controlled Low-Power modes. Dx, LSx, and GSx memories are also powered down, and their memory contents lost.

D. A falling edge on the GPIOHIBWAKEn pin will drive the wakeup of the devices clock sources INTOSC1, INTOSC2, and X1/X2 OSC. The wakeup source must keep the GPIOHIBWAKEn pin low long enough to ensure full power-up of these clock sources.

E. After the clock sources are powered up, the GPIOHIBWAKEn must be driven high to trigger the wakeup sequence of the remainder of the device.

F. The BootROM will then begin to execute. The BootROM can distinguish a HIBERNATE wakeup by reading the CPU1.REC.HIBRESETn bit. After the TI OTP trims are loaded, the BootROM code will branch to the user-defined IoRestore function if it has been configured.

G. At this point, the device is out of HIBERNATE mode, and the application may continue.

H. The IoRestore function is a user-defined function where the application may reconfigure GPIO states, disable I/O isolation, reconfigure the PLL, restore peripheral configurations, or branch to application code. This is up to the application requirements.

I. If the application has not branched to application code, the BootROM will continue after completing IoRestore. It will disable I/O isolation automatically if it was not taken care of inside of IoRestore. CPU2 will be brought out of reset at this point as well.

J. BootROM will then boot as determined by the HIBBOOTMODE register. Refer to the ROM Code and Peripheral Booting chapter of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual for more information.

Figure 4-21 HIBERNATE Entry and Exit Timing Diagram

NOTE

1. If the IORESTOREADDR is configured as the default value, the BootROM will continue its execution to boot as determined by the HIBBOOTMODE register. Refer to the ROM Code and Peripheral Booting chapter of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual for more information.
2. The user may choose to disable I/O Isolation at any point in the IoRestore function. Regardless if the user has disabled Isolation in the IoRestore function or if IoRestore is not defined, the BootROM will automatically disable isolation before booting as determined by the HIBBOOTMODE register.

NOTE

For applications using both CPU1 and CPU2, TI recommends that the application puts CPU2 in either IDLE or STANDBY before entering HIBERNATE mode. If any GPIOs are used and the state is to be preserved, data can be stored in M0/M1 memory of CPU1 to be reconfigured upon wakeup. This should be done before step A of Figure 4-21.

4.7.9 External Memory Interface (EMIF)

The EMIF provides a means of connecting the CPU to various external storage devices like asynchronous memories (SRAM, NOR flash) or synchronous memory (SDRAM).

Additionally, the EMIF supports placing the SDRAM in self-refresh and power-down modes. Self-refresh mode allows the SDRAM to be put in a low-power state while still retaining memory contents because the SDRAM will continue to refresh itself even without clocks from the microcontroller. Power-down mode achieves even lower power, except the microcontroller must periodically wake up and issue refreshes if data retention is required. The EMIF module does not support mobile SDRAM devices.

On this device, the EMIF does not support burst access for SDRAM configurations. This means every access to an external SDRAM device will have CAS latency.

4.7.9.3 EMIF Electrical Data and Timing

4.7.9.3.1 Asynchronous RAM

Table 4-37 shows the EMIF asynchronous memory timing requirements. Table 4-38 shows the EMIF asynchronous memory switching characteristics. Figure 4-22 through Figure 4-25 show the EMIF asynchronous memory timing diagrams.

Table 4-37 EMIF Asynchronous Memory Timing Requirements⁽¹⁾

NO.			MIN	MAX	UNIT
Reads and Writes
	E	EMIF clock period	tc(SYSCLK)		ns
2	tw(EM_WAIT)	Pulse duration, EMxWAIT assertion and deassertion	2E		ns
Reads
12	tsu(EMDV-EMOEH)	Setup time, EMxD[y:0] valid before EMxOE high	15		ns
13	th(EMOEH-EMDIV)	Hold time, EMxD[y:0] valid after EMxOE high	0		ns
14	tsu(EMOEL-EMWAIT)	Setup Time, EMxWAIT asserted before end of Strobe Phase(2)	4E+20		ns
Writes
28	tsu(EMWEL-EMWAIT)	Setup Time, EMxWAIT asserted before end of Strobe Phase(2)	4E+20		ns

(1) E = EMxCLK period in ns.

(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMxWAIT must be asserted to add extended wait states. Figure 4-23 and Figure 4-25 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles.

Table 4-38 EMIF Asynchronous Memory Switching Characteristics^(1)(2)(3)

NO.	PARAMETER		MIN	MAX	UNIT
Reads and Writes
1	td(TURNAROUND)	Turn around time	(TA)*E–3	(TA)*E+2	ns
Reads
3	tc(EMRCYCLE)	EMIF read cycle time (EW = 0)	(RS+RST+RH+2)*E–3	(RS+RST+RH+2)*E+2	ns
		EMIF read cycle time (EW = 1)	(RS+RST+RH+2+ (EWC*16))*E–3	(RS+RST+RH+2+ (EWC*16))*E+2	ns
4	tsu(EMCEL-EMOEL)	Output setup time, EMxCS[y:2] low to EMxOE low (SS = 0)	(RS)*E–3	(RS)*E+2	ns
		Output setup time, EMxCS[y:2] low to EMxOE low (SS = 1)	–3	2	ns
5	th(EMOEH-EMCEH)	Output hold time, EMxOE high to EMxCS[y:2] high (SS = 0)	(RH)*E–3	(RH)*E	ns
		Output hold time, EMxOE high to EMxCS[y:2] high (SS = 1)	–3	0	ns
6	tsu(EMBAV-EMOEL)	Output setup time, EMxBA[y:0] valid to EMxOE low	(RS)*E–3	(RS)*E+2	ns
7	th(EMOEH-EMBAIV)	Output hold time, EMxOE high to EMxBA[y:0] invalid	(RH)*E–3	(RH)*E	ns
8	tsu(EMAV-EMOEL)	Output setup time, EMxA[y:0] valid to EMxOE low	(RS)*E–3	(RS)*E+2	ns
9	th(EMOEH-EMAIV)	Output hold time, EMxOE high to EMxA[y:0] invalid	(RH)*E–3	(RH)*E	ns
10	tw(EMOEL)	EMxOE active low width (EW = 0)	(RST)*E–1	(RST)*E+1	ns
		EMxOE active low width (EW = 1)	(RST+(EWC*16))*E–1	(RST+(EWC*16))*E+1	ns
11	td(EMWAITH-EMOEH)	Delay time from EMxWAIT deasserted to EMxOE high	4E+10	5E+15	ns
29	tsu(EMDQMV-EMOEL)	Output setup time, EMxDQM[y:0] valid to EMxOE low	(RS)*E–3	(RS)*E+2	ns
30	th(EMOEH-EMDQMIV)	Output hold time, EMxOE high to EMxDQM[y:0] invalid	(RH)*E–3	(RH)*E	ns
Writes
15	tc(EMWCYCLE)	EMIF write cycle time (EW = 0)	(WS+WST+WH+2)*E–3	(WS+WST+WH+2)*E+1	ns
		EMIF write cycle time (EW = 1)	(WS+WST+WH+2+ (EWC*16))*E–3	(WS+WST+WH+2+ (EWC*16))*E+1	ns
16	tsu(EMCEL-EMWEL)	Output setup time, EMxCS[y:2] low to EMxWE low (SS = 0)	(WS)*E–3	(WS)*E+1	ns
		Output setup time, EMxCS[y:2] low to EMxWE low (SS = 1)	–3	1	ns
17	th(EMWEH-EMCEH)	Output hold time, EMxWE high to EMxCS[y:2] high (SS = 0)	(WH)*E–3	(WH)*E	ns
		Output hold time, EMxWE high to EMxCS[y:2] high (SS = 1)	–3	0	ns
18	tsu(EMDQMV-EMWEL)	Output setup time, EMxDQM[y:0] valid to EMxWE low	(WS)*E–3	(WS)*E+1	ns
19	th(EMWEH-EMDQMIV)	Output hold time, EMxWE high to EMxDQM[y:0] invalid	(WH)*E–3	(WH)*E	ns
20	tsu(EMBAV-EMWEL)	Output setup time, EMxBA[y:0] valid to EMxWE low	(WS)*E–3	(WS)*E+1	ns
21	th(EMWEH-EMBAIV)	Output hold time, EMxWE high to EMxBA[y:0] invalid	(WH)*E–3	(WH)*E	ns
22	tsu(EMAV-EMWEL)	Output setup time, EMxA[y:0] valid to EMxWE low	(WS)*E–3	(WS)*E+1	ns
23	th(EMWEH-EMAIV)	Output hold time, EMxWE high to EMxA[y:0] invalid	(WH)*E–3	(WH)*E	ns
24	tw(EMWEL)	EMxWE active low width (EW = 0)	(WST)*E–1	(WST)*E+1	ns
		EMxWE active low width (EW = 1)	(WST+(EWC*16))*E–1	(WST+(EWC*16))*E+1	ns
25	td(EMWAITH-EMWEH)	Delay time from EMxWAIT deasserted to EMxWE high	4E+10	5E+15	ns
26	tsu(EMDV-EMWEL)	Output setup time, EMxD[y:0] valid to EMxWE low	(WS)*E–3	(WS)*E+1	ns
27	th(EMWEH-EMDIV)	Output hold time, EMxWE high to EMxD[y:0] invalid	(WH)*E–3	(WH)*E	ns

(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–4], RH[8–1], WS[16–1], WST[64–1], WH[8–1], and MEWC[1–256]. See the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual for more information.

(2) E = EMxCLK period in ns.

(3) EWC = external wait cycles determined by EMxWAIT input signal. EWC supports the following range of values. EWC[256–1]. The maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual for more information.

Figure 4-22 Asynchronous Memory Read Timing

Figure 4-23 EMxWAIT Read Timing Requirements

Figure 4-24 Asynchronous Memory Write Timing

Figure 4-25 EMxWAIT Write Timing Requirements

4.7.9.3.2 Synchronous RAM

Table 4-39 shows the EMIF synchronous memory timing requirements. Table 4-40 shows the EMIF synchronous memory switching characteristics. Figure 4-26 and Figure 4-27 show the synchronous memory timing diagrams.

Table 4-39 EMIF Synchronous Memory Timing Requirements

NO.			MIN	MAX	UNIT
19	tsu(EMIFDV-EM_CLKH)	Input setup time, read data valid on EMxD[y:0] before EMxCLK rising	2		ns
20	th(CLKH-DIV)	Input hold time, read data valid on EMxD[y:0] after EMxCLK rising	1.5		ns

Table 4-40 EMIF Synchronous Memory Switching Characteristics

NO.	PARAMETER		MIN	MAX	UNIT
1	tc(CLK)	Cycle time, EMIF clock EMxCLK	10		ns
2	tw(CLK)	Pulse width, EMIF clock EMxCLK high or low	3		ns
3	td(CLKH-CSV)	Delay time, EMxCLK rising to EMxCS[y:2] valid		8	ns
4	toh(CLKH-CSIV)	Output hold time, EMxCLK rising to EMxCS[y:2] invalid	1		ns
5	td(CLKH-DQMV)	Delay time, EMxCLK rising to EMxDQM[y:0] valid		8	ns
6	toh(CLKH-DQMIV)	Output hold time, EMxCLK rising to EMxDQM[y:0] invalid	1		ns
7	td(CLKH-AV)	Delay time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] valid		8	ns
8	toh(CLKH-AIV)	Output hold time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] invalid	1		ns
9	td(CLKH-DV)	Delay time, EMxCLK rising to EMxD[y:0] valid		8	ns
10	toh(CLKH-DIV)	Output hold time, EMxCLK rising to EMxD[y:0] invalid	1		ns
11	td(CLKH-RASV)	Delay time, EMxCLK rising to EMxRAS valid		8	ns
12	toh(CLKH-RASIV)	Output hold time, EMxCLK rising to EMxRAS invalid	1		ns
13	td(CLKH-CASV)	Delay time, EMxCLK rising to EMxCAS valid		8	ns
14	toh(CLKH-CASIV)	Output hold time, EMxCLK rising to EMxCAS invalid	1		ns
15	td(CLKH-WEV)	Delay time, EMxCLK rising to EMxWE valid		8	ns
16	toh(CLKH-WEIV)	Output hold time, EMxCLK rising to EMxWE invalid	1		ns
17	td(CLKH-DHZ)	Delay time, EMxCLK rising to EMxD[y:0] tri-stated		8	ns
18	toh(CLKH-DLZ)	Output hold time, EMxCLK rising to EMxD[y:0] driving	1		ns

Figure 4-26 Basic SDRAM Read Operation

Figure 4-27 Basic SDRAM Write Operation

4.8.1 Analog-to-Digital Converter (ADC)

The ADCs on this device are successive approximation (SAR) style ADCs with selectable resolution of either 16 bits or 12 bits. There are multiple ADC modules which allow simultaneous sampling. The ADC wrapper is start-of-conversion (SOC) based [see the SOC Principle of Operation section of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual.

Each ADC has the following features:

• Selectable resolution of 16 bits or 12 bits
• Ratiometric external reference set by V_REFHI and V_REFLO
• Differential signal conversions (16-bit mode only)
• Single-ended signal conversions (12-bit mode only)
• Input multiplexer with up to 16 channels (single-ended) or 8 channels (differential)
• 16 configurable SOCs
• 16 individually addressable result registers
• Multiple trigger sources
  • Software immediate start
  • All ePWMs
  • GPIO XINT2
  • CPU timers
  • ADCINT1 or 2
• Four flexible PIE interrupts
• Burst mode
• Four post-processing blocks, each with:
  • Saturating offset calibration
  • Error from setpoint calculation
  • High, low, and zero-crossing compare, with interrupt and ePWM trip capability
  • Trigger-to-sample delay capture

Figure 4-31 shows the ADC module block diagram.

Figure 4-31 ADC Module Block Diagram

4.8.1.1 ADC Electrical Data and Timing

Table 4-41 shows the ADC operating conditions for 16-bit differential mode. Table 4-42 shows the ADC characteristics for 16-bit differential mode. Table 4-43 shows the ADC operating conditions for 12-bit single-ended mode. Table 4-44 shows the ADC characteristics for 12-bit single-ended mode. Table 4-45 shows the ADCEXTSOC timing requirements.

Table 4-41 ADC Operating Conditions (16-Bit Differential Mode)

over recommended operating conditions (unless otherwise noted)

		MIN	TYP	MAX	UNIT
ADCCLK (derived from PERx.SYSCLK)		5		50	MHz
Sample window duration (set by ACQPS and PERx.SYSCLK)(1)		320			ns
VREFHI		2.4	2.5 or 3.0	VDDA	V
VREFLO		VSSA	0	VSSA	V
VREFHI – VREFLO		2.4		VDDA	V
ADC input conversion range		VREFLO		VREFHI	V
ADC input signal common mode voltage(2)(3)		VREFCM – 50	VREFCM	VREFCM + 50	mV

(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.

(2) V_REFCM = (V_REFHI + V_REFLO)/2

(3) The V_REFCM requirements will not be met if the negative ADC input pin is connected to V_SSA or V_REFLO.

NOTE

The ADC inputs should be kept below V_DDA + 0.3 V during operation. If an ADC input exceeds this level, the V_REF internal to the device may be disturbed, which can impact results for other ADC or DAC inputs using the same V_REF.

Table 4-42 ADC Characteristics (16-Bit Differential Mode)

over recommended operating conditions (unless otherwise noted)⁽⁶⁾

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
ADC conversion cycles(1)		29.6		31	ADCCLKs
Power-up time (after setting ADCPWDNZ to first conversion)				500	µs
Gain error		–64	±9	64	LSBs
Offset error(2)		–16	±9	16	LSBs
Channel-to-channel gain error			±6		LSBs
Channel-to-channel offset error			±3		LSBs
ADC-to-ADC gain error	Identical VREFHI and VREFLO for all ADCs		±6		LSBs
ADC-to-ADC offset error	Identical VREFHI and VREFLO for all ADCs		±3		LSBs
DNL(3)		> –1	±0.5	1	LSBs
INL		–3	±1.5	3	LSBs
SNR(4)(11)	VREFHI = 2.5 V, fin = 10 kHz		87.6		dB
THD(4)(11)	VREFHI = 2.5 V, fin = 10 kHz		–93.5		dB
SFDR(4)(11)	VREFHI = 2.5 V, fin = 10 kHz		95.4		dB
SINAD(4)(11)	VREFHI = 2.5 V, fin = 10 kHz		86.6		dB
ENOB(4)(11)	VREFHI = 2.5 V, fin = 10 kHz, single ADC(7)		14.1		bits
	VREFHI = 2.5 V, fin = 10 kHz, synchronous ADCs(8)		14.1
	VREFHI = 2.5 V, fin = 10 kHz, asynchronous ADCs(9)		Not supported
PSRR	VDDA = 3.3-V DC + 200 mV DC up to Sine at 1 kHz		77		dB
PSRR	VDDA = 3.3-V DC + 200 mV Sine at 800 kHz		74		dB
CMRR	DC to 1 MHz		60		dB
VREFHI input current			190		µA
ADC-to-ADC isolation(11)(5)(10)	VREFHI = 2.5 V, synchronous ADCs(8)	–2		2	LSBs
	VREFHI = 2.5 V, asynchronous ADCs(9)		Not supported

(1) See Section 4.8.1.1.2.

(2) Difference from conversion result 32768 when ADCINp = ADCINn = V_REFCM.

(3) No missing codes.

(4) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.

(5) Maximum DC code deviation due to operation of multiple ADCs simultaneously.

(6) Typical values are measured with V_REFHI = 2.5 V and V_REFLO = 0 V. Minimum and Maximum values are tested or characterized with V_REFHI = 2.5 V and V_REFLO = 0 V.

(7) One ADC operating while all other ADCs are idle.

(8) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.

(9) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.

(10) Value based on characterization.

(11) I/O activity is minimized on pins adjacent to ADC input and V_REFHI pins as part of best practices to reduce capacitive coupling and crosstalk.

Table 4-43 ADC Operating Conditions (12-Bit Single-Ended Mode)

over recommended operating conditions (unless otherwise noted)

	MIN	TYP	MAX	UNIT
ADCCLK (derived from PERx.SYSCLK)	5		50	MHz
Sample window duration (set by ACQPS and PERx.SYSCLK)(1)	75			ns
VREFHI	2.4	2.5 or 3.0	VDDA	V
VREFLO	VSSA	0	VSSA	V
VREFHI – VREFLO	2.4		VDDA	V
ADC input conversion range	VREFLO		VREFHI	V

(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.

NOTE

The ADC inputs should be kept below V_DDA + 0.3 V during operation. If an ADC input exceeds this level, the V_REF internal to the device may be disturbed, which can impact results for other ADC or DAC inputs using the same V_REF.

Table 4-44 ADC Characteristics (12-Bit Single-Ended Mode)

over recommended operating conditions (unless otherwise noted)⁽⁵⁾

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
ADC conversion cycles(1)		10.1		11	ADCCLKs
Power-up time				500	µs
Gain error		–5	±3	5	LSBs
Offset error		–4	±2	4	LSBs
Channel-to-channel gain error			±4		LSBs
Channel-to-channel offset error			±2		LSBs
ADC-to-ADC gain error	Identical VREFHI and VREFLO for all ADCs		±4		LSBs
ADC-to-ADC offset error	Identical VREFHI and VREFLO for all ADCs		±2		LSBs
DNL(2)		> –1	±0.5	1	LSBs
INL		–2	±1.0	2	LSBs
SNR(3)(10)	VREFHI = 2.5 V, fin = 100 kHz		68.8		dB
THD(3)(10)	VREFHI = 2.5 V, fin = 100 kHz		–78.4		dB
SFDR(3)(10)	VREFHI = 2.5 V, fin = 100 kHz		79.2		dB
SINAD(3)(10)	VREFHI = 2.5 V, fin = 100 kHz		68.4		dB
ENOB(3)(10)	VREFHI = 2.5 V, fin = 100 kHz, single ADC(6), all packages		11.1		bits
	VREFHI = 2.5 V, fin = 100 kHz, synchronous ADCs(7), all packages		11.1
	VREFHI = 2.5 V, fin = 100 kHz, asynchronous ADCs(8), 100-pin PZP package		Not supported
	VREFHI = 2.5 V, fin = 100 kHz, asynchronous ADCs(8), 176-pin PTP package		9.7
	VREFHI = 2.5 V, fin = 100 kHz, asynchronous ADCs(8), 337-ball ZWT package		10.9
PSRR	VDDA = 3.3-V DC + 200 mV DC up to Sine at 1 kHz		60		dB
PSRR	VDDA = 3.3-V DC + 200 mV Sine at 800 kHz		57		dB
ADC-to-ADC isolation(10)(4)(9)	VREFHI = 2.5 V, synchronous ADCs(7), all packages	–1		1	LSBs
	VREFHI = 2.5 V, asynchronous ADCs(8), 100-pin PZP package		Not supported
	VREFHI = 2.5 V, asynchronous ADCs(8), 176-pin PTP package	–9		9
	VREFHI = 2.5 V, asynchronous ADCs(8), 337-ball ZWT package	–2		2
VREFHI input current			130		µA

(1) See Section 4.8.1.1.2.

(2) No missing codes.

(3) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.

(4) Maximum DC code deviation due to operation of multiple ADCs simultaneously.

(5) Typical values are measured with V_REFHI = 2.5 V and V_REFLO = 0 V. Minimum and Maximum values are tested or characterized with V_REFHI = 2.5 V and V_REFLO = 0 V.

(6) One ADC operating while all other ADCs are idle.

(7) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.

(8) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.

(9) Value based on characterization.

(10) I/O activity is minimized on pins adjacent to ADC input and V_REFHI pins as part of best practices to reduce capacitive coupling and crosstalk.

Table 4-45 ADCEXTSOC Timing Requirements⁽¹⁾

			MIN	MAX	UNIT
tw(INT)	Pulse duration, INT input low/high	Synchronous	2tc(SYSCLK)		cycles
		With qualifier	tw(IQSW) + tw(SP) + 1tc(SYSCLK)		cycles

(1) For an explanation of the input qualifier parameters, see Table 4-24.

4.8.1.1.1 ADC Input Models

NOTE

ADC channels ADCINA0, ADCINA1, and ADCINB1 have a 50-kΩ pulldown resistor to V_SSA.

For single-ended operation, the ADC input characteristics are given by Table 4-46 and Figure 4-32.

Table 4-46 Single-Ended Input Model Parameters

	DESCRIPTION	VALUE (12-BIT MODE)
Cp	Parasitic input capacitance	See Table 4-48
Ron	Sampling switch resistance	425 Ω
Ch	Sampling capacitor	14.5 pF
Rs	Nominal source impedance	50 Ω

Figure 4-32 Single-Ended Input Model

For differential operation, the ADC input characteristics are given by Table 4-47 and Figure 4-33.

Table 4-47 Differential Input Model Parameters

	DESCRIPTION	VALUE (16-BIT MODE)
Cp	Parasitic input capacitance	See Table 4-48
Ron	Sampling switch resistance	700 Ω
Ch	Sampling capacitor	16.5 pF
Rs	Nominal source impedance	50 Ω

Figure 4-33 Differential Input Model

Table 4-48 shows the parasitic capacitance on each channel. Also, enabling a comparator adds approximately 1.4 pF of capacitance on positive comparator inputs and 2.5 pF of capacitance on negative comparator inputs.

Table 4-48 Per-Channel Parasitic Capacitance

ADC CHANNEL	Cp (pF)
	COMPARATOR DISABLED	COMPARATOR ENABLED
ADCINA0	12.9	N/A
ADCINA1	10.3	N/A
ADCINA2	5.9	7.3
ADCINA3	6.3	8.8
ADCINA4	5.9	7.3
ADCINA5	6.3	8.8
ADCINB0(1)	117.0	N/A
ADCINB1	10.6	N/A
ADCINB2	5.9	7.3
ADCINB3	6.2	8.7
ADCINB4	5.2	N/A
ADCINB5	5.1	N/A
ADCINC2	5.5	6.9
ADCINC3	5.8	8.3
ADCINC4	5.0	6.4
ADCINC5	5.3	7.8
ADCIND0	5.3	6.7
ADCIND1	5.7	8.2
ADCIND2	5.3	6.7
ADCIND3	5.6	8.1
ADCIND4	4.3	N/A
ADCIND5	4.3	N/A
ADCIN14	8.6	10.0
ADCIN15	9.0	11.5

(1) The increased capacitance is due to VDAC functionality.

These input models should be used along with actual signal source impedance to determine the acquisition window duration. See the Choosing an Acquisition Window Duration section of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual for more information.

The user should analyze the ADC input setting assuming worst-case initial conditions on C_h. This will require assuming that C_h could start the S+H window completely charged to V_REFHI or completely discharged to V_REFLO. When the ADC transitions from an odd-numbered channel to an even-numbered channel, or vice-versa, the actual initial voltage on C_h will be close to being completely discharged to V_REFLO. For even-to-even or odd-to-odd channel transitions, the initial voltage on C_h will be close to the voltage of the previously converted channel.

4.8.1.1.2 ADC Timing Diagrams

Table 4-49 shows the ADC timings in 12-bit mode (SYSCLK cycles). Table 4-50 shows the ADC timings in 16-bit mode. Figure 4-34 and Figure 4-35 show the ADC conversion timings for two SOCs given the following assumptions:

• SOC0 and SOC1 are configured to use the same trigger.
• No other SOCs are converting or pending when the trigger occurs.
• The round robin pointer is in a state that causes SOC0 to convert first.
• ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).

The following parameters are identified in the timing diagrams:

• The parameter t_SH is the duration of the S+H window. At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each SOC, so t_SH will not necessarily be the same for different SOCs.
• The parameter t_LAT is the time from the end of the S+H window until the ADC conversion results latch in the ADCRESULTx register. If the ADCRESULTx register is read before this time, the previous conversion results will be returned.
• The parameter t_EOC is the time from the end of the S+H window until the next ADC conversion S+H window can begin. In 16-bit mode, this will coincide with the latching of the conversion results, while in 12-bit mode, the subsequent sample can start before the conversion results are latched.
• The parameter t_INT is the time from the end of the S+H window until an ADCINT flag is set (if configured). If the INTPULSEPOS bit in the ADCCTL1 register is set, this will coincide with the conversion results being latched into the result register. If the bit is cleared, this will coincide with the end of the S+H window.

Table 4-49 ADC Timings in 12-Bit Mode (SYSCLK Cycles)

ADCCLK PRESCALE		SYSCLK CYCLES				ADCCLK CYCLES
ADCCTL2 [PRESCALE]	RATIO ADCCLK:SYSCLK	tEOC	tLAT	tINT(EARLY)	tINT(LATE)	tEOC
0	1	11	13	1	11	11.0
1	1.5	Invalid
2	2	21	23	1	21	10.5
3	2.5	26	28	1	26	10.4
4	3	31	34	1	31	10.3
5	3.5	36	39	1	36	10.3
6	4	41	44	1	41	10.3
7	4.5	46	49	1	46	10.2
8	5	51	55	1	51	10.2
9	5.5	56	60	1	56	10.2
10	6	61	65	1	61	10.2
11	6.5	66	70	1	66	10.2
12	7	71	76	1	71	10.1
13	7.5	76	81	1	76	10.1
14	8	81	86	1	81	10.1
15	8.5	86	91	1	86	10.1

Figure 4-34 ADC Timings for 12-Bit Mode

Table 4-50 ADC Timings in 16-Bit Mode

ADCCLK PRESCALE		SYSCLK CYCLES				ADCCLK CYCLES
ADCCTL2 [PRESCALE]	RATIO ADCCLK:SYSCLK	tEOC	tLAT	tINT(EARLY)	tINT(LATE)	tEOC
0	1	31	32	1	31	31.0
1	1.5	Invalid
2	2	60	61	1	60	30.0
3	2.5	75	75	1	75	30.0
4	3	90	91	1	90	30.0
5	3.5	104	106	1	104	29.7
6	4	119	120	1	119	29.8
7	4.5	134	134	1	134	29.8
8	5	149	150	1	149	29.8
9	5.5	163	165	1	163	29.6
10	6	178	179	1	178	29.7
11	6.5	193	193	1	193	29.7
12	7	208	209	1	208	29.7
13	7.5	222	224	1	222	29.6
14	8	237	238	1	237	29.6
15	8.5	252	252	1	252	29.6

Figure 4-35 ADC Timings for 16-Bit Mode

4.8.2 Comparator Subsystem (CMPSS)

Each CMPSS module includes two comparators, two internal voltage reference DACs (CMPSS DACs), two digital glitch filters, and one ramp generator. There are two inputs, CMPINxP and CMPINxN. Each of these inputs will be internally connected to an ADCIN pin. The CMPINxP pin is always connected to the positive input of the CMPSS comparators. CMPINxN can be used instead of the DAC output to drive the negative comparator inputs. There are two comparators, and therefore two outputs from the CMPSS module, which are connected to the input of a digital filter module before being passed on to the Comparator TRIP crossbar and either PWM modules or directly to a GPIO pin. Figure 4-36 shows the CMPSS connectivity on the 337-ball ZWT and 176-pin PTP packages. Figure 4-37 shows CMPSS connectivity on the 100-pin PZP package.

Figure 4-36 CMPSS Connectivity (337-Ball ZWT and 176-Pin PTP)

Figure 4-37 CMPSS Connectivity (100-Pin PZP)

4.8.2.1 CMPSS Electrical Data and Timing

Table 4-52 shows the comparator electrical characteristics. Figure 4-38 shows the CMPSS comparator input referred offset. Figure 4-39 shows the CMPSS comparator hysteresis.

Table 4-52 Comparator Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Power-up time (from COMPCTL[COMPDACE] to comparator ready)				10	µs
Comparator input (CMPINxx) range		0		VDDA	V
Input referred offset error		–20		20	mV
Hysteresis(1)	1x		12		CMPSS DAC LSB
	2x		24
	3x		36
	4x		48
Response time (delay from CMPINx input change to output on ePWM X-BAR or Output X-BAR)	Step response		21	60	ns
	Ramp response (1.65 V/µs)		26
	Ramp response (8.25 mV/µs)		30

(1) The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the CMPSS DAC reference voltage. Hysteresis is available for all comparator input source configurations.

NOTE

The CMPSS inputs must be kept below V_DDA + 0.3 V to ensure proper functional operation. If a CMPSS input exceeds this level, an internal blocking circuit will isolate the internal comparator from the external pin until the external pin voltage returns below V_DDA + 0.3 V. During this time, the internal comparator input will be floating and can decay below V_DDA within approximately 0.5 µs. After this time, the comparator could begin to output an incorrect result depending on the value of the other comparator input.

Figure 4-38 CMPSS Comparator Input Referred Offset

Figure 4-39 CMPSS Comparator Hysteresis

Table 4-53 shows the CMPSS DAC static electrical characteristics. Figure 4-40 shows the CMPSS DAC static offset. Figure 4-41 shows the CMPSS DAC static gain. Figure 4-42 shows the CMPSS DAC static linearity.

Table 4-53 CMPSS DAC Static Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
CMPSS DAC output range	Internal reference	0		VDDA	V
	External reference	0		VDAC
Static offset error(1)		–25		25	mV
Static gain error(1)		–2		2	% of FSR
Static DNL	Endpoint corrected	>–1		4	LSB
Static INL	Endpoint corrected	–16		16	LSB
Settling time	Settling to 1 LSB after full-scale output change			1	µs
Resolution			12		bits
CMPSS DAC output disturbance(2)	Error induced by comparator trip or CMPSS DAC code change within the same CMPSS module	–100		100	LSB
CMPSS DAC disturbance time(2)			200		ns
VDAC reference voltage	When VDAC is reference	2.4	2.5 or 3.0	VDDA	V
VDAC load(3)	When VDAC is reference		6		kΩ

(1) Includes comparator input referred errors.

(2) Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.

(3) Per active CMPSS module.

Figure 4-40 CMPSS DAC Static Offset

Figure 4-41 CMPSS DAC Static Gain

Figure 4-42 CMPSS DAC Static Linearity

4.8.3 Buffered Digital-to-Analog Converter (DAC)

The buffered DAC module consists of an internal reference DAC and an analog output buffer that is capable of driving an external load. An integrated pulldown resistor on the DAC output helps to provide a known pin voltage when the output buffer is disabled. This pulldown resistor cannot be disabled and remains as a passive component on the pin, even for other shared pin mux functions. Software writes to the DAC value register can take effect immediately or can be synchronized with PWMSYNC events.

Each buffered DAC has the following features:

• 12-bit programmable internal DAC
• Selectable reference voltage
• Pulldown resistor on output
• Ability to synchronize with PWMSYNC

The block diagram for the buffered DAC is shown in Figure 4-43.

Figure 4-43 DAC Module Block Diagram

4.8.3.1 Buffered DAC Electrical Data and Timing

Table 4-54 shows the buffered DAC electrical characteristics. Figure 4-44 shows the buffered DAC offset. Figure 4-45 shows the buffered DAC gain. Figure 4-46 shows the buffered DAC linearity.

Table 4-54 Buffered DAC Electrical Characteristics

over recommended operating conditions (unless otherwise noted)⁽¹⁾

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Power-up time (DACOUTEN to DAC output valid)				10	µs
Trimmed offset error	Midpoint	–10		10	mV
Gain error(2)		–2.5		2.5	% of FSR
DNL(3)	Endpoint corrected	> –1		1	LSB
INL	Endpoint corrected	–5		5	LSB
DACOUTx settling time	Settling to 2 LSBs after 0.3V-to-3V transition		2		µs
Resolution			12		bits
Voltage output range(4)		0.3		VDDA – 0.3	V
Capacitive load	Output drive capability			100	pF
Resistive load	Output drive capability	5			kΩ
RPD			50		kΩ
Reference voltage(5)	VDAC or VREFHI	2.4	2.5 or 3.0	VDDA	V
Reference load(6)	VDAC or VREFHI		170		kΩ
Output noise	Integrated noise from 100 Hz to 100 kHz		500		µVrms
	Noise density at 10 kHz		711		nVrms/√Hz
Glitch energy			1.5		V-ns
PSRR(7)	DC up to 1 kHz		70		dB
	100 kHz		30
SNR	1020 Hz		67		dB
THD	1020 Hz		–63		dB
SFDR	1020 Hz, including harmonics and spurs		66		dBc
	1020 Hz, including only spurs		104

(1) Typical values are measured with V_REFHI = 3.3 V and V_REFLO = 0 V unless otherwise noted. Minimum and Maximum values are tested or characterized with V_REFHI = 2.5 V and V_REFLO = 0 V.

(2) Gain error is calculated for linear output range.

(3) The DAC output is monotonic.

(4) This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear due to the buffer.

(5) For best PSRR performance, VDAC or V_REFHI should be less than V_DDA.

(6) Per active Buffered DAC module.

(7) V_REFHI = 3.2 V, V_DDA = 3.3 V DC + 100 mV Sine.

NOTE

The VDAC pin must be kept below V_DDA + 0.3 V to ensure proper functional operation. If the VDAC pin exceeds this level, a blocking circuit may activate, and the internal value of VDAC may float to 0 V internally, giving improper DAC output.

Figure 4-44 Buffered DAC Offset

Figure 4-45 Buffered DAC Gain

Figure 4-46 Buffered DAC Linearity

4.9.1 Enhanced Capture (eCAP)

The eCAP module can be used in systems where accurate timing of external events is important.

Applications for eCAP include:

• Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors

The eCAP module includes the following features:

• 4-event time-stamp registers (each 32 bits)
• Edge-polarity selection for up to four sequenced time-stamp capture events
• Interrupt on either of the four events
• Single shot capture of up to four event timestamps
• Continuous mode capture of timestamps in a four-deep circular buffer
• Absolute time-stamp capture
• Difference (Delta) mode time-stamp capture
• All of the above resources dedicated to a single input pin
• When not used in capture mode, the eCAP module can be configured as a single-channel PWM output (APWM).

The eCAP inputs connect to any GPIO input through the Input X-BAR. The APWM outputs connect to GPIO pins through the Output X-BAR to OUTPUTx positions in the GPIO mux. See Section 3.4.2 and Section 3.4.3.

Figure 4-47 shows the block diagram of an eCAP module.

Figure 4-47 eCAP Block Diagram

The eCAP module is clocked by PERx.SYSCLK.

The clock enable bits (ECAP1–ECAP6) in the PCLKCR3 register turn off the eCAP module individually (for low-power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.

4.9.2 Enhanced Pulse Width Modulator (ePWM)

The ePWM peripheral is a key element in controlling many of the power electronic systems found in both commercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module include complex waveform generation, dead-band generation, a flexible synchronization scheme, advanced trip-zone functionality, and global register reload capabilities.

Figure 4-48 shows the signal interconnections with the ePWM. Figure 4-49 shows the ePWM trip input connectivity.

A. These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.

Figure 4-48 ePWM Submodules and Critical Internal Signal Interconnects

Figure 4-49 ePWM Trip Input Connectivity

4.9.2.1 Control Peripherals Synchronization

The ePWM and eCAP synchronization chain on the device provides flexibility in partitioning the ePWM and eCAP modules between CPU1 and CPU2 and allows localized synchronization within the modules belonging to the same CPU. Like the other peripherals, the partitioning of the ePWM and eCAP modules needs to be done using the CPUSELx registers. Figure 4-50 shows the synchronization chain architecture.

Figure 4-50 Synchronization Chain Architecture

4.9.2.2 ePWM Electrical Data and Timing

Table 4-57 shows the PWM timing requirements and Table 4-58 shows the PWM switching characteristics.

Table 4-57 ePWM Timing Requirements⁽¹⁾

			MIN	MAX	UNIT
tw(SYNCIN)	Sync input pulse width	Asynchronous	2tc(EPWMCLK)		cycles
		Synchronous	2tc(EPWMCLK)		cycles
		With input qualifier	1tc(EPWMCLK) + tw(IQSW)		cycles

(1) For an explanation of the input qualifier parameters, see Table 4-24.

Table 4-58 ePWM Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		MIN	MAX	UNIT
tw(PWM)	Pulse duration, PWMx output high/low	20		ns
tw(SYNCOUT)	Sync output pulse width	8tc(SYSCLK)		cycles
td(TZ-PWM)	Delay time, trip input active to PWM forced high Delay time, trip input active to PWM forced low Delay time, trip input active to PWM Hi-Z		25	ns

4.9.2.2.1 Trip-Zone Input Timing

Table 4-59 shows the trip-zone input timing requirements. Figure 4-51 shows the PWM Hi-Z characteristics.

Table 4-59 Trip-Zone Input Timing Requirements⁽¹⁾

			MIN	MAX	UNIT
tw(TZ)	Pulse duration, TZx input low	Asynchronous	1tc(EPWMCLK)		cycles
		Synchronous	2tc(EPWMCLK)		cycles
		With input qualifier	1tc(EPWMCLK) + tw(IQSW)		cycles

(1) For an explanation of the input qualifier parameters, see Table 4-24.

A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12

B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.

Figure 4-51 PWM Hi-Z Characteristics

4.9.2.3 External ADC Start-of-Conversion Electrical Data and Timing

Table 4-60 shows the external ADC start-of-conversion switching characteristics. Figure 4-52 shows the ADCSOCAO or ADCSOCBO timing.

Table 4-60 External ADC Start-of-Conversion Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		MIN	MAX	UNIT
tw(ADCSOCL)	Pulse duration, ADCSOCxO low	32tc(SYSCLK)		cycles

Figure 4-52 ADCSOCAO or ADCSOCBO Timing

4.9.3 Enhanced Quadrature Encoder Pulse (eQEP)

The eQEP module interfaces directly with linear or rotary incremental encoders to obtain position, direction, and speed information from rotating machines used in high-performance motion and position-control systems.

Each eQEP peripheral comprises five major functional blocks:

• Quadrature Capture Unit (QCAP)
• Position Counter/Control Unit (PCCU)
• Quadrature Decoder Unit (QDU)
• Unit Time Base for speed and frequency measurement (UTIME)
• Watchdog timer for detecting stalls (QWDOG)

The eQEP peripherals are clocked by PERx.SYSCLK. Figure 4-53 shows the eQEP block diagram.

Figure 4-53 eQEP Block Diagram

4.9.4 High-Resolution Pulse Width Modulator (HRPWM)

The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a dedicated calibration delay line. For each ePWM module, there are two HR outputs:

• HR Duty and Deadband control on Channel A
• HR Duty and Deadband control on Channel B

The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:

• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge control for frequency/period modulation.
• Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B, phase, period and deadband registers of the ePWM module.

4.9.5 Sigma-Delta Filter Module (SDFM)

The SDFM is a four-channel digital filter designed specifically for current measurement and resolver position decoding in motor control applications. Each channel can receive an independent sigma-delta (ΣΔ) modulated bit stream. The bit streams are processed by four individually programmable digital decimation filters. The filter set includes a fast comparator for immediate digital threshold comparisons for overcurrent and undercurrent monitoring. Figure 4-54 shows a block diagram of the SDFMs.

SDFM features include:

• Eight external pins per SDFM module:
  • Four sigma-delta data input pins per SDFM module (SDx_Dy, where x = 1 to 2 and y = 1 to 4)
  • Four sigma-delta clock input pins per SDFM module (SDx_Cy, where x = 1 to 2 and y = 1 to 4)
• Four different configurable modulator clock modes:
  • Modulator clock rate equals modulator data rate
  • Modulator clock rate running at half the modulator data rate
  • Modulator data is Manchester encoded. Modulator clock not required.
  • Modulator clock rate is double that of modulator data rate
• Four independent configurable comparator units:
  • Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
  • Ability to detect over-value and under-value conditions
  • Comparator Over-Sampling Ratio (COSR) value for comparator programmable from 1 to 32
• Four independent configurable data filter units:
  • Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
  • Data filter Over-Sampling Ratio (DOSR) value for data filter unit programmable from 1 to 256
  • Ability to enable or disable individual filter module
  • Ability to synchronize all four independent filters of a SDFM module using the Master Filter Enable (MFE) bit or the PWM signals.
• Filter data can be 16-bit or 32-bit representation
• PWMs can be used to generate modulator clock for sigma-delta modulators

Figure 4-54 SDFM Block Diagram

4.9.5.1 SDFM Electrical Data and Timing

Table 4-64 shows the SDFM timing requirements. Figure 4-55 through Figure 4-58 show the SDFM timing diagrams.

Table 4-64 SDFM Timing Requirements

		MIN	MAX	UNIT
Mode 0
tc(SDC)M0	Cycle time, SDx_Cy	40	256 * SYSCLK period	ns
tw(SDCH)M0	Pulse duration, SDx_Cy high	10	tc(SDC)M0 – 10	ns
tsu(SDDV-SDCH)M0	Setup time, SDx_Dy valid before SDx_Cy goes high	5		ns
th(SDCH-SDD)M0	Hold time, SDx_Dy wait after SDx_Cy goes high	5		ns
Mode 1
tc(SDC)M1	Cycle time, SDx_Cy	80	256 * SYSCLK period	ns
tw(SDCH)M1	Pulse duration, SDx_Cy high	10	tc(SDC)M1 – 10	ns
tsu(SDDV-SDCL)M1	Setup time, SDx_Dy valid before SDx_Cy goes low	5		ns
tsu(SDDV-SDCH)M1	Setup time, SDx_Dy valid before SDx_Cy goes high	5		ns
th(SDCL-SDD)M1	Hold time, SDx_Dy wait after SDx_Cy goes low	5		ns
th(SDCH-SDD)M1	Hold time, SDx_Dy wait after SDx_Cy goes high	5		ns
Mode 2
tc(SDD)M2	Cycle time, SDx_Dy	8 * tc(SYSCLK)	20 * tc(SYSCLK)	ns
tw(SDDH)M2	Pulse duration, SDx_Dy high	10		ns
Mode 3
tc(SDC)M3	Cycle time, SDx_Cy	40	256 * SYSCLK period	ns
tw(SDCH)M3	Pulse duration, SDx_Cy high	10	tc(SDC)M3 – 5	ns
tsu(SDDV-SDCH)M3	Setup time, SDx_Dy valid before SDx_Cy goes high	5		ns
th(SDCH-SDD)M3	Hold time, SDx_Dy wait after SDx_Cy goes high	5		ns

Figure 4-55 SDFM Timing Diagram – Mode 0

Figure 4-56 SDFM Timing Diagram – Mode 1

Figure 4-57 SDFM Timing Diagram – Mode 2

Figure 4-58 SDFM Timing Diagram – Mode 3

4.10.1 Controller Area Network (CAN)

The CAN module implements the following features:

• Complies with ISO 11898-1 (Bosch® CAN protocol specification 2.0 A and B)
• Bit rates up to 1 Mbps
• Multiple clock sources
• 32 message objects, each with the following properties:
  • Configurable as receive or transmit
  • Configurable with standard or extended identifier
  • Programmable receive and identifier masks for each object
  • Supports data and remote frames
  • Holds 0 to 8 bytes of data
  • Parity-checked configuration and data RAM
• Individual identifier mask for each message object
• Programmable FIFO mode for receive message objects
• Programmable loop-back modes for self-test operation
• Suspend mode for debug support
• Software module reset
• Automatic bus on after Bus-Off state by a programmable 32-bit timer
• Message RAM parity check mechanism
• Two interrupt lines
• Global power down and wakeup support

4.10.2 Inter-Integrated Circuit (I2C)

The I2C module has the following features:

• Compliance with the Philips Semiconductors I²C-bus specification (version 2.1):
  • Support for 1-bit to 8-bit format transfers
  • 7-bit and 10-bit addressing modes
  • General call
  • START byte mode
  • Support for multiple master-transmitters and slave-receivers
  • Support for multiple slave-transmitters and master-receivers
  • Combined master transmit/receive and receive/transmit mode
  • Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
• One 16-byte receive FIFO and one 16-byte transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions:
  • Transmit-data ready
  • Receive-data ready
  • Register-access ready
  • No-acknowledgment received
  • Arbitration lost
  • Stop condition detected
  • Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability
• Free data format mode

Figure 4-59 shows how the I2C peripheral module interfaces within the device.

Figure 4-59 I2C Peripheral Module Interfaces

4.10.3 Multichannel Buffered Serial Port (McBSP)

The McBSP module has the following features:

• Compatible with McBSP in TMS320C28x and TMS320F28x DSP devices
• Full-duplex communication
• Double-buffered data registers that allow a continuous data stream
• Independent framing and clocking for receive and transmit
• External shift clock generation or an internal programmable frequency shift clock
• 8-bit data transfer mode can be configured to transmit with LSB or MSB first
• Programmable polarity for both frame synchronization and data clocks
• Highly programmable internal clock and frame generation
• Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected A/D and D/A devices
• Supports AC97, I2S, and SPI protocols
• McBSP clock rate,


where CLKSRG source could be LSPCLK, CLKX, or CLKR.

Figure 4-60 shows the block diagram of the McBSP module.

Figure 4-60 McBSP Block Diagram