SPRS880P December 2013 – February 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Table 7-10 shows a broad view of the peripheral and configuration register accessibility from each bus master. Peripherals can be individually assigned to the CPU1 or CPU2 subsystem (for example, ePWM can be assigned to CPU1 and eQEP assigned to CPU2). Peripherals within peripheral frames 1 or 2 will all be mapped to the respective secondary master as a group (if SPI is assigned to CPUx.DMA, then McBSP is also assigned to CPUx.DMA).
PERIPHERALS (BY BUS ACCESS TYPE) | CPU1.DMA | CPU1.CLA1 | CPU1 | CPU2 | CPU2.CLA1 | CPU2.DMA |
---|---|---|---|---|---|---|
Peripherals that can be assigned to CPU1 or CPU2 and have common selectable Secondary Masters | ||||||
Peripheral Frame 1: | Y | Y | Y | Y | Y | Y |
Peripheral Frame 1:
| Y | Y | Y | |||
Peripheral Frame 2:
| Y | Y | Y | Y | Y | Y |
Peripheral Frame 2:
| Y | Y | Y | |||
Peripherals that can be assigned to CPU1 or CPU2 subsystems | ||||||
SCI | Y | Y | ||||
I2C | Y | Y | ||||
CAN | Y | Y | ||||
ADC Configuration | Y | Y | Y | Y | ||
EMIF1 | Y | Y | Y | Y | ||
Peripherals and Device Configuration Registers only on CPU1 subsystem | ||||||
EMIF2 | Y | Y | ||||
USB | Y | |||||
Device Capability, Peripheral Reset, Peripheral CPU Select | Y | |||||
GPIO Pin Mapping and Configuration | Y | |||||
Analog System Control | Y | |||||
uPP Message RAMs | Y | Y | ||||
Reset Configuration | Y | |||||
Accessible by only one CPU at a time with Semaphore | ||||||
Clock and PLL Configuration | Y | Y | ||||
Peripherals and Registers with Unique Copies of Registers for each CPU and CLA Master(2) | ||||||
System Configuration (WD, NMIWD, LPM, Peripheral Clock Gating) | Y | Y | ||||
Flash Configuration(3) | Y | Y | ||||
CPU Timers | Y | Y | ||||
DMA and CLA Trigger Source Select | Y | Y | ||||
GPIO Data(4) | Y | Y | Y | Y | ||
ADC Results | Y | Y | Y | Y | Y | Y |