SPRS880P December 2013 – February 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
RAM TYPE | SIZE | FETCH
TIME (Cycles) |
READ TIME (Cycles) |
STORE
TIME (Cycles) |
BUS WIDTH | NUMBER OF BUSSES AVAILABLE(1) | NUMBER OF WAIT STATES | BURST ACCESS |
---|---|---|---|---|---|---|---|---|
GS RAM | 128KB | 2 | 2 | 1 | 16/32 bits | 4 | 0 | No |
LS RAM | 24KB | 2 | 2 | 1 | 16/32 bits | 2 | 0 | No |
M0 | 2KB | 2 | 2 | 1 | 16/32 bits | 1 | 0 | No |
M1 | 2KB | 2 | 2 | 1 | 16/32 bits | 1 | 0 | No |
CLA1 to CPU Message RAM | 256B | 2 | 2 | 1 | 16/32 bits | 2 | 0 | No |
CPU to CLA1 Message RAM | 256B | 2 | 2 | 1 | 16/32 bits | 2 | 0 | No |
CPU1 to CPU2 Message RAM | 2KB | 2 | 2 | 1 | 16/32 bits | 4 | 0 | No |
CPU2 to CPU1 Message RAM | 2KB | 2 | 2 | 1 | 16/32 bits | 4 | 0 | No |
RAM TYPE | SIZE | FETCH
TIME (Cycles) |
READ TIME (Cycles) |
STORE
TIME (Cycles) |
BUS WIDTH | NUMBER OF BUSSES AVAILABLE(1) | NUMBER OF WAIT STATES | BURST ACCESS |
---|---|---|---|---|---|---|---|---|
GS RAM | 128KB | 2 | 2 | 1 | 16/32 bits | 4 | 0 | No |
LS RAM | 24KB | 2 | 2 | 1 | 16/32 bits | 2 | 0 | No |
M0 | 2KB | 2 | 2 | 1 | 16/32 bits | 1 | 0 | No |
M1 | 2KB | 2 | 2 | 1 | 16/32 bits | 1 | 0 | No |
CLA1 to CPU Message RAM | 256B | 2 | 2 | 1 | 16/32 bits | 2 | 0 | No |
CPU to CLA1 Message RAM | 256B | 2 | 2 | 1 | 16/32 bits | 2 | 0 | No |
CPU1 to CPU2 Message RAM | 2KB | 2 | 2 | 1 | 16/32 bits | 4 | 0 | No |
CPU2 to CPU1 Message RAM | 2KB | 2 | 2 | 1 | 16/32 bits | 4 | 0 | No |