SPRS881K August   2014  – February 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Signal Descriptions
      1. 5.2.1 Signal Descriptions
    3. 5.3 Pins With Internal Pullup and Pulldown
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Input X-BAR
      3. 5.4.3 Output X-BAR and ePWM X-BAR
      4. 5.4.4 USB Pin Muxing
      5. 5.4.5 High-Speed SPI Pin Muxing
    5. 5.5 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 Device Current Consumption at 200-MHz SYSCLK
      2. 6.5.2 Current Consumption Graphs
      3. 6.5.3 Reducing Current Consumption
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics
      1. 6.7.1 ZWT Package
      2. 6.7.2 PTP Package
      3. 6.7.3 PZP Package
    8. 6.8  Thermal Design Considerations
    9. 6.9  System
      1. 6.9.1  Power Sequencing
        1. 6.9.1.1 Signal Pin Requirements
        2. 6.9.1.2 VDDIO, VDDA, VDD3VFL, and VDDOSC Requirements
        3. 6.9.1.3 VDD Requirements
        4. 6.9.1.4 Supply Ramp Rate
          1. 6.9.1.4.1 Supply Ramp Rate
        5. 6.9.1.5 Supply Supervision
      2. 6.9.2  Reset Timing
        1. 6.9.2.1 Reset Sources
        2. 6.9.2.2 Reset Electrical Data and Timing
          1. 6.9.2.2.1 Reset ( XRS) Timing Requirements
          2. 6.9.2.2.2 Reset ( XRS) Switching Characteristics
      3. 6.9.3  Clock Specifications
        1. 6.9.3.1 Clock Sources
        2. 6.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.9.3.2.1.1 Input Clock Frequency
            2. 6.9.3.2.1.2 X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
            3. 6.9.3.2.1.3 XTAL Oscillator Characteristics
            4. 6.9.3.2.1.4 X1 Timing Requirements
            5. 6.9.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.9.3.2.1.6 PLL Lock Times
          2. 6.9.3.2.2 Internal Clock Frequencies
            1. 6.9.3.2.2.1 Internal Clock Frequencies
          3. 6.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. 6.9.3.2.3.1 Output Clock Frequency
            2. 6.9.3.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        3. 6.9.3.3 Input Clocks and PLLs
        4. 6.9.3.4 XTAL Oscillator
          1. 6.9.3.4.1 Introduction
          2. 6.9.3.4.2 Overview
            1. 6.9.3.4.2.1 Electrical Oscillator
              1. 6.9.3.4.2.1.1 Modes of Operation
                1. 6.9.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.9.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.9.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.9.3.4.2.2 Quartz Crystal
          3. 6.9.3.4.3 Functional Operation
            1. 6.9.3.4.3.1 ESR – Effective Series Resistance
            2. 6.9.3.4.3.2 Rneg – Negative Resistance
            3. 6.9.3.4.3.3 Start-up Time
            4. 6.9.3.4.3.4 DL – Drive Level
          4. 6.9.3.4.4 How to Choose a Crystal
          5. 6.9.3.4.5 Testing
          6. 6.9.3.4.6 Common Problems and Debug Tips
          7. 6.9.3.4.7 Crystal Oscillator Specifications
            1. 6.9.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.9.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
        5. 6.9.3.5 Internal Oscillators
          1. 6.9.3.5.1 Internal Oscillator Electrical Characteristics
      4. 6.9.4  Flash Parameters
        1. 6.9.4.1 Flash Parameters
      5. 6.9.5  RAM Specifications
      6. 6.9.6  ROM Specifications
      7. 6.9.7  Emulation/JTAG
        1. 6.9.7.1 JTAG Electrical Data and Timing
          1. 6.9.7.1.1 JTAG Timing Requirements
          2. 6.9.7.1.2 JTAG Switching Characteristics
      8. 6.9.8  GPIO Electrical Data and Timing
        1. 6.9.8.1 GPIO - Output Timing
          1. 6.9.8.1.1 General-Purpose Output Switching Characteristics
        2. 6.9.8.2 GPIO - Input Timing
          1. 6.9.8.2.1 General-Purpose Input Timing Requirements
        3. 6.9.8.3 Sampling Window Width for Input Signals
      9. 6.9.9  Interrupts
        1. 6.9.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.9.9.1.1 External Interrupt Timing Requirements
          2. 6.9.9.1.2 External Interrupt Switching Characteristics
      10. 6.9.10 Low-Power Modes
        1. 6.9.10.1 Clock-Gating Low-Power Modes
        2. 6.9.10.2 Power-Gating Low-Power Modes
        3. 6.9.10.3 Low-Power Mode Wakeup Timing
          1. 6.9.10.3.1 IDLE Mode Timing Requirements
          2. 6.9.10.3.2 IDLE Mode Switching Characteristics
          3. 6.9.10.3.3 STANDBY Mode Timing Requirements
          4. 6.9.10.3.4 STANDBY Mode Switching Characteristics
          5. 6.9.10.3.5 HALT Mode Timing Requirements
          6. 6.9.10.3.6 HALT Mode Switching Characteristics
          7. 6.9.10.3.7 HIBERNATE Mode Timing Requirements
          8. 6.9.10.3.8 HIBERNATE Mode Switching Characteristics
      11. 6.9.11 External Memory Interface (EMIF)
        1. 6.9.11.1 Asynchronous Memory Support
        2. 6.9.11.2 Synchronous DRAM Support
        3. 6.9.11.3 EMIF Electrical Data and Timing
          1. 6.9.11.3.1 Asynchronous RAM
            1. 6.9.11.3.1.1 EMIF Asynchronous Memory Timing Requirements
            2. 6.9.11.3.1.2 EMIF Asynchronous Memory Switching Characteristics
          2. 6.9.11.3.2 Synchronous RAM
            1. 6.9.11.3.2.1 EMIF Synchronous Memory Timing Requirements
            2. 6.9.11.3.2.2 EMIF Synchronous Memory Switching Characteristics
    10. 6.10 Analog Peripherals
      1. 6.10.1 Analog-to-Digital Converter (ADC)
        1. 6.10.1.1 ADC Configurability
          1. 6.10.1.1.1 Signal Mode
        2. 6.10.1.2 ADC Electrical Data and Timing
          1. 6.10.1.2.1 ADC Operating Conditions (16-Bit Differential Mode)
          2. 6.10.1.2.2 ADC Characteristics (16-Bit Differential Mode)
          3. 6.10.1.2.3 ADC Operating Conditions (12-Bit Single-Ended Mode)
          4. 6.10.1.2.4 ADC Characteristics (12-Bit Single-Ended Mode)
          5. 6.10.1.2.5 ADCEXTSOC Timing Requirements
          6. 6.10.1.2.6 ADC Input Models
            1. 6.10.1.2.6.1 Differential Input Model Parameters
            2. 6.10.1.2.6.2 Single-Ended Input Model Parameters
          7. 6.10.1.2.7 ADC Timing Diagrams
            1. 6.10.1.2.7.1 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
            2. 6.10.1.2.7.2 ADC Timings in 16-Bit Mode
        3. 6.10.1.3 Temperature Sensor Electrical Data and Timing
          1. 6.10.1.3.1 Temperature Sensor Electrical Characteristics
      2. 6.10.2 Comparator Subsystem (CMPSS)
        1. 6.10.2.1 CMPSS Electrical Data and Timing
          1. 6.10.2.1.1 Comparator Electrical Characteristics
          2. 6.10.2.1.2 CMPSS DAC Static Electrical Characteristics
      3. 6.10.3 Buffered Digital-to-Analog Converter (DAC)
        1. 6.10.3.1 Buffered DAC Electrical Data and Timing
          1. 6.10.3.1.1 Buffered DAC Electrical Characteristics
        2. 6.10.3.2 CMPSS DAC Dynamic Error
    11. 6.11 Control Peripherals
      1. 6.11.1 Enhanced Capture (eCAP)
        1. 6.11.1.1 eCAP Electrical Data and Timing
          1. 6.11.1.1.1 eCAP Timing Requirement
          2. 6.11.1.1.2 eCAP Switching Characteristics
      2. 6.11.2 Enhanced Pulse Width Modulator (ePWM)
        1. 6.11.2.1 Control Peripherals Synchronization
        2. 6.11.2.2 ePWM Electrical Data and Timing
          1. 6.11.2.2.1 ePWM Timing Requirements
          2. 6.11.2.2.2 ePWM Switching Characteristics
          3. 6.11.2.2.3 Trip-Zone Input Timing
            1. 6.11.2.2.3.1 Trip-Zone Input Timing Requirements
        3. 6.11.2.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 6.11.2.3.1 External ADC Start-of-Conversion Switching Characteristics
      3. 6.11.3 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.11.3.1 eQEP Electrical Data and Timing
          1. 6.11.3.1.1 eQEP Timing Requirements
          2. 6.11.3.1.2 eQEP Switching Characteristics
      4. 6.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.11.4.1 HRPWM Electrical Data and Timing
          1. 6.11.4.1.1 High-Resolution PWM Timing Requirements
          2. 6.11.4.1.2 High-Resolution PWM Characteristics
      5. 6.11.5 Sigma-Delta Filter Module (SDFM)
        1. 6.11.5.1 SDFM Electrical Data and Timing (Using ASYNC)
          1. 6.11.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
        2. 6.11.5.2 SDFM Electrical Data and Timing (Using 3-Sample GPIO Input Qualification)
          1. 6.11.5.2.1 SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window) Option
    12. 6.12 Communications Peripherals
      1. 6.12.1 Controller Area Network (CAN)
      2. 6.12.2 Inter-Integrated Circuit (I2C)
        1. 6.12.2.1 I2C Electrical Data and Timing
          1. 6.12.2.1.1 I2C Timing Requirements
          2. 6.12.2.1.2 I2C Switching Characteristics
          3. 6.12.2.1.3 I2C Timing Diagram
      3. 6.12.3 Multichannel Buffered Serial Port (McBSP)
        1. 6.12.3.1 McBSP Electrical Data and Timing
          1. 6.12.3.1.1 McBSP Transmit and Receive Timing
            1. 6.12.3.1.1.1 McBSP Timing Requirements
            2. 6.12.3.1.1.2 McBSP Switching Characteristics
          2. 6.12.3.1.2 McBSP as SPI Master or Slave Timing
            1. 6.12.3.1.2.1 McBSP as SPI Master Timing Requirements
            2. 6.12.3.1.2.2 McBSP as SPI Master Switching Characteristics
            3. 6.12.3.1.2.3 McBSP as SPI Slave Timing Requirements
            4. 6.12.3.1.2.4 McBSP as SPI Slave Switching Characteristics
      4. 6.12.4 Serial Communications Interface (SCI)
      5. 6.12.5 Serial Peripheral Interface (SPI)
        1. 6.12.5.1 SPI Electrical Data and Timing
          1. 6.12.5.1.1 SPI Master Mode Timings
            1. 6.12.5.1.1.1 SPI Master Mode Timing Requirements
            2. 6.12.5.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            3. 6.12.5.1.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
          2. 6.12.5.1.2 SPI Slave Mode Timings
            1. 6.12.5.1.2.1 SPI Slave Mode Timing Requirements
            2. 6.12.5.1.2.2 SPI Slave Mode Switching Characteristics
      6. 6.12.6 Universal Serial Bus (USB) Controller
        1. 6.12.6.1 USB Electrical Data and Timing
          1. 6.12.6.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.12.6.1.2 USB Output Ports DP and DM Switching Characteristics
      7. 6.12.7 Universal Parallel Port (uPP) Interface
        1. 6.12.7.1 uPP Electrical Data and Timing
          1. 6.12.7.1.1 uPP Timing Requirements
          2. 6.12.7.1.2 uPP Switching Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 C28x Memory Map
      2. 7.3.2 Flash Memory Map
      3. 7.3.3 EMIF Chip Select Memory Map
      4. 7.3.4 Peripheral Registers Memory Map
      5. 7.3.5 Memory Types
        1. 7.3.5.1 Dedicated RAM (Mx and Dx RAM)
        2. 7.3.5.2 Local Shared RAM (LSx RAM)
        3. 7.3.5.3 Global Shared RAM (GSx RAM)
        4. 7.3.5.4 CLA Message RAM (CLA MSGRAM)
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit
      2. 7.6.2 Trigonometric Math Unit
      3. 7.6.3 Viterbi, Complex Math, and CRC Unit II
    7. 7.7  Control Law Accelerator
    8. 7.8  Direct Memory Access
    9. 7.9  Boot ROM and Peripheral Booting
      1. 7.9.1 EMU Boot or Emulation Boot
      2. 7.9.2 WAIT Boot Mode
      3. 7.9.3 Get Mode
      4. 7.9.4 Peripheral Pins Used by Bootloaders
    10. 7.10 Dual Code Security Module
    11. 7.11 Timers
    12. 7.12 Nonmaskable Interrupt With Watchdog Timer (NMIWD)
    13. 7.13 Watchdog
    14. 7.14 Configurable Logic Block (CLB)
    15. 7.15 Functional Safety
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 Servo Drive Control Module
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Servo Drive Control Module Resources
        2. 8.3.1.2 Solar Micro Inverter
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 Solar Micro Inverter Resources
        3. 8.3.1.3 On-Board Charger (OBC)
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 OBC Resources
        4. 8.3.1.4 EV Charging Station Power Module
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 EV Charging Station Power Module Resources
        5. 8.3.1.5 High-Voltage Traction Inverter
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 High-Voltage Traction Inverter Resources
        6. 8.3.1.6 Single-Phase Online UPS
          1. 8.3.1.6.1 System Block Diagram
          2. 8.3.1.6.2 Single-Phase Online UPS Resources
  10. 9 Device and Documentation Support
    1. 9.1 Device and Development Support Tool Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZP|100
  • ZWT|337
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2 Key Device Features

Table 8-1 Key Device Features
MODULE FEATURE SYSTEM BENEFIT
C28x PROCESSING
Real-time control CPUs

Up to 400 MIPS

One C28x cores: 200 MIPS

One CLA cores: 200 MIPS

Flash: Up to 1 MB

RAM : Up to 164 KB

64-bit Floating Point Unit (FPU64)

Trigonometric Math Unit (TMU)

CRC engine and instructions (VCRC)

TI’s two 32-bit C28x DSP cores, provides 400 MHz of signal-processing performance for floating- or fixed-point code running from either on-chip flash or SRAM

Provides 400 MHz of signal-processing performance for floating- or fixed-point code running from either on-chip flash or SRAM.

CLA: Allows user to execute time-critical control loops concurrently with main CPU

FPU64: Native hardware support for IEEE-754 double-precision floating-point operations

TMU: Accelerators used to speed up execution of trigonometric and arithmetic operations for faster computation (such as PLL and DQ transform) optimized for control applications. Helps in achieving faster control loops, resulting in higher efficiency and better component sizing.

Special instructions to support nonlinear PID control algorithms

VCRC: Provides a straightforward method for verifying data integrity over large data blocks, communication packets, or code sections.

See Real-time Benchmarks Showcasing C2000™ControlMCU's Optimized Signal Chain.
SENSING
Analog-to-Digital Converter (ADC) (configurable 12-bit or 16-bit)

Four ADC modules

16-bit mode: (1.1 MSPS)

Differential mode : Up to 12 channels

12-bit mode: (3.5 MSPS)

Single-ended mode: Up to 24 channels

ADC provides precise and concurrent sampling of all three-phase currents and DC bus with zero jitter.

ADC post-processing – On-chip hardware reduces ADC ISR complexity and shortens current loop cycles.

More ADCs help in multiphase applications. Provide better effective MSPS (oversampling) and typical ENOB for better control-loop performance.

Comparator Subsystem (CMPSS) CMPSS

8 windowed comparators

Three 12-bit DACs

60-ns detection to trip time

DAC ramp generation

Low DAC output on external pin

Digital filters

Slope compensation

System protection without false alarms:

Comparator Subsystem (CMPSS) modules are useful for applications such as peak-current mode control, switched-mode power, power factor correction, and voltage trip monitoring.

PWM trip-triggering and removal of unwanted noise are easy with blanking window and filtering features provided with the analog comparator subsystems.

Provides better control accuracy. No need for further CPU configuration to control the PWM with the comparator and 12-bit DAC (CMPSS).

Enables protection and control using the same pin.
Sigma Delta Filter Module (SDFM)

Up to 8 independently configurable digital comparator filter channels

Up to 8 independently configurable digital data filter channels

Enables galvanic isolation with reinforced delta sigma modulators.

SDFMs interface with external delta sigma modulator ADCs, which is ideal for signals that may require isolation.

Comparator filter supports overcurrent and undercurrent protection but tripping the PWM without CPU intervention

Digital data filter provides higher ENOBs for better control-loop performance
Enhanced Quadrature Encoder Pulse (eQEP) 3 eQEP modules Used for direct interface with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine used in a high-performance motion and position-control system. Also can be used in other applications to count input pulses from an external device (such as a sensor).
Enhanced Capture (eCAP)

7 eCAP modules

Measures elapsed time between events (up to 4 time-stamped events).

Connects to any GPIO through the input X-BAR.

When not used in capture mode, the eCAP module can be configured as a single-channel PWM output (APWM).

Applications for eCAP include:

Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall sensors)

Elapsed time measurements between position sensor pulses

Period and duty-cycle measurements of pulse train signals

Decoding current or voltage amplitude derived from duty-cycle encoded current/voltage sensors
ACTUATION
Enhanced Pulse Width Modulation (ePWM)/High-Resolution Pulse Width Modulation (HRPWM)

Up to 24 ePWM channels

Ability to generate high-side/low-side PWMs with deadband

Supports Valley switching (ability to switch PWM output at valley point) and features like blanking window

Flexible PWM waveform generation with best power topology coverage.

Shadowed Dead band itself and shadowed action qualifier enable adaptive PWM generation and protection for improved control accuracy and reduced power loss.

Enables improvement in Power Factor (PF) and Total Harmonic Distortion (THD), which is especially relevant in Power Factor Correction (PFC) applications. Improves light load efficiency.

HRPWM capability:

16 channels provide high-resolution capability (150 ps)

Provides 150-ps steps for duty cycle, period, deadband, and phase offsets for 99% greater precision

Beneficial for accurate control and enables better-performance high-frequency power conversion.

Achieves cleaner waveforms and avoids oscillations/limit cycle at output.

One-shot and global reload feature

Critical for variable-frequency and multiphase DC-DC applications and helps in attaining high-frequency control loops (>2 MHz).

Enables control of interleaved LLC topologies at high frequencies

Independent PWM action on a Cycle-by-Cycle (CBC) trip event and an One-Shot Trip (OST) trip event

 Provides cycle-by-cycle protection and complete shutoff of PWM under fault condition. Helps implement multiphase PFC or DC-DC control.
Load on SYNC (support for shadow-to-active load on a SYNC event) Enables variable-frequency applications (allows LLC control in power conversion).
Ability to shut down the PWMs without software intervention (no ISR latency) Fast protection under fault condition
Delayed Trip Functionality Helps implement the deadband with Peak Current Mode Control (PCMC) Phase-Shifted Full Bride (PSFB) DC-DC easily without occupying much CPU resources (even on trigger events based on comparator, trip, or sync-in events).
Dead band Generator (DB) submodule Prevents simultaneous ON conditions of High- and Low-side gates by adding programmable delay to rising (RED) and falling (FED) PWM signal edges.
Flexible PWM Phase Relationships and Timer Synchronization Each ePWM module can be synchronized with other ePWM modules or other peripherals. Keeps PWM edges perfectly in synchronization with certain events.

Supports flexible ADC scheduling with specific sampling window in synchronization with power device switching.
CONNECTIVITY
Serial Peripheral Interface (SPI) 3 high-speed SPI port Supports 50 MHz
Serial Communication Interface (SCI) 4 SCI (UART) modules Interfaces with controllers
Controller Area Network (CAN/DCAN) 2 DCAN module Provides compatibility with classic CAN modules
Inter-Integrated Circuit (I2C) 2 I2C modules Interfaces with external EEPROMs, sensors, or controllers
Multichannel Buffered Serial Port (McBSP) Up to 2 McBSP modules Interface to high-speed external ADC or additional SPI peripheral
External Memory Interfaces (EMIFs) with ASRAM and SDRAM support Two EMIF modules Interface with External ASRAM and SDRAM
OTHER SYSTEM FEATURES
Configurable Logic Block (CLB)

Collection of configurable blocks that can be inter-connected using software to implement custom digital logic functions

User customized PWM protection features, custom logic to off-load complex algorithms/state machines, custom peripherals, and used to implement absolute encoders used in servo drives

User also used for protection of multilevel inverter/PFC or multilevel DC-DC

Provides the ability to build logic around existing IPs like ETPWM, ECAP, QEP and GPIOs.

Enables development of unique IP such as PWM Safety modules, Encoder engines, etc.
Security enhancers

Dual-zone Code Security Module (DCSM)

Secure Boot

JTAGLOCK

BackGround CRC (BGCRC)

Generic CRC (GCRC)

Watchdog

Write Protection on Register

Missing Clock Detection Logic (MCD)

Error Correction Code (ECC) and parity

DCSM: Prevents duplication and reverse-engineering of proprietary code

Secure Boot: Uses AES128 CMAC algorithm to ensure code that runs on the device is authentic

JTAGLOCK: Ability to block emulation of the device

BGCRC: Checks memory integrity with no CPU overhead or system performance impact

GCRC: Designated Connectivity Manager module for computing the CRC value on a configurable block of memory

Watchdog: Generates reset if CPU gets stuck in endless loops of execution

Write Protection on Registers:

LOCK protection on system configuration registers

Protection against spurious CPU writes

MCD: Automatic clock failure detection

ECC and parity: Single-bit error correction and double-bit error detection
Crossbars (XBARs)

Provides flexibility to connect device inputs, outputs, and internal resources in a variety of configurations.

• Input X-BAR

• Output X-BAR

• ePWM X-BAR

• CLB Input X-BAR

• CLB Output X-BAR

• CLB X-BAR

Enhances hardware design versatility:

Input X-BAR: Routes signals from any GPIO to multiple IP blocks within the chip

Output XBAR: Routes internal signals onto designated GPIO pins

ePWM X-BAR: Routes internal signals from various IP blocks to ePWM

CLB Input X-BAR: Allows user to route signals directly from any GPIO to Configurable Logic Block (CLB)

CLB Output X-BAR: Allows user to bring signals from CLB tiles to designated GPIO pins

CLB X-BAR: Allows user to bring signals from various IP blocks to CLB
Direct Memory Access (DMA) controller 6-channels The direct memory access (DMA) module provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up CPU bandwidth for other system functions.
USB Useful for system datalogging and boot to USB for updating on-chip flash