SPRS880P December 2013 – February 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
NO. | PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
CLOCK | ||||||
M33 | tc(CLKG) | Cycle time, CLKG(1) (n * tc(LSPCLK)) | 40 | ns | ||
P | Half CLKG cycle; 0.5 * tc(CLKG) | 20 | ns | |||
n | LSPCLK to CLKG divider | 2 | ns | |||
CLKSTP = 10b, CLKXP = 0 | ||||||
M24 | th(CKXL-FXL) | Hold time, FSX high after CLKX low | 2P – 6 | ns | ||
M25 | td(FXL-CKXH) | Delay time, FSX low to CLKX high | P – 6 | ns | ||
M26 | td(CLKXH-DXV) | Delay time, CLKX high to DX valid [check clock polarity and add to timing diagram] | –4 | 6 | ns | |
M28 | tdis(FXH-DXHZ) | Disable time, DX high impedance following last data bit from CLKX low [redefine timing diagram] | P – 8 | ns | ||
M29 | td(FXL-DXV) | Delay time, FSX low to DX valid | P – 3 | P + 6 | ns | |
CLKSTP = 11b, CLKXP = 0 | ||||||
M34 | th(CKXL-FXH) | Hold time, FSX high after CLKX low | P – 6 | ns | ||
M35 | td(FXL-CKXH) | Delay time, FSX low to CLKX high | P – 6 | ns | ||
M36 | td(CLKXL-DXV) | Delay time, CLKX low to DX valid [check clock polarity and add to timing diagram] | –4 | 6 | ns | |
M37 | tdis(CKXL-DXHZ) | Disable time, DX high impedance following last data bit from CLKX low | P – 6 | ns | ||
M38 | td(FXL-DXV) | Delay time, FSX low to DX valid | –2 | 1 | ns | |
CLKSTP = 10b, CLKXP = 1 | ||||||
M43 | th(CKXH-FXH) | Hold time, FSX high after CLKX high | 2P – 6 | ns | ||
M44 | td(FXL-CKXL) | Delay time, FSX low to CLKX low | P – 6 | ns | ||
M45 | td(CLKXL-DXV) | Delay time, CLKX low to DX valid [check clock polarity and add to timing diagram] | –4 | 6 | ns | |
M47 | tdis(FXH-DXHZ) | Disable time, DX high impedance following last data bit from CLKX low [redefine timing diagram] | P – 6 | ns | ||
M48 | td(FXL-DXV) | Delay time, FSX low to DX valid | –2 | 1 | ns | |
CLKSTP = 11b, CLKXP = 1 | ||||||
M53 | th(CKXH-FXH) | Hold time, FSX high after CLKX high | P – 6 | ns | ||
M54 | td(FXL-CKXL) | Delay time, FSX low to CLKX low | 2P – 6 | ns | ||
M55 | td(CLKXH-DXV) | Delay time, CLKX high to DX valid | –4 | 6 | ns | |
M56 | tdis(CKXH-DXHZ) | Disable time, DX high impedance following last data bit from CLKX high | P – 8 | ns | ||
M57 | td(FXL-DXV) | Delay time, FSX low to DX valid | –2 | 1 | ns |