SPRS880P December 2013 – February 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
TERMINAL | I/O/Z(1) | DESCRIPTION | ||||
---|---|---|---|---|---|---|
NAME | MUX POSITION | ZWT BALL NO. | PTP PIN NO. | PZP PIN NO. | ||
ADC, DAC, AND COMPARATOR SIGNALS | ||||||
VREFHIA | V1 | 37 | 19 | I | ADC-A high reference. This voltage must be driven into the pin from external circuitry. Place at least a 1-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIA and VREFLOA pins. NOTE: Do not load this pin externally. | |
VREFHIB | W5 | 53 | 37 | I | ADC-B high reference. This voltage must be driven into the pin from external circuitry. Place at least a 1-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIB and VREFLOB pins. NOTE: Do not load this pin externally. | |
VREFHIC | R1 | 35 | – | I | ADC-C high reference. This voltage must be driven into the pin from external circuitry. Place at least a 1-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIC and VREFLOC pins. NOTE: Do not load this pin externally. | |
VREFHID | V5 | 55 | – | I | ADC-D high reference. This voltage must be driven into the pin from external circuitry. Place at least a 1-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHID and VREFLOD pins. NOTE: Do not load this pin externally. | |
VREFLOA | R2 | 33 | 17 | I | ADC-A low reference. On the PZP package, pin 17 is double-bonded to VSSA and VREFLOA. On the PZP package, pin 17 must be connected to VSSA on the system board. | |
VREFLOB | V6 | 50 | 34 | I | ADC-B low reference | |
VREFLOC | P2 | 32 | – | I | ADC-C low reference | |
VREFLOD | W6 | 51 | – | I | ADC-D low reference | |
ADCIN14 | T4 | 44 | 26 | I | Input 14 to all ADCs. This pin can be used as a general-purpose ADCIN pin or it can be used to calibrate all ADCs together (either single-ended or differential) from an external reference. | |
CMPIN4P | I | Comparator 4 positive input | ||||
ADCIN15 | U4 | 45 | 27 | I | Input 15 to all ADCs. This pin can be used as a general-purpose ADCIN pin or it can be used to calibrate all ADCs together (either single-ended or differential) from an external reference. | |
CMPIN4N | I | Comparator 4 negative input | ||||
ADCINA0 | U1 | 43 | 25 | I | ADC-A input 0. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled. | |
DACOUTA | O | DAC-A output | ||||
ADCINA1 | T1 | 42 | 24 | I | ADC-A input 1. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled. | |
DACOUTB | O | DAC-B output | ||||
ADCINA2 | U2 | 41 | 23 | I | ADC-A input 2 | |
CMPIN1P | I | Comparator 1 positive input | ||||
ADCINA3 | T2 | 40 | 22 | I | ADC-A input 3 | |
CMPIN1N | I | Comparator 1 negative input | ||||
ADCINA4 | U3 | 39 | 21 | I | ADC-A input 4 | |
CMPIN2P | I | Comparator 2 positive input | ||||
ADCINA5 | T3 | 38 | 20 | I | ADC-A input 5 | |
CMPIN2N | I | Comparator 2 negative input | ||||
ADCINB0 | V2 | 46 | 28 | I | ADC-B input 0. There is a 100-pF capacitor to VSSA on this pin in both ADC input or DAC reference mode which cannot be disabled. If this pin is being used as a reference for the on-chip DACs, place at least a 1-µF capacitor on this pin. | |
VDAC | I | Optional external reference voltage for on-chip DACs. There is a 100-pF capacitor to VSSA on this pin in both ADC input or DAC reference mode which cannot be disabled. If this pin is being used as a reference for the on-chip DACs, place at least a 1-µF capacitor on this pin. | ||||
ADCINB1 | W2 | 47 | 29 | I | ADC-B input 1. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled. | |
DACOUTC | O | DAC-C output | ||||
ADCINB2 | V3 | 48 | 30 | I | ADC-B input 2 | |
CMPIN3P | I | Comparator 3 positive input | ||||
ADCINB3 | W3 | 49 | 31 | I | ADC-B input 3 | |
CMPIN3N | I | Comparator 3 negative input | ||||
ADCINB4 | V4 | – | 32 | I | ADC-B input 4 | |
ADCINB5 | W4 | – | 33 | I | ADC-B input 5 | |
ADCINC2 | R3 | 31 | – | I | ADC-C input 2 | |
CMPIN6P | I | Comparator 6 positive input | ||||
ADCINC3 | P3 | 30 | – | I | ADC-C input 3 | |
CMPIN6N | I | Comparator 6 negative input | ||||
ADCINC4 | R4 | 29 | – | I | ADC-C input 4 | |
CMPIN5P | I | Comparator 5 positive input | ||||
ADCINC5 | P4 | – | – | I | ADC-C input 5 | |
CMPIN5N | I | Comparator 5 negative input | ||||
ADCIND0 | T5 | 56 | – | I | ADC-D input 0 | |
CMPIN7P | I | Comparator 7 positive input | ||||
ADCIND1 | U5 | 57 | – | I | ADC-D input 1 | |
CMPIN7N | I | Comparator 7 negative input | ||||
ADCIND2 | T6 | 58 | – | I | ADC-D input 2 | |
CMPIN8P | I | Comparator 8 positive input | ||||
ADCIND3 | U6 | 59 | – | I | ADC-D input 3 | |
CMPIN8N | I | Comparator 8 negative input | ||||
ADCIND4 | T7 | 60 | – | I | ADC-D input 4 | |
ADCIND5 | U7 | – | – | I | ADC-D input 5 | |
GPIO AND PERIPHERAL SIGNALS | ||||||
GPIO0 | 0, 4, 8, 12 | C8 | 160 | – | I/O | General-purpose input/output 0 |
EPWM1A | 1 | O | Enhanced PWM1 output A (HRPWM-capable) | |||
SDAA | 6 | I/OD | I2C-A data open-drain bidirectional port | |||
GPIO1 | 0, 4, 8, 12 | D8 | 161 | – | I/O | General-purpose input/output 1 |
EPWM1B | 1 | O | Enhanced PWM1 output B (HRPWM-capable) | |||
MFSRB | 3 | I/O | McBSP-B receive frame synch | |||
SCLA | 6 | I/OD | I2C-A clock open-drain bidirectional port | |||
GPIO2 | 0, 4, 8, 12 | A7 | 162 | 91 | I/O | General-purpose input/output 2 |
EPWM2A | 1 | O | Enhanced PWM2 output A (HRPWM-capable) | |||
OUTPUTXBAR1 | 5 | O | Output 1 of the output XBAR | |||
SDAB | 6 | I/OD | I2C-B data open-drain bidirectional port | |||
GPIO3 | 0, 4, 8, 12 | B7 | 163 | 92 | I/O | General-purpose input/output 3 |
EPWM2B | 1 | O | Enhanced PWM2 output B (HRPWM-capable) | |||
OUTPUTXBAR2 | 2 | O | Output 2 of the output XBAR | |||
MCLKRB | 3 | I/O | McBSP-B receive clock | |||
OUTPUTXBAR2 | 5 | O | Output 2 of the output XBAR | |||
SCLB | 6 | I/OD | I2C-B clock open-drain bidirectional port | |||
GPIO4 | 0, 4, 8, 12 | C7 | 164 | 93 | I/O | General-purpose input/output 4 |
EPWM3A | 1 | O | Enhanced PWM3 output A (HRPWM-capable) | |||
OUTPUTXBAR3 | 5 | O | Output 3 of the output XBAR | |||
CANTXA | 6 | O | CAN-A transmit | |||
GPIO5 | 0, 4, 8, 12 | D7 | 165 | – | I/O | General-purpose input/output 5 |
EPWM3B | 1 | O | Enhanced PWM3 output B (HRPWM-capable) | |||
MFSRA | 2 | I/O | McBSP-A receive frame synch | |||
OUTPUTXBAR3 | 3 | O | Output 3 of the output XBAR | |||
CANRXA | 6 | I | CAN-A receive | |||
GPIO6 | 0, 4, 8, 12 | A6 | 166 | – | I/O | General-purpose input/output 6 |
EPWM4A | 1 | O | Enhanced PWM4 output A (HRPWM-capable) | |||
OUTPUTXBAR4 | 2 | O | Output 4 of the output XBAR | |||
EXTSYNCOUT | 3 | O | External ePWM synch pulse output | |||
EQEP3A | 5 | I | Enhanced QEP3 input A | |||
CANTXB | 6 | O | CAN-B transmit | |||
GPIO7 | 0, 4, 8, 12 | B6 | 167 | – | I/O | General-purpose input/output 7 |
EPWM4B | 1 | O | Enhanced PWM4 output B (HRPWM-capable) | |||
MCLKRA | 2 | I/O | McBSP-A receive clock | |||
OUTPUTXBAR5 | 3 | O | Output 5 of the output XBAR | |||
EQEP3B | 5 | I | Enhanced QEP3 input B | |||
CANRXB | 6 | I | CAN-B receive | |||
GPIO8 | 0, 4, 8, 12 | G2 | 18 | – | I/O | General-purpose input/output 8 |
EPWM5A | 1 | O | Enhanced PWM5 output A (HRPWM-capable) | |||
CANTXB | 2 | O | CAN-B transmit | |||
ADCSOCAO | 3 | O | ADC start-of-conversion A output for external ADC | |||
EQEP3S | 5 | I/O | Enhanced QEP3 strobe | |||
SCITXDA | 6 | O | SCI-A transmit data | |||
GPIO9 | 0, 4, 8, 12 | G3 | 19 | – | I/O | General-purpose input/output 9 |
EPWM5B | 1 | O | Enhanced PWM5 output B (HRPWM-capable) | |||
SCITXDB | 2 | O | SCI-B transmit data | |||
OUTPUTXBAR6 | 3 | O | Output 6 of the output XBAR | |||
EQEP3I | 5 | I/O | Enhanced QEP3 index | |||
SCIRXDA | 6 | I | SCI-A receive data | |||
GPIO10 | 0, 4, 8, 12 | B2 | 1 | 100 | I/O | General-purpose input/output 10 |
EPWM6A | 1 | O | Enhanced PWM6 output A (HRPWM-capable) | |||
CANRXB | 2 | I | CAN-B receive | |||
ADCSOCBO | 3 | O | ADC start-of-conversion B output for external ADC | |||
EQEP1A | 5 | I | Enhanced QEP1 input A | |||
SCITXDB | 6 | O | SCI-B transmit data | |||
UPP-WAIT | 15 | I/O | Universal parallel port wait. Receiver asserts to request a pause in transfer. | |||
GPIO11 | 0, 4, 8, 12 | C1 | 2 | 1 | I/O | General-purpose input/output 11 |
EPWM6B | 1 | O | Enhanced PWM6 output B (HRPWM-capable) | |||
SCIRXDB | 2, 6 | I | SCI-B receive data | |||
OUTPUTXBAR7 | 3 | O | Output 7 of the output XBAR | |||
EQEP1B | 5 | I | Enhanced QEP1 input B | |||
UPP-START | 15 | I/O | Universal parallel port start. Transmitter asserts at start of DMA line. | |||
GPIO12 | 0, 4, 8, 12 | C2 | 4 | 3 | I/O | General-purpose input/output 12 |
EPWM7A | 1 | O | Enhanced PWM7 output A (HRPWM-capable) | |||
CANTXB | 2 | O | CAN-B transmit | |||
MDXB | 3 | O | McBSP-B transmit serial data | |||
EQEP1S | 5 | I/O | Enhanced QEP1 strobe | |||
SCITXDC | 6 | O | SCI-C transmit data | |||
UPP-ENA | 15 | I/O | Universal parallel port enable. Transmitter asserts while data bus is active. | |||
GPIO13 | 0, 4, 8, 12 | D1 | 5 | 4 | I/O | General-purpose input/output 13 |
EPWM7B | 1 | O | Enhanced PWM7 output B (HRPWM-capable) | |||
CANRXB | 2 | I | CAN-B receive | |||
MDRB | 3 | I | McBSP-B receive serial data | |||
EQEP1I | 5 | I/O | Enhanced QEP1 index | |||
SCIRXDC | 6 | I | SCI-C receive data | |||
UPP-D7 | 15 | I/O | Universal parallel port data line 7 | |||
GPIO14 | 0, 4, 8, 12 | D2 | 6 | 5 | I/O | General-purpose input/output 14 |
EPWM8A | 1 | O | Enhanced PWM8 output A (HRPWM-capable) | |||
SCITXDB | 2 | O | SCI-B transmit data | |||
MCLKXB | 3 | I/O | McBSP-B transmit clock | |||
OUTPUTXBAR3 | 6 | O | Output 3 of the output XBAR | |||
UPP-D6 | 15 | I/O | Universal parallel port data line 6 | |||
GPIO15 | 0, 4, 8, 12 | D3 | 7 | 6 | I/O | General-purpose input/output 15 |
EPWM8B | 1 | O | Enhanced PWM8 output B (HRPWM-capable) | |||
SCIRXDB | 2 | I | SCI-B receive data | |||
MFSXB | 3 | I/O | McBSP-B transmit frame synch | |||
OUTPUTXBAR4 | 6 | O | Output 4 of the output XBAR | |||
UPP-D5 | 15 | I/O | Universal parallel port data line 5 | |||
GPIO16 | 0, 4, 8, 12 | E1 | 8 | 7 | I/O | General-purpose input/output 16 |
SPISIMOA | 1 | I/O | SPI-A slave in, master out | |||
CANTXB | 2 | O | CAN-B transmit | |||
OUTPUTXBAR7 | 3 | O | Output 7 of the output XBAR | |||
EPWM9A | 5 | O | Enhanced PWM9 output A | |||
SD1_D1 | 7 | I | Sigma-Delta 1 channel 1 data input | |||
UPP-D4 | 15 | I/O | Universal parallel port data line 4 | |||
GPIO17 | 0, 4, 8, 12 | E2 | 9 | 8 | I/O | General-purpose input/output 17 |
SPISOMIA | 1 | I/O | SPI-A slave out, master in | |||
CANRXB | 2 | I | CAN-B receive | |||
OUTPUTXBAR8 | 3 | O | Output 8 of the output XBAR | |||
EPWM9B | 5 | O | Enhanced PWM9 output B | |||
SD1_C1 | 7 | I | Sigma-Delta 1 channel 1 clock input | |||
UPP-D3 | 15 | I/O | Universal parallel port data line 3 | |||
GPIO18 | 0, 4, 8, 12 | E3 | 10 | 9 | I/O | General-purpose input/output 18 |
SPICLKA | 1 | I/O | SPI-A clock | |||
SCITXDB | 2 | O | SCI-B transmit data | |||
CANRXA | 3 | I | CAN-A receive | |||
EPWM10A | 5 | O | Enhanced PWM10 output A | |||
SD1_D2 | 7 | I | Sigma-Delta 1 channel 2 data input | |||
UPP-D2 | 15 | I/O | Universal parallel port data line 2 | |||
GPIO19 | 0, 4, 8, 12 | E4 | 12 | 11 | I/O | General-purpose input/output 19 |
SPISTEA | 1 | I/O | SPI-A slave transmit enable | |||
SCIRXDB | 2 | I | SCI-B receive data | |||
CANTXA | 3 | O | CAN-A transmit | |||
EPWM10B | 5 | O | Enhanced PWM10 output B | |||
SD1_C2 | 7 | I | Sigma-Delta 1 channel 2 clock input | |||
UPP-D1 | 15 | I/O | Universal parallel port data line 1 | |||
GPIO20 | 0, 4, 8, 12 | F2 | 13 | 12 | I/O | General-purpose input/output 20 |
EQEP1A | 1 | I | Enhanced QEP1 input A | |||
MDXA | 2 | O | McBSP-A transmit serial data | |||
CANTXB | 3 | O | CAN-B transmit | |||
EPWM11A | 5 | O | Enhanced PWM11 output A | |||
SD1_D3 | 7 | I | Sigma-Delta 1 channel 3 data input | |||
UPP-D0 | 15 | I/O | Universal parallel port data line 0 | |||
GPIO21 | 0, 4, 8, 12 | F3 | 14 | 13 | I/O | General-purpose input/output 21 |
EQEP1B | 1 | I | Enhanced QEP1 input B | |||
MDRA | 2 | I | McBSP-A receive serial data | |||
CANRXB | 3 | I | CAN-B receive | |||
EPWM11B | 5 | O | Enhanced PWM11 output B | |||
SD1_C3 | 7 | I | Sigma-Delta 1 channel 3 clock input | |||
UPP-CLK | 15 | I/O | Universal parallel port transmit clock | |||
GPIO22 | 0, 4, 8, 12 | J4 | 22 | – | I/O | General-purpose input/output 22 |
EQEP1S | 1 | I/O | Enhanced QEP1 strobe | |||
MCLKXA | 2 | I/O | McBSP-A transmit clock | |||
SCITXDB | 3 | O | SCI-B transmit data | |||
EPWM12A | 5 | O | Enhanced PWM12 output A | |||
SPICLKB | 6 | I/O | SPI-B clock | |||
SD1_D4 | 7 | I | Sigma-Delta 1 channel 4 data input | |||
GPIO23 | 0, 4, 8, 12 | K4 | 23 | – | I/O | General-purpose input/output 23 |
EQEP1I | 1 | I/O | Enhanced QEP1 index | |||
MFSXA | 2 | I/O | McBSP-A transmit frame synch | |||
SCIRXDB | 3 | I | SCI-B receive data | |||
EPWM12B | 5 | O | Enhanced PWM12 output B | |||
SPISTEB | 6 | I/O | SPI-B slave transmit enable | |||
SD1_C4 | 7 | I | Sigma-Delta 1 channel 4 clock input | |||
GPIO24 | 0, 4, 8, 12 | K3 | 24 | – | I/O | General-purpose input/output 24 |
OUTPUTXBAR1 | 1 | O | Output 1 of the output XBAR | |||
EQEP2A | 2 | I | Enhanced QEP2 input A | |||
MDXB | 3 | O | McBSP-B transmit serial data | |||
SPISIMOB | 6 | I/O | SPI-B slave in, master out | |||
SD2_D1 | 7 | I | Sigma-Delta 2 channel 1 data input | |||
GPIO25 | 0, 4, 8, 12 | K2 | 25 | – | I/O | General-purpose input/output 25 |
OUTPUTXBAR2 | 1 | O | Output 2 of the output XBAR | |||
EQEP2B | 2 | I | Enhanced QEP2 input B | |||
MDRB | 3 | I | McBSP-B receive serial data | |||
SPISOMIB | 6 | I/O | SPI-B slave out, master in | |||
SD2_C1 | 7 | I | Sigma-Delta 2 channel 1 clock input | |||
GPIO26 | 0, 4, 8, 12 | K1 | 27 | – | I/O | General-purpose input/output 26 |
OUTPUTXBAR3 | 1 | O | Output 3 of the output XBAR | |||
EQEP2I | 2 | I/O | Enhanced QEP2 index | |||
MCLKXB | 3 | I/O | McBSP-B transmit clock | |||
OUTPUTXBAR3 | 5 | O | Output 3 of the output XBAR | |||
SPICLKB | 6 | I/O | SPI-B clock | |||
SD2_D2 | 7 | I | Sigma-Delta 2 channel 2 data input | |||
GPIO27 | 0, 4, 8, 12 | L1 | 28 | – | I/O | General-purpose input/output 27 |
OUTPUTXBAR4 | 1 | O | Output 4 of the output XBAR | |||
EQEP2S | 2 | I/O | Enhanced QEP2 strobe | |||
MFSXB | 3 | I/O | McBSP-B transmit frame synch | |||
OUTPUTXBAR4 | 5 | O | Output 4 of the output XBAR | |||
SPISTEB | 6 | I/O | SPI-B slave transmit enable | |||
SD2_C2 | 7 | I | Sigma-Delta 2 channel 2 clock input | |||
GPIO28 | 0, 4, 8, 12 | V11 | 64 | – | I/O | General-purpose input/output 28 |
SCIRXDA | 1 | I | SCI-A receive data | |||
EM1CS4 | 2 | O | External memory interface 1 chip select 4 | |||
OUTPUTXBAR5 | 5 | O | Output 5 of the output XBAR | |||
EQEP3A | 6 | I | Enhanced QEP3 input A | |||
SD2_D3 | 7 | I | Sigma-Delta 2 channel 3 data input | |||
GPIO29 | 0, 4, 8, 12 | W11 | 65 | – | I/O | General-purpose input/output 29 |
SCITXDA | 1 | O | SCI-A transmit data | |||
EM1SDCKE | 2 | O | External memory interface 1 SDRAM clock enable | |||
OUTPUTXBAR6 | 5 | O | Output 6 of the output XBAR | |||
EQEP3B | 6 | I | Enhanced QEP3 input B | |||
SD2_C3 | 7 | I | Sigma-Delta 2 channel 3 clock input | |||
GPIO30 | 0, 4, 8, 12 | T11 | 63 | – | I/O | General-purpose input/output 30 |
CANRXA | 1 | I | CAN-A receive | |||
EM1CLK | 2 | O | External memory interface 1 clock | |||
OUTPUTXBAR7 | 5 | O | Output 7 of the output XBAR | |||
EQEP3S | 6 | I/O | Enhanced QEP3 strobe | |||
SD2_D4 | 7 | I | Sigma-Delta 2 channel 4 data input | |||
GPIO31 | 0, 4, 8, 12 | U11 | 66 | – | I/O | General-purpose input/output 31 |
CANTXA | 1 | O | CAN-A transmit | |||
EM1WE | 2 | O | External memory interface 1 write enable | |||
OUTPUTXBAR8 | 5 | O | Output 8 of the output XBAR | |||
EQEP3I | 6 | I/O | Enhanced QEP3 index | |||
SD2_C4 | 7 | I | Sigma-Delta 2 channel 4 clock input | |||
GPIO32 | 0, 4, 8, 12 | U13 | 67 | – | I/O | General-purpose input/output 32 |
SDAA | 1 | I/OD | I2C-A data open-drain bidirectional port | |||
EM1CS0 | 2 | O | External memory interface 1 chip select 0 | |||
GPIO33 | 0, 4, 8, 12 | T13 | 69 | – | I/O | General-purpose input/output 33 |
SCLA | 1 | I/OD | I2C-A clock open-drain bidirectional port | |||
EM1RNW | 2 | O | External memory interface 1 read not write | |||
GPIO34 | 0, 4, 8, 12 | U14 | 70 | – | I/O | General-purpose input/output 34 |
OUTPUTXBAR1 | 1 | O | Output 1 of the output XBAR | |||
EM1CS2 | 2 | O | External memory interface 1 chip select 2 | |||
SDAB | 6 | I/OD | I2C-B data open-drain bidirectional port | |||
GPIO35 | 0, 4, 8, 12 | T14 | 71 | – | I/O | General-purpose input/output 35 |
SCIRXDA | 1 | I | SCI-A receive data | |||
EM1CS3 | 2 | O | External memory interface 1 chip select 3 | |||
SCLB | 6 | I/OD | I2C-B clock open-drain bidirectional port | |||
GPIO36 | 0, 4, 8, 12 | V16 | 83 | – | I/O | General-purpose input/output 36 |
SCITXDA | 1 | O | SCI-A transmit data | |||
EM1WAIT | 2 | I | External memory interface 1 Asynchronous SRAM WAIT | |||
CANRXA | 6 | I | CAN-A receive | |||
GPIO37 | 0, 4, 8, 12 | U16 | 84 | – | I/O | General-purpose input/output 37 |
OUTPUTXBAR2 | 1 | O | Output 2 of the output XBAR | |||
EM1OE | 2 | O | External memory interface 1 output enable | |||
CANTXA | 6 | O | CAN-A transmit | |||
GPIO38 | 0, 4, 8, 12 | T16 | 85 | – | I/O | General-purpose input/output 38 |
EM1A0 | 2 | O | External memory interface 1 address line 0 | |||
SCITXDC | 5 | O | SCI-C transmit data | |||
CANTXB | 6 | O | CAN-B transmit | |||
GPIO39 | 0, 4, 8, 12 | W17 | 86 | – | I/O | General-purpose input/output 39 |
EM1A1 | 2 | O | External memory interface 1 address line 1 | |||
SCIRXDC | 5 | I | SCI-C receive data | |||
CANRXB | 6 | I | CAN-B receive | |||
GPIO40 | 0, 4, 8, 12 | V17 | 87 | – | I/O | General-purpose input/output 40 |
EM1A2 | 2 | O | External memory interface 1 address line 2 | |||
SDAB | 6 | I/OD | I2C-B data open-drain bidirectional port | |||
GPIO41 | 0, 4, 8, 12 | U17 | 89 | 51 | I/O | General-purpose input/output 41. For applications using the Hibernate low-power mode, this pin serves as the GPIOHIBWAKE signal. For details, see the Low Power Modes section of the System Control chapter in the TMS320F2837xD Dual-Core Real-Time Microcontrollers Technical Reference Manual. |
EM1A3 | 2 | O | External memory interface 1 address line 3 | |||
SCLB | 6 | I/OD | I2C-B clock open-drain bidirectional port | |||
GPIO42 | 0, 4, 8, 12 | D19 | 130 | 73 | I/O | General-purpose input/output 42 |
SDAA | 6 | I/OD | I2C-A data open-drain bidirectional port | |||
SCITXDA | 15 | O | SCI-A transmit data | |||
USB0DM | Analog | I/O | USB PHY differential data | |||
GPIO43 | 0, 4, 8, 12 | C19 | 131 | 74 | I/O | General-purpose input/output 43 |
SCLA | 6 | I/OD | I2C-A clock open-drain bidirectional port | |||
SCIRXDA | 15 | I | SCI-A receive data | |||
USB0DP | Analog | I/O | USB PHY differential data | |||
GPIO44 | 0, 4, 8, 12 | K18 | 113 | – | I/O | General-purpose input/output 44 |
EM1A4 | 2 | O | External memory interface 1 address line 4 | |||
GPIO45 | 0, 4, 8, 12 | K19 | 115 | – | I/O | General-purpose input/output 45 |
EM1A5 | 2 | O | External memory interface 1 address line 5 | |||
GPIO46 | 0, 4, 8, 12 | E19 | 128 | – | I/O | General-purpose input/output 46 |
EM1A6 | 2 | O | External memory interface 1 address line 6 | |||
SCIRXDD | 6 | I | SCI-D receive data | |||
GPIO47 | 0, 4, 8, 12 | E18 | 129 | – | I/O | General-purpose input/output 47 |
EM1A7 | 2 | O | External memory interface 1 address line 7 | |||
SCITXDD | 6 | O | SCI-D transmit data | |||
GPIO48 | 0, 4, 8, 12 | R16 | 90 | – | I/O | General-purpose input/output 48 |
OUTPUTXBAR3 | 1 | O | Output 3 of the output XBAR | |||
EM1A8 | 2 | O | External memory interface 1 address line 8 | |||
SCITXDA | 6 | O | SCI-A transmit data | |||
SD1_D1 | 7 | I | Sigma-Delta 1 channel 1 data input | |||
GPIO49 | 0, 4, 8, 12 | R17 | 93 | – | I/O | General-purpose input/output 49 |
OUTPUTXBAR4 | 1 | O | Output 4 of the output XBAR | |||
EM1A9 | 2 | O | External memory interface 1 address line 9 | |||
SCIRXDA | 6 | I | SCI-A receive data | |||
SD1_C1 | 7 | I | Sigma-Delta 1 channel 1 clock input | |||
GPIO50 | 0, 4, 8, 12 | R18 | 94 | – | I/O | General-purpose input/output 50 |
EQEP1A | 1 | I | Enhanced QEP1 input A | |||
EM1A10 | 2 | O | External memory interface 1 address line 10 | |||
SPISIMOC | 6 | I/O | SPI-C slave in, master out | |||
SD1_D2 | 7 | I | Sigma-Delta 1 channel 2 data input | |||
GPIO51 | 0, 4, 8, 12 | R19 | 95 | – | I/O | General-purpose input/output 51 |
EQEP1B | 1 | I | Enhanced QEP1 input B | |||
EM1A11 | 2 | O | External memory interface 1 address line 11 | |||
SPISOMIC | 6 | I/O | SPI-C slave out, master in | |||
SD1_C2 | 7 | I | Sigma-Delta 1 channel 2 clock input | |||
GPIO52 | 0, 4, 8, 12 | P16 | 96 | – | I/O | General-purpose input/output 52 |
EQEP1S | 1 | I/O | Enhanced QEP1 strobe | |||
EM1A12 | 2 | O | External memory interface 1 address line 12 | |||
SPICLKC | 6 | I/O | SPI-C clock | |||
SD1_D3 | 7 | I | Sigma-Delta 1 channel 3 data input | |||
GPIO53 | 0, 4, 8, 12 | P17 | 97 | – | I/O | General-purpose input/output 53 |
EQEP1I | 1 | I/O | Enhanced QEP1 index | |||
EM1D31 | 2 | I/O | External memory interface 1 data line 31 | |||
EM2D15 | 3 | I/O | External memory interface 2 data line 15 | |||
SPISTEC | 6 | I/O | SPI-C slave transmit enable | |||
SD1_C3 | 7 | I | Sigma-Delta 1 channel 3 clock input | |||
GPIO54 | 0, 4, 8, 12 | P18 | 98 | – | I/O | General-purpose input/output 54 |
SPISIMOA | 1 | I/O | SPI-A slave in, master out | |||
EM1D30 | 2 | I/O | External memory interface 1 data line 30 | |||
EM2D14 | 3 | I/O | External memory interface 2 data line 14 | |||
EQEP2A | 5 | I | Enhanced QEP2 input A | |||
SCITXDB | 6 | O | SCI-B transmit data | |||
SD1_D4 | 7 | I | Sigma-Delta 1 channel 4 data input | |||
GPIO55 | 0, 4, 8, 12 | P19 | 100 | – | I/O | General-purpose input/output 55 |
SPISOMIA | 1 | I/O | SPI-A slave out, master in | |||
EM1D29 | 2 | I/O | External memory interface 1 data line 29 | |||
EM2D13 | 3 | I/O | External memory interface 2 data line 13 | |||
EQEP2B | 5 | I | Enhanced QEP2 input B | |||
SCIRXDB | 6 | I | SCI-B receive data | |||
SD1_C4 | 7 | I | Sigma-Delta 1 channel 4 clock input | |||
GPIO56 | 0, 4, 8, 12 | N16 | 101 | – | I/O | General-purpose input/output 56 |
SPICLKA | 1 | I/O | SPI-A clock | |||
EM1D28 | 2 | I/O | External memory interface 1 data line 28 | |||
EM2D12 | 3 | I/O | External memory interface 2 data line 12 | |||
EQEP2S | 5 | I/O | Enhanced QEP2 strobe | |||
SCITXDC | 6 | O | SCI-C transmit data | |||
SD2_D1 | 7 | I | Sigma-Delta 2 channel 1 data input | |||
GPIO57 | 0, 4, 8, 12 | N18 | 102 | – | I/O | General-purpose input/output 57 |
SPISTEA | 1 | I/O | SPI-A slave transmit enable | |||
EM1D27 | 2 | I/O | External memory interface 1 data line 27 | |||
EM2D11 | 3 | I/O | External memory interface 2 data line 11 | |||
EQEP2I | 5 | I/O | Enhanced QEP2 index | |||
SCIRXDC | 6 | I | SCI-C receive data | |||
SD2_C1 | 7 | I | Sigma-Delta 2 channel 1 clock input | |||
GPIO58 | 0, 4, 8, 12 | N17 | 103 | 52 | I/O | General-purpose input/output 58 |
MCLKRA | 1 | I/O | McBSP-A receive clock | |||
EM1D26 | 2 | I/O | External memory interface 1 data line 26 | |||
EM2D10 | 3 | I/O | External memory interface 2 data line 10 | |||
OUTPUTXBAR1 | 5 | O | Output 1 of the output XBAR | |||
SPICLKB | 6 | I/O | SPI-B clock | |||
SD2_D2 | 7 | I | Sigma-Delta 2 channel 2 data input | |||
SPISIMOA | 15 | I/O | SPI-A slave in, master out(2) | |||
GPIO59 | 0, 4, 8, 12 | M16 | 104 | 53 | I/O | General-purpose input/output 59(3) |
MFSRA | 1 | I/O | McBSP-A receive frame synch | |||
EM1D25 | 2 | I/O | External memory interface 1 data line 25 | |||
EM2D9 | 3 | I/O | External memory interface 2 data line 9 | |||
OUTPUTXBAR2 | 5 | O | Output 2 of the output XBAR | |||
SPISTEB | 6 | I/O | SPI-B slave transmit enable | |||
SD2_C2 | 7 | I | Sigma-Delta 2 channel 2 clock input | |||
SPISOMIA | 15 | I/O | SPI-A slave out, master in(2) | |||
GPIO60 | 0, 4, 8, 12 | M17 | 105 | 54 | I/O | General-purpose input/output 60 |
MCLKRB | 1 | I/O | McBSP-B receive clock | |||
EM1D24 | 2 | I/O | External memory interface 1 data line 24 | |||
EM2D8 | 3 | I/O | External memory interface 2 data line 8 | |||
OUTPUTXBAR3 | 5 | O | Output 3 of the output XBAR | |||
SPISIMOB | 6 | I/O | SPI-B slave in, master out | |||
SD2_D3 | 7 | I | Sigma-Delta 2 channel 3 data input | |||
SPICLKA | 15 | I/O | SPI-A clock(2) | |||
GPIO61 | 0, 4, 8, 12 | L16 | 107 | 56 | I/O | General-purpose input/output 61(3) |
MFSRB | 1 | I/O | McBSP-B receive frame synch | |||
EM1D23 | 2 | I/O | External memory interface 1 data line 23 | |||
EM2D7 | 3 | I/O | External memory interface 2 data line 7 | |||
OUTPUTXBAR4 | 5 | O | Output 4 of the output XBAR | |||
SPISOMIB | 6 | I/O | SPI-B slave out, master in | |||
SD2_C3 | 7 | I | Sigma-Delta 2 channel 3 clock input | |||
SPISTEA | 15 | I/O | SPI-A slave transmit enable(2) | |||
GPIO62 | 0, 4, 8, 12 | J17 | 108 | 57 | I/O | General-purpose input/output 62 |
SCIRXDC | 1 | I | SCI-C receive data | |||
EM1D22 | 2 | I/O | External memory interface 1 data line 22 | |||
EM2D6 | 3 | I/O | External memory interface 2 data line 6 | |||
EQEP3A | 5 | I | Enhanced QEP3 input A | |||
CANRXA | 6 | I | CAN-A receive | |||
SD2_D4 | 7 | I | Sigma-Delta 2 channel 4 data input | |||
GPIO63 | 0, 4, 8, 12 | J16 | 109 | 58 | I/O | General-purpose input/output 63 |
SCITXDC | 1 | O | SCI-C transmit data | |||
EM1D21 | 2 | I/O | External memory interface 1 data line 21 | |||
EM2D5 | 3 | I/O | External memory interface 2 data line 5 | |||
EQEP3B | 5 | I | Enhanced QEP3 input B | |||
CANTXA | 6 | O | CAN-A transmit | |||
SD2_C4 | 7 | I | Sigma-Delta 2 channel 4 clock input | |||
SPISIMOB | 15 | I/O | SPI-B slave in, master out(2) | |||
GPIO64 | 0, 4, 8, 12 | L17 | 110 | 59 | I/O | General-purpose input/output 64(3) |
EM1D20 | 2 | I/O | External memory interface 1 data line 20 | |||
EM2D4 | 3 | I/O | External memory interface 2 data line 4 | |||
EQEP3S | 5 | I/O | Enhanced QEP3 strobe | |||
SCIRXDA | 6 | I | SCI-A receive data | |||
SPISOMIB | 15 | I/O | SPI-B slave out, master in(2) | |||
GPIO65 | 0, 4, 8, 12 | K16 | 111 | 60 | I/O | General-purpose input/output 65 |
EM1D19 | 2 | I/O | External memory interface 1 data line 19 | |||
EM2D3 | 3 | I/O | External memory interface 2 data line 3 | |||
EQEP3I | 5 | I/O | Enhanced QEP3 index | |||
SCITXDA | 6 | O | SCI-A transmit data | |||
SPICLKB | 15 | I/O | SPI-B clock(2) | |||
GPIO66 | 0, 4, 8, 12 | K17 | 112 | 61 | I/O | General-purpose input/output 66(3) |
EM1D18 | 2 | I/O | External memory interface 1 data line 18 | |||
EM2D2 | 3 | I/O | External memory interface 2 data line 2 | |||
SDAB | 6 | I/OD | I2C-B data open-drain bidirectional port | |||
SPISTEB | 15 | I/O | SPI-B slave transmit enable(2) | |||
GPIO67 | 0, 4, 8, 12 | B19 | 132 | – | I/O | General-purpose input/output 67 |
EM1D17 | 2 | I/O | External memory interface 1 data line 17 | |||
EM2D1 | 3 | I/O | External memory interface 2 data line 1 | |||
GPIO68 | 0, 4, 8, 12 | C18 | 133 | – | I/O | General-purpose input/output 68 |
EM1D16 | 2 | I/O | External memory interface 1 data line 16 | |||
EM2D0 | 3 | I/O | External memory interface 2 data line 0 | |||
GPIO69 | 0, 4, 8, 12 | B18 | 134 | 75 | I/O | General-purpose input/output 69 |
EM1D15 | 2 | I/O | External memory interface 1 data line 15 | |||
SCLB | 6 | I/OD | I2C-B clock open-drain bidirectional port | |||
SPISIMOC | 15 | I/O | SPI-C slave in, master out(2) | |||
GPIO70 | 0, 4, 8, 12 | A17 | 135 | 76 | I/O | General-purpose input/output 70(3) |
EM1D14 | 2 | I/O | External memory interface 1 data line 14 | |||
CANRXA | 5 | I | CAN-A receive | |||
SCITXDB | 6 | O | SCI-B transmit data | |||
SPISOMIC | 15 | I/O | SPI-C slave out, master in(2) | |||
GPIO71 | 0, 4, 8, 12 | B17 | 136 | 77 | I/O | General-purpose input/output 71 |
EM1D13 | 2 | I/O | External memory interface 1 data line 13 | |||
CANTXA | 5 | O | CAN-A transmit | |||
SCIRXDB | 6 | I | SCI-B receive data | |||
SPICLKC | 15 | I/O | SPI-C clock(2) | |||
GPIO72 | 0, 4, 8, 12 | B16 | 139 | 80 | I/O | General-purpose input/output 72.(3) This is the factory default boot mode select pin 1. |
EM1D12 | 2 | I/O | External memory interface 1 data line 12 | |||
CANTXB | 5 | O | CAN-B transmit | |||
SCITXDC | 6 | O | SCI-C transmit data | |||
SPISTEC | 15 | I/O | SPI-C slave transmit enable(2) | |||
GPIO73 | 0, 4, 8, 12 | A16 | 140 | 81 | I/O | General-purpose input/output 73 |
EM1D11 | 2 | I/O | External memory interface 1 data line 11 | |||
XCLKOUT | 3 | O/Z | External clock output. This pin outputs a divided-down version of a chosen clock signal from within the device. The clock signal is chosen using the CLKSRCCTL3.XCLKOUTSEL bit field while the divide ratio is chosen using the XCLKOUTDIVSEL.XCLKOUTDIV bit field. | |||
CANRXB | 5 | I | CAN-B receive | |||
SCIRXDC | 6 | I | SCI-C receive | |||
GPIO74 | 0, 4, 8, 12 | C17 | 141 | – | I/O | General-purpose input/output 74 |
EM1D10 | 2 | I/O | External memory interface 1 data line 10 | |||
GPIO75 | 0, 4, 8, 12 | D16 | 142 | – | I/O | General-purpose input/output 75 |
EM1D9 | 2 | I/O | External memory interface 1 data line 9 | |||
GPIO76 | 0, 4, 8, 12 | C16 | 143 | – | I/O | General-purpose input/output 76 |
EM1D8 | 2 | I/O | External memory interface 1 data line 8 | |||
SCITXDD | 6 | O | SCI-D transmit data | |||
GPIO77 | 0, 4, 8, 12 | A15 | 144 | – | I/O | General-purpose input/output 77 |
EM1D7 | 2 | I/O | External memory interface 1 data line 7 | |||
SCIRXDD | 6 | I | SCI-D receive data | |||
GPIO78 | 0, 4, 8, 12 | B15 | 145 | 82 | I/O | General-purpose input/output 78 |
EM1D6 | 2 | I/O | External memory interface 1 data line 6 | |||
EQEP2A | 6 | I | Enhanced QEP2 input A | |||
GPIO79 | 0, 4, 8, 12 | C15 | 146 | – | I/O | General-purpose input/output 79 |
EM1D5 | 2 | I/O | External memory interface 1 data line 5 | |||
EQEP2B | 6 | I | Enhanced QEP2 input B | |||
GPIO80 | 0, 4, 8, 12 | D15 | 148 | – | I/O | General-purpose input/output 80 |
EM1D4 | 2 | I/O | External memory interface 1 data line 4 | |||
EQEP2S | 6 | I/O | Enhanced QEP2 strobe | |||
GPIO81 | 0, 4, 8, 12 | A14 | 149 | – | I/O | General-purpose input/output 81 |
EM1D3 | 2 | I/O | External memory interface 1 data line 3 | |||
EQEP2I | 6 | I/O | Enhanced QEP2 index | |||
GPIO82 | 0, 4, 8, 12 | B14 | 150 | – | I/O | General-purpose input/output 82 |
EM1D2 | 2 | I/O | External memory interface 1 data line 2 | |||
GPIO83 | 0, 4, 8, 12 | C14 | 151 | – | I/O | General-purpose input/output 83 |
EM1D1 | 2 | I/O | External memory interface 1 data line 1 | |||
GPIO84 | 0, 4, 8, 12 | A11 | 154 | 85 | I/O | General-purpose input/output 84. This is the factory default boot mode select pin 0. |
SCITXDA | 5 | O | SCI-A transmit data | |||
MDXB | 6 | O | McBSP-B transmit serial data | |||
MDXA | 15 | O | McBSP-A transmit serial data | |||
GPIO85 | 0, 4, 8, 12 | B11 | 155 | 86 | I/O | General-purpose input/output 85 |
EM1D0 | 2 | I/O | External memory interface 1 data line 0 | |||
SCIRXDA | 5 | I | SCI-A receive data | |||
MDRB | 6 | I | McBSP-B receive serial data | |||
MDRA | 15 | I | McBSP-A receive serial data | |||
GPIO86 | 0, 4, 8, 12 | C11 | 156 | 87 | I/O | General-purpose input/output 86 |
EM1A13 | 2 | O | External memory interface 1 address line 13 | |||
EM1CAS | 3 | O | External memory interface 1 column address strobe | |||
SCITXDB | 5 | O | SCI-B transmit data | |||
MCLKXB | 6 | I/O | McBSP-B transmit clock | |||
MCLKXA | 15 | I/O | McBSP-A transmit clock | |||
GPIO87 | 0, 4, 8, 12 | D11 | 157 | 88 | I/O | General-purpose input/output 87 |
EM1A14 | 2 | O | External memory interface 1 address line 14 | |||
EM1RAS | 3 | O | External memory interface 1 row address strobe | |||
SCIRXDB | 5 | I | SCI-B receive data | |||
MFSXB | 6 | I/O | McBSP-B transmit frame synch | |||
MFSXA | 15 | I/O | McBSP-A transmit frame synch | |||
GPIO88 | 0, 4, 8, 12 | C6 | 170 | – | I/O | General-purpose input/output 88 |
EM1A15 | 2 | O | External memory interface 1 address line 15 | |||
EM1DQM0 | 3 | O | External memory interface 1 Input/output mask for byte 0 | |||
GPIO89 | 0, 4, 8, 12 | D6 | 171 | 96 | I/O | General-purpose input/output 89 |
EM1A16 | 2 | O | External memory interface 1 address line 16 | |||
EM1DQM1 | 3 | O | External memory interface 1 Input/output mask for byte 1 | |||
SCITXDC | 6 | O | SCI-C transmit data | |||
GPIO90 | 0, 4, 8, 12 | A5 | 172 | 97 | I/O | General-purpose input/output 90 |
EM1A17 | 2 | O | External memory interface 1 address line 17 | |||
EM1DQM2 | 3 | O | External memory interface 1 Input/output mask for byte 2 | |||
SCIRXDC | 6 | I | SCI-C receive data | |||
GPIO91 | 0, 4, 8, 12 | B5 | 173 | 98 | I/O | General-purpose input/output 91 |
EM1A18 | 2 | O | External memory interface 1 address line 18 | |||
EM1DQM3 | 3 | O | External memory interface 1 Input/output mask for byte 3 | |||
SDAA | 6 | I/OD | I2C-A data open-drain bidirectional port | |||
GPIO92 | 0, 4, 8, 12 | A4 | 174 | 99 | I/O | General-purpose input/output 92 |
EM1A19 | 2 | O | External memory interface 1 address line 19 | |||
EM1BA1 | 3 | O | External memory interface 1 bank address 1 | |||
SCLA | 6 | I/OD | I2C-A clock open-drain bidirectional port | |||
GPIO93 | 0, 4, 8, 12 | B4 | 175 | – | I/O | General-purpose input/output 93 |
EM1BA0 | 3 | O | External memory interface 1 bank address 0 | |||
SCITXDD | 6 | O | SCI-D transmit data | |||
GPIO94 | 0, 4, 8, 12 | A3 | 176 | – | I/O | General-purpose input/output 94 |
SCIRXDD | 6 | I | SCI-D receive data | |||
GPIO95 | 0, 4, 8, 12 | B3 | – | – | I/O | General-purpose input/output 95 |
GPIO96 | 0, 4, 8, 12 | C3 | – | – | I/O | General-purpose input/output 96 |
EM2DQM1 | 3 | O | External memory interface 2 Input/output mask for byte 1 | |||
EQEP1A | 5 | I | Enhanced QEP1 input A | |||
GPIO97 | 0, 4, 8, 12 | A2 | – | – | I/O | General-purpose input/output 97 |
EM2DQM0 | 3 | O | External memory interface 2 Input/output mask for byte 0 | |||
EQEP1B | 5 | I | Enhanced QEP1 input B | |||
GPIO98 | 0, 4, 8, 12 | F1 | – | – | I/O | General-purpose input/output 98 |
EM2A0 | 3 | O | External memory interface 2 address line 0 | |||
EQEP1S | 5 | I/O | Enhanced QEP1 strobe | |||
GPIO99 | 0, 4, 8, 12 | G1 | 17 | 14 | I/O | General-purpose input/output 99 |
EM2A1 | 3 | O | External memory interface 2 address line 1 | |||
EQEP1I | 5 | I/O | Enhanced QEP1 index | |||
GPIO100 | 0, 4, 8, 12 | H1 | – | – | I/O | General-purpose input/output 100 |
EM2A2 | 3 | O | External memory interface 2 address line 2 | |||
EQEP2A | 5 | I | Enhanced QEP2 input A | |||
SPISIMOC | 6 | I/O | SPI-C slave in, master out | |||
GPIO101 | 0, 4, 8, 12 | H2 | – | – | I/O | General-purpose input/output 101 |
EM2A3 | 3 | O | External memory interface 2 address line 3 | |||
EQEP2B | 5 | I | Enhanced QEP2 input B | |||
SPISOMIC | 6 | I/O | SPI-C slave out, master in | |||
GPIO102 | 0, 4, 8, 12 | H3 | – | – | I/O | General-purpose input/output 102 |
EM2A4 | 3 | O | External memory interface 2 address line 4 | |||
EQEP2S | 5 | I/O | Enhanced QEP2 strobe | |||
SPICLKC | 6 | I/O | SPI-C clock | |||
GPIO103 | 0, 4, 8, 12 | J1 | – | – | I/O | General-purpose input/output 103 |
EM2A5 | 3 | O | External memory interface 2 address line 5 | |||
EQEP2I | 5 | I/O | Enhanced QEP2 index | |||
SPISTEC | 6 | I/O | SPI-C slave transmit enable | |||
GPIO104 | 0, 4, 8, 12 | J2 | – | – | I/O | General-purpose input/output 104 |
SDAA | 1 | I/OD | I2C-A data open-drain bidirectional port | |||
EM2A6 | 3 | O | External memory interface 2 address line 6 | |||
EQEP3A | 5 | I | Enhanced QEP3 input A | |||
SCITXDD | 6 | O | SCI-D transmit data | |||
GPIO105 | 0, 4, 8, 12 | J3 | – | – | I/O | General-purpose input/output 105 |
SCLA | 1 | I/OD | I2C-A clock open-drain bidirectional port | |||
EM2A7 | 3 | O | External memory interface 2 address line 7 | |||
EQEP3B | 5 | I | Enhanced QEP3 input B | |||
SCIRXDD | 6 | I | SCI-D receive data | |||
GPIO106 | 0, 4, 8, 12 | L2 | – | – | I/O | General-purpose input/output 106 |
EM2A8 | 3 | O | External memory interface 2 address line 8 | |||
EQEP3S | 5 | I/O | Enhanced QEP3 strobe | |||
SCITXDC | 6 | O | SCI-C transmit data | |||
GPIO107 | 0, 4, 8, 12 | L3 | – | – | I/O | General-purpose input/output 107 |
EM2A9 | 3 | O | External memory interface 2 address line 9 | |||
EQEP3I | 5 | I/O | Enhanced QEP3 index | |||
SCIRXDC | 6 | I | SCI-C receive data | |||
GPIO108 | 0, 4, 8, 12 | L4 | – | – | I/O | General-purpose input/output 108 |
EM2A10 | 3 | O | External memory interface 2 address line 10 | |||
GPIO109 | 0, 4, 8, 12 | N2 | – | – | I/O | General-purpose input/output 109 |
EM2A11 | 3 | O | External memory interface 2 address line 11 | |||
GPIO110 | 0, 4, 8, 12 | M2 | – | – | I/O | General-purpose input/output 110 |
EM2WAIT | 3 | I | External memory interface 2 Asynchronous SRAM WAIT | |||
GPIO111 | 0, 4, 8, 12 | M4 | – | – | I/O | General-purpose input/output 111 |
EM2BA0 | 3 | O | External memory interface 2 bank address 0 | |||
GPIO112 | 0, 4, 8, 12 | M3 | – | – | I/O | General-purpose input/output 112 |
EM2BA1 | 3 | O | External memory interface 2 bank address 1 | |||
GPIO113 | 0, 4, 8, 12 | N4 | – | – | I/O | General-purpose input/output 113 |
EM2CAS | 3 | O | External memory interface 2 column address strobe | |||
GPIO114 | 0, 4, 8, 12 | N3 | – | – | I/O | General-purpose input/output 114 |
EM2RAS | 3 | O | External memory interface 2 row address strobe | |||
GPIO115 | 0, 4, 8, 12 | V12 | – | – | I/O | General-purpose input/output 115 |
EM2CS0 | 3 | O | External memory interface 2 chip select 0 | |||
GPIO116 | 0, 4, 8, 12 | W10 | – | – | I/O | General-purpose input/output 116 |
EM2CS2 | 3 | O | External memory interface 2 chip select 2 | |||
GPIO117 | 0, 4, 8, 12 | U12 | – | – | I/O | General-purpose input/output 117 |
EM2SDCKE | 3 | O | External memory interface 2 SDRAM clock enable | |||
GPIO118 | 0, 4, 8, 12 | T12 | – | – | I/O | General-purpose input/output 118 |
EM2CLK | 3 | O | External memory interface 2 clock | |||
GPIO119 | 0, 4, 8, 12 | T15 | – | – | I/O | General-purpose input/output 119 |
EM2RNW | 3 | O | External memory interface 2 read not write | |||
GPIO120 | 0, 4, 8, 12 | U15 | – | – | I/O | General-purpose input/output 120 |
EM2WE | 3 | O | External memory interface 2 write enable | |||
USB0PFLT | 15 | I/O | USB external regulator power fault indicator | |||
GPIO121 | 0, 4, 8, 12 | W16 | – | – | I/O | General-purpose input/output 121 |
EM2OE | 3 | O | External memory interface 2 output enable | |||
USB0EPEN | 15 | I/O | USB external regulator enable | |||
GPIO122 | 0, 4, 8, 12 | T8 | – | – | I/O | General-purpose input/output 122 |
SPISIMOC | 6 | I/O | SPI-C slave in, master out | |||
SD1_D1 | 7 | I | Sigma-Delta 1 channel 1 data input | |||
GPIO123 | 0, 4, 8, 12 | U8 | – | – | I/O | General-purpose input/output 123 |
SPISOMIC | 6 | I/O | SPI-C slave out, master in | |||
SD1_C1 | 7 | I | Sigma-Delta 1 channel 1 clock input | |||
GPIO124 | 0, 4, 8, 12 | V8 | – | – | I/O | General-purpose input/output 124 |
SPICLKC | 6 | I/O | SPI-C clock | |||
SD1_D2 | 7 | I | Sigma-Delta 1 channel 2 data input | |||
GPIO125 | 0, 4, 8, 12 | T9 | – | – | I/O | General-purpose input/output 125 |
SPISTEC | 6 | I/O | SPI-C slave transmit enable | |||
SD1_C2 | 7 | I | Sigma-Delta 1 channel 2 clock input | |||
GPIO126 | 0, 4, 8, 12 | U9 | – | – | I/O | General-purpose input/output 126 |
SD1_D3 | 7 | I | Sigma-Delta 1 channel 3 data input | |||
GPIO127 | 0, 4, 8, 12 | V9 | – | – | I/O | General-purpose input/output 127 |
SD1_C3 | 7 | I | Sigma-Delta 1 channel 3 clock input | |||
GPIO128 | 0, 4, 8, 12 | W9 | – | – | I/O | General-purpose input/output 128 |
SD1_D4 | 7 | I | Sigma-Delta 1 channel 4 data input | |||
GPIO129 | 0, 4, 8, 12 | T10 | – | – | I/O | General-purpose input/output 129 |
SD1_C4 | 7 | I | Sigma-Delta 1 channel 4 clock input | |||
GPIO130 | 0, 4, 8, 12 | U10 | – | – | I/O | General-purpose input/output 130 |
SD2_D1 | 7 | I | Sigma-Delta 2 channel 1 data input | |||
GPIO131 | 0, 4, 8, 12 | V10 | – | – | I/O | General-purpose input/output 131 |
SD2_C1 | 7 | I | Sigma-Delta 2 channel 1 clock input | |||
GPIO132 | 0, 4, 8, 12 | W18 | – | – | I/O | General-purpose input/output 132 |
SD2_D2 | 7 | I | Sigma-Delta 2 channel 2 data input | |||
GPIO133/AUXCLKIN | 0, 4, 8, 12 | G18 | 118 | – | I/O | General-purpose input/output 133. The AUXCLKIN function of this GPIO pin could be used to provide a single-ended 3.3-V level clock signal to the Auxiliary Phase-Locked Loop (AUXPLL), whose output is used for the USB module. The AUXCLKIN clock may also be used for the CAN module. |
SD2_C2 | 7 | I | Sigma-Delta 2 channel 2 clock input | |||
GPIO134 | 0, 4, 8, 12 | V18 | – | – | I/O | General-purpose input/output 134 |
SD2_D3 | 7 | I | Sigma-Delta 2 channel 3 data input | |||
GPIO135 | 0, 4, 8, 12 | U18 | – | – | I/O | General-purpose input/output 135 |
SCITXDA | 6 | O | SCI-A transmit data | |||
SD2_C3 | 7 | I | Sigma-Delta 2 channel 3 clock input | |||
GPIO136 | 0, 4, 8, 12 | T17 | – | – | I/O | General-purpose input/output 136 |
SCIRXDA | 6 | I | SCI-A receive data | |||
SD2_D4 | 7 | I | Sigma-Delta 2 channel 4 data input | |||
GPIO137 | 0, 4, 8, 12 | T18 | – | – | I/O | General-purpose input/output 137 |
SCITXDB | 6 | O | SCI-B transmit data | |||
SD2_C4 | 7 | I | Sigma-Delta 2 channel 4 clock input | |||
GPIO138 | 0, 4, 8, 12 | T19 | – | – | I/O | General-purpose input/output 138 |
SCIRXDB | 6 | I | SCI-B receive data | |||
GPIO139 | 0, 4, 8, 12 | N19 | – | – | I/O | General-purpose input/output 139 |
SCIRXDC | 6 | I | SCI-C receive data | |||
GPIO140 | 0, 4, 8, 12 | M19 | – | – | I/O | General-purpose input/output 140 |
SCITXDC | 6 | O | SCI-C transmit data | |||
GPIO141 | 0, 4, 8, 12 | M18 | – | – | I/O | General-purpose input/output 141 |
SCIRXDD | 6 | I | SCI-D receive data | |||
GPIO142 | 0, 4, 8, 12 | L19 | – | – | I/O | General-purpose input/output 142 |
SCITXDD | 6 | O | SCI-D transmit data | |||
GPIO143 | 0, 4, 8, 12 | F18 | – | – | I/O | General-purpose input/output 143 |
GPIO144 | 0, 4, 8, 12 | F17 | – | – | I/O | General-purpose input/output 144 |
GPIO145 | 0, 4, 8, 12 | E17 | – | – | I/O | General-purpose input/output 145 |
EPWM1A | 1 | O | Enhanced PWM1 output A (HRPWM-capable) | |||
GPIO146 | 0, 4, 8, 12 | D18 | – | – | I/O | General-purpose input/output 146 |
EPWM1B | 1 | O | Enhanced PWM1 output B (HRPWM-capable) | |||
GPIO147 | 0, 4, 8, 12 | D17 | – | – | I/O | General-purpose input/output 147 |
EPWM2A | 1 | O | Enhanced PWM2 output A (HRPWM-capable) | |||
GPIO148 | 0, 4, 8, 12 | D14 | – | – | I/O | General-purpose input/output 148 |
EPWM2B | 1 | O | Enhanced PWM2 output B (HRPWM-capable) | |||
GPIO149 | 0, 4, 8, 12 | A13 | – | – | I/O | General-purpose input/output 149 |
EPWM3A | 1 | O | Enhanced PWM3 output A (HRPWM-capable) | |||
GPIO150 | 0, 4, 8, 12 | B13 | – | – | I/O | General-purpose input/output 150 |
EPWM3B | 1 | O | Enhanced PWM3 output B (HRPWM-capable) | |||
GPIO151 | 0, 4, 8, 12 | C13 | – | – | I/O | General-purpose input/output 151 |
EPWM4A | 1 | O | Enhanced PWM4 output A (HRPWM-capable) | |||
GPIO152 | 0, 4, 8, 12 | D13 | – | – | I/O | General-purpose input/output 152 |
EPWM4B | 1 | O | Enhanced PWM4 output B (HRPWM-capable) | |||
GPIO153 | 0, 4, 8, 12 | A12 | – | – | I/O | General-purpose input/output 153 |
EPWM5A | 1 | O | Enhanced PWM5 output A (HRPWM-capable) | |||
GPIO154 | 0, 4, 8, 12 | B12 | – | – | I/O | General-purpose input/output 154 |
EPWM5B | 1 | O | Enhanced PWM5 output B (HRPWM-capable) | |||
GPIO155 | 0, 4, 8, 12 | C12 | – | – | I/O | General-purpose input/output 155 |
EPWM6A | 1 | O | Enhanced PWM6 output A (HRPWM-capable) | |||
GPIO156 | 0, 4, 8, 12 | D12 | – | – | I/O | General-purpose input/output 156 |
EPWM6B | 1 | O | Enhanced PWM6 output B (HRPWM-capable) | |||
GPIO157 | 0, 4, 8, 12 | B10 | – | – | I/O | General-purpose input/output 157 |
EPWM7A | 1 | O | Enhanced PWM7 output A (HRPWM-capable) | |||
GPIO158 | 0, 4, 8, 12 | C10 | – | – | I/O | General-purpose input/output 158 |
EPWM7B | 1 | O | Enhanced PWM7 output B (HRPWM-capable) | |||
GPIO159 | 0, 4, 8, 12 | D10 | – | – | I/O | General-purpose input/output 159 |
EPWM8A | 1 | O | Enhanced PWM8 output A (HRPWM-capable) | |||
GPIO160 | 0, 4, 8, 12 | B9 | – | – | I/O | General-purpose input/output 160 |
EPWM8B | 1 | O | Enhanced PWM8 output B (HRPWM-capable) | |||
GPIO161 | 0, 4, 8, 12 | C9 | – | – | I/O | General-purpose input/output 161 |
EPWM9A | 1 | O | Enhanced PWM9 output A | |||
GPIO162 | 0, 4, 8, 12 | D9 | – | – | I/O | General-purpose input/output 162 |
EPWM9B | 1 | O | Enhanced PWM9 output B | |||
GPIO163 | 0, 4, 8, 12 | A8 | – | – | I/O | General-purpose input/output 163 |
EPWM10A | 1 | O | Enhanced PWM10 output A | |||
GPIO164 | 0, 4, 8, 12 | B8 | – | – | I/O | General-purpose input/output 164 |
EPWM10B | 1 | O | Enhanced PWM10 output B | |||
GPIO165 | 0, 4, 8, 12 | C5 | – | – | I/O | General-purpose input/output 165 |
EPWM11A | 1 | O | Enhanced PWM11 output A | |||
GPIO166 | 0, 4, 8, 12 | D5 | – | – | I/O | General-purpose input/output 166 |
EPWM11B | 1 | O | Enhanced PWM11 output B | |||
GPIO167 | 0, 4, 8, 12 | C4 | – | – | I/O | General-purpose input/output 167 |
EPWM12A | 1 | O | Enhanced PWM12 output A | |||
GPIO168 | 0, 4, 8, 12 | D4 | – | – | I/O | General-purpose input/output 168 |
EPWM12B | 1 | O | Enhanced PWM12 output B | |||
RESET | ||||||
XRS | F19 | 124 | 69 | I/OD | Device Reset (in) and Watchdog Reset (out). The devices have a built-in power-on reset (POR) circuit. During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset or NMI watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is placed between XRS and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. The output buffer of this pin is an open drain with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device. | |
CLOCKS | ||||||
X1 | G19 | 123 | 68 | I | On-chip crystal-oscillator input. To use this oscillator, a quartz crystal must be connected across X1 and X2. If this pin is not used, it must be tied to GND. This pin can also be used to feed a single-ended 3.3-V level clock. In this case, X2 is a No Connect (NC). | |
X2 | J19 | 121 | 66 | O | On-chip crystal-oscillator output. A quartz crystal may be connected across X1 and X2. If X2 is not used, it must be left unconnected. | |
NO CONNECT | ||||||
NC | H4 | – | – | No connect. BGA ball is electrically open and not connected to the die. | ||
JTAG | ||||||
TCK | V15 | 81 | 50 | I | JTAG test clock with internal pullup (see Section 6.6) | |
TDI | W13 | 77 | 46 | I | JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. | |
TDO | W15 | 78 | 47 | O/Z | JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK.(3) | |
TMS | W14 | 80 | 49 | I | JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. | |
TRST | V14 | 79 | 48 | I | JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST must be maintained low at all times during normal device operation, so an external pulldown resistor is required on this pin for protection against noise spikes. The value of this resistor should be as small as possible, so long as the JTAG debug probe is still able to drive the TRST pin high. A resistor between 2.2-kΩ and 10-kΩ generally offers adequate protection. Since the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debug probe and the application. This pin has an internal 50-ns (nominal) glitch filter. | |
INTERNAL VOLTAGE REGULATOR CONTROL | ||||||
VREGENZ | J18 | 119 | 64 | I | Internal voltage regulator enable with internal pulldown. The internal VREG is not supported and must be disabled. Connect VREGENZ to VDDIO. | |
ANALOG, DIGITAL, AND I/O POWER | ||||||
VDD | E9 | 16 | 16 | 1.2-V digital
logic power pins. There are two options for placing the decoupling capacitors.
| ||
E11 | 21 | 39 | ||||
F9 | 61 | 45 | ||||
F11 | 76 | 63 | ||||
G14 | 117 | 71 | ||||
G15 | 126 | 78 | ||||
J14 | 137 | 84 | ||||
J15 | 153 | 89 | ||||
K5 | 158 | 95 | ||||
K6 | 169 | – | ||||
P10 | – | – | ||||
P13 | – | – | ||||
R10 | – | – | ||||
R13 | – | – | ||||
VDD3VFL | R11 | 72 | 41 | 3.3-V Flash power pin. Place a minimum 0.1-µF decoupling capacitor on each pin. | ||
R12 | – | – | ||||
VDDA | P6 | 36 | 18 | 3.3-V analog power pins. Place a minimum 2.2-µF decoupling capacitor to VSSA on each pin. | ||
R6 | 54 | 38 | ||||
VDDIO | A9 | 3 | 2 | 3.3-V digital I/O power pins. Place a minimum 0.1-µF decoupling capacitor on each pin. The exact value of the decoupling capacitance should be determined by your system voltage regulation solution. | ||
A18 | 11 | 10 | ||||
B1 | 15 | 15 | ||||
E7 | 20 | 40 | ||||
E10 | 26 | 44 | ||||
E13 | 62 | 55 | ||||
E16 | 68 | 62 | ||||
F4 | 75 | 72 | ||||
F7 | 82 | 79 | ||||
F10 | 88 | 83 | ||||
F13 | 91 | 90 | ||||
F16 | 99 | 94 | ||||
G4 | 106 | – | ||||
G5 | 114 | – | ||||
G6 | 116 | – | ||||
H5 | 127 | – | ||||
H6 | 138 | – | ||||
L14 | 147 | – | ||||
L15 | 152 | – | ||||
M1 | 159 | – | ||||
M5 | 168 | – | ||||
M6 | – | – | ||||
N14 | – | – | ||||
N15 | – | – | ||||
P9 | – | – | ||||
R9 | – | – | ||||
V19 | – | – | ||||
W8 | – | – | ||||
VDDOSC | H16 | 120 | 65 | Power pins for the 3.3-V on-chip crystal oscillator (X1 and X2) and the two zero-pin internal oscillators (INTOSC). Place a 0.1-μF (minimum) decoupling capacitor on each pin. | ||
H17 | 125 | 70 | ||||
VSS | A1 | PWR PAD (177) | PWR PAD (101) | Device ground. For Quad Flatpacks (QFPs), the PowerPAD on the bottom of the package must be soldered to the ground plane of the PCB. | ||
A10 | ||||||
A19 | ||||||
E5 | ||||||
E6 | ||||||
E8 | ||||||
E12 | ||||||
E14 | ||||||
E15 | ||||||
F5 | ||||||
F6 | ||||||
F8 | ||||||
F12 | ||||||
F14 | ||||||
F15 | ||||||
G16 | ||||||
G17 | ||||||
H8 | ||||||
H9 | ||||||
H10 | ||||||
H11 | ||||||
H12 | ||||||
H14 | ||||||
H15 | ||||||
J5 | ||||||
J6 | ||||||
J8 | ||||||
J9 | ||||||
J10 | ||||||
J11 | ||||||
J12 | ||||||
K8 | ||||||
K9 | ||||||
K10 | ||||||
K11 | ||||||
K12 | ||||||
K14 | ||||||
K15 | ||||||
L5 | ||||||
L6 | ||||||
L8 | ||||||
L9 | ||||||
VSS | L10 | PWR PAD (177) | PWR PAD (101) | Device ground. For Quad Flatpacks (QFPs), the PowerPAD on the bottom of the package must be soldered to the ground plane of the PCB. | ||
L11 | ||||||
L12 | ||||||
L18 | ||||||
M8 | ||||||
M9 | ||||||
M10 | ||||||
M11 | ||||||
M12 | ||||||
M14 | ||||||
M15 | ||||||
N1 | ||||||
N5 | ||||||
N6 | ||||||
P7 | ||||||
P8 | ||||||
P11 | ||||||
P12 | ||||||
P14 | ||||||
P15 | ||||||
R7 | ||||||
R8 | ||||||
R14 | ||||||
R15 | ||||||
W7 | ||||||
W19 | ||||||
VSSOSC | H18 | 122 | 67 | Crystal oscillator (X1 and X2) ground pin. When using an external crystal, do not connect this pin to the board ground. Instead, connect it to the ground reference of the external crystal oscillator circuit. If an external crystal is not used, this pin may be connected to the board ground. | ||
H19 | – | – | ||||
VSSA | P1 | 34 | 17 | Analog ground. On the PZP package, pin 17 is double-bonded to VSSA and VREFLOA. This pin must be connect to VSSA. | ||
P5 | 52 | 35 | ||||
R5 | – | 36 | ||||
V7 | – | – | ||||
W1 | – | – | ||||
SPECIAL FUNCTIONS | ||||||
ERRORSTS | U19 | 92 | – | O | Error status output. This pin has an internal pulldown. | |
TEST PINS | ||||||
FLT1 | W12 | 73 | 42 | I/O | Flash test pin 1. Reserved for TI. Must be left unconnected. | |
FLT2 | V13 | 74 | 43 | I/O | Flash test pin 2. Reserved for TI. Must be left unconnected. |