SPRS880P December 2013 – February 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
MIN | TYP | MAX | UNIT | |
---|---|---|---|---|
ADCCLK (derived from PERx.SYSCLK) | 5 | 50 | MHz | |
Sample window duration (set by ACQPS and PERx.SYSCLK)(1) | 75 | ns | ||
VREFHI | 2.4 | 2.5 or 3.0 | VDDA | V |
VREFLO | VSSA | 0 | VSSA | V |
VREFHI – VREFLO | 2.4 | VDDA | V | |
ADC input conversion range | VREFLO | VREFHI | V |
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this level, the VREF internal to the device may be disturbed, which can impact results for other ADC or DAC inputs using the same VREF.
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VREFHI pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may float to 0 V internally, giving improper ADC conversion or DAC output.