SPRS880P December 2013 – February 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
ADC conversion cycles(1) | 29.6 | 31 | ADCCLKs | ||
Power-up time (after setting ADCPWDNZ to first conversion) | 500 | µs | |||
Gain error | –64 | ±9 | 64 | LSBs | |
Offset error(2) | –16 | ±9 | 16 | LSBs | |
Channel-to-channel gain error | ±6 | LSBs | |||
Channel-to-channel offset error | ±3 | LSBs | |||
ADC-to-ADC gain error | Identical VREFHI and VREFLO for all ADCs | ±6 | LSBs | ||
ADC-to-ADC offset error | Identical VREFHI and VREFLO for all ADCs | ±3 | LSBs | ||
DNL(3) | > –1 | ±0.5 | 1 | LSBs | |
INL | –3 | ±1.5 | 3 | LSBs | |
SNR(4)(11) | VREFHI = 2.5 V, fin = 10 kHz | 90.2 | dB | ||
THD(4)(11) | VREFHI = 2.5 V, fin = 10 kHz | –105 | dB | ||
SFDR(4)(11) | VREFHI = 2.5 V, fin = 10 kHz | 106 | dB | ||
SINAD(4)(11) | VREFHI = 2.5 V, fin = 10 kHz | 90.0 | dB | ||
ENOB(4)(11) | VREFHI = 2.5 V, fin = 10 kHz, single ADC(7) |
14.65 | bits | ||
VREFHI = 2.5 V, fin = 10 kHz, synchronous ADCs(8) | 14.65 | ||||
VREFHI = 2.5 V, fin = 10 kHz, asynchronous ADCs(9) | Not supported | ||||
PSRR | VDDA = 3.3-V DC + 200 mV DC up to Sine at 1 kHz | 77 | dB | ||
PSRR | VDDA = 3.3-V DC + 200 mV Sine at 800 kHz | 74 | dB | ||
CMRR | DC to 1 MHz | 60 | dB | ||
VREFHI input current | 190 | µA | |||
ADC-to-ADC isolation(11)(5)(10) | VREFHI = 2.5 V, synchronous ADCs(8) | –2 | 2 | LSBs | |
VREFHI = 2.5 V, asynchronous ADCs(9) | Not supported |