SPRSP14E may   2019  – june 2023 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Revision History
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1 Analog Signals
      2. 6.3.2 Digital Signals
      3. 6.3.3 Power and Ground
      4. 6.3.4 Test, JTAG, and Reset
    4. 6.4 Pins With Internal Pullup and Pulldown
    5. 6.5 Pin Multiplexing
      1. 6.5.1 GPIO Muxed Pins Table
      2. 6.5.2 Input X-BAR
      3. 6.5.3 Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
      4. 6.5.4 USB Pin Muxing
      5. 6.5.5 High-Speed SPI Pin Muxing
      6. 6.5.6 High-Speed SSI Pin Muxing
    6. 6.6 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 System Current Consumption (External Supply)
      2. 7.5.2 Operating Mode Test Description
      3. 7.5.3 Current Consumption Graphs
      4. 7.5.4 Reducing Current Consumption
        1. 7.5.4.1 Typical Current Reduction per Disabled Peripheral
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics for ZWT Package
    8. 7.8  Thermal Resistance Characteristics for PTP Package
    9. 7.9  Thermal Design Considerations
    10. 7.10 System
      1. 7.10.1  Power Management Module (PMM)
        1. 7.10.1.1 Introduction
        2. 7.10.1.2 Overview
          1. 7.10.1.2.1 Power Rail Monitors
          2. 7.10.1.2.2 I/O POR (Power-On Reset) Monitor
          3. 7.10.1.2.3 VDD POR (Power-On Reset) Monitor
          4. 7.10.1.2.4 External Supervisor Usage
          5. 7.10.1.2.5 Delay Blocks
        3. 7.10.1.3 External Components
          1. 7.10.1.3.1 Decoupling Capacitors
          2. 7.10.1.3.2 VDDIO Decoupling
        4. 7.10.1.4 Power Sequencing
          1. 7.10.1.4.1 Supply Pins Ganging
          2. 7.10.1.4.2 Signal Pins Power Sequence
          3. 7.10.1.4.3 Supply Pins Power Sequence
            1. 7.10.1.4.3.1 Power Supply Sequence
            2. 7.10.1.4.3.2 Supply Sequencing Summary and Effects of Violations
            3. 7.10.1.4.3.3 Supply Slew Rate
        5. 7.10.1.5 Power Management Module Electrical Data and Timing
          1. 7.10.1.5.1 Power Management Module Operating Conditions
          2. 7.10.1.5.2 Power Management Module Characteristics
      2. 7.10.2  Reset Timing
        1. 7.10.2.1 Reset Sources
        2. 7.10.2.2 Reset Electrical Data and Timing
          1. 7.10.2.2.1 Reset (XRSn) Timing Requirements
          2. 7.10.2.2.2 Reset (XRSn) Switching Characteristics
          3. 7.10.2.2.3 Reset Timing Diagrams
      3. 7.10.3  Clock Specifications
        1. 7.10.3.1 Clock Sources
        2. 7.10.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 7.10.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 7.10.3.2.1.1 Input Clock Frequency
            2. 7.10.3.2.1.2 XTAL Oscillator Characteristics
            3. 7.10.3.2.1.3 X1 Timing Requirements
            4. 7.10.3.2.1.4 AUXCLKIN Timing Requirements
            5. 7.10.3.2.1.5 APLL Characteristics
          2. 7.10.3.2.2 Internal Clock Frequencies
            1. 7.10.3.2.2.1 Internal Clock Frequencies
          3. 7.10.3.2.3 Output Clock Frequency and Switching Characteristics
            1. 7.10.3.2.3.1 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        3. 7.10.3.3 Input Clocks
        4. 7.10.3.4 XTAL Oscillator
          1. 7.10.3.4.1 Introduction
          2. 7.10.3.4.2 Overview
            1. 7.10.3.4.2.1 Electrical Oscillator
              1. 7.10.3.4.2.1.1 Modes of Operation
                1. 7.10.3.4.2.1.1.1 Crystal Mode of Operation
                2. 7.10.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 7.10.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 7.10.3.4.2.2 Quartz Crystal
            3. 7.10.3.4.2.3 GPIO Modes of Operation
          3. 7.10.3.4.3 Functional Operation
            1. 7.10.3.4.3.1 ESR – Effective Series Resistance
            2. 7.10.3.4.3.2 Rneg – Negative Resistance
            3. 7.10.3.4.3.3 Start-up Time
              1. 7.10.3.4.3.3.1 X1/X2 Precondition
            4. 7.10.3.4.3.4 DL – Drive Level
          4. 7.10.3.4.4 How to Choose a Crystal
          5. 7.10.3.4.5 Testing
          6. 7.10.3.4.6 Common Problems and Debug Tips
          7. 7.10.3.4.7 Crystal Oscillator Specifications
            1. 7.10.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 7.10.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 7.10.3.4.7.3 Crystal Oscillator Parameters
            4. 7.10.3.4.7.4 Crystal Oscillator Electrical Characteristics
        5. 7.10.3.5 Internal Oscillators
          1. 7.10.3.5.1 INTOSC Characteristics
      4. 7.10.4  Flash Parameters
        1. 7.10.4.1 Flash Parameters 
        2.       111
      5. 7.10.5  RAM Specifications
      6. 7.10.6  ROM Specifications
      7. 7.10.7  Emulation/JTAG
        1. 7.10.7.1 JTAG Electrical Data and Timing
          1. 7.10.7.1.1 JTAG Timing Requirements
          2. 7.10.7.1.2 JTAG Switching Characteristics
          3. 7.10.7.1.3 JTAG Timing
      8. 7.10.8  GPIO Electrical Data and Timing
        1. 7.10.8.1 GPIO - Output Timing
          1. 7.10.8.1.1 General-Purpose Output Switching Characteristics
          2. 7.10.8.1.2 General-Purpose Output Timing
        2. 7.10.8.2 GPIO - Input Timing
          1. 7.10.8.2.1 General-Purpose Input Timing Requirements
          2. 7.10.8.2.2 Sampling Mode
        3. 7.10.8.3 Sampling Window Width for Input Signals
      9. 7.10.9  Interrupts
        1. 7.10.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 7.10.9.1.1 External Interrupt Timing Requirements
          2. 7.10.9.1.2 External Interrupt Switching Characteristics
          3. 7.10.9.1.3 External Interrupt Timing
      10. 7.10.10 Low-Power Modes
        1. 7.10.10.1 Clock-Gating Low-Power Modes
        2. 7.10.10.2 Low-Power Mode Wakeup Timing
          1. 7.10.10.2.1 IDLE Mode Timing Requirements
          2. 7.10.10.2.2 IDLE Mode Switching Characteristics
          3. 7.10.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 7.10.10.2.4 STANDBY Mode Timing Requirements
          5. 7.10.10.2.5 STANDBY Mode Switching Characteristics
          6. 7.10.10.2.6 STANDBY Entry and Exit Timing Diagram
      11. 7.10.11 External Memory Interface (EMIF)
        1. 7.10.11.1 Asynchronous Memory Support
        2. 7.10.11.2 Synchronous DRAM Support
        3. 7.10.11.3 EMIF Electrical Data and Timing
          1. 7.10.11.3.1 Asynchronous RAM
            1. 7.10.11.3.1.1 EMIF Asynchronous Memory Timing Requirements
            2. 7.10.11.3.1.2 EMIF Asynchronous Memory Switching Characteristics
            3. 7.10.11.3.1.3 EMIF Asynchronous Memory Timing Diagrams
          2. 7.10.11.3.2 Synchronous RAM
            1. 7.10.11.3.2.1 EMIF Synchronous Memory Timing Requirements
            2. 7.10.11.3.2.2 EMIF Synchronous Memory Switching Characteristics
            3. 7.10.11.3.2.3 EMIF Synchronous Memory Timing Diagrams
    11. 7.11 C28x Analog Peripherals
      1. 7.11.1 Analog Subsystem
      2. 7.11.2 Analog-to-Digital Converter (ADC)
        1. 7.11.2.1 Result Register Mapping
        2. 7.11.2.2 ADC Configurability
          1. 7.11.2.2.1 Signal Mode
        3. 7.11.2.3 ADC Electrical Data and Timing
          1. 7.11.2.3.1 ADC Operating Conditions (16-bit Differential)
            1. 7.11.2.3.1.1 ADC Operating Conditions (16-bit Differential) Notes
          2. 7.11.2.3.2 ADC Characteristics (16-bit Differential)
          3. 7.11.2.3.3 ADC Operating Conditions (16-bit Single-Ended)
            1. 7.11.2.3.3.1 ADC Operating Conditions (16-bit Single-Ended) Notes
          4. 7.11.2.3.4 ADC Characteristics (16-bit Single-Ended)
          5. 7.11.2.3.5 ADC Operating Conditions (12-bit Single-Ended)
            1. 7.11.2.3.5.1 ADC Operating Conditions (12-bit Single-Ended) Notes
          6. 7.11.2.3.6 ADC Characteristics (12-bit Single-Ended)
          7. 7.11.2.3.7 ADCEXTSOC Timing Requirements
          8. 7.11.2.3.8 ADC Input Models
            1. 7.11.2.3.8.1 Single-Ended Input Model Parameters (12-bit Resolution)
            2. 7.11.2.3.8.2 Single-Ended Input Model Parameters (16-bit Resolution)
            3. 7.11.2.3.8.3 Single-Ended Input Model
            4. 7.11.2.3.8.4 Differential Input Model Parameters (16-bit Resolution)
            5. 7.11.2.3.8.5 Differential Input Model
          9. 7.11.2.3.9 ADC Timing Diagrams
            1. 7.11.2.3.9.1 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
            2. 7.11.2.3.9.2 ADC Timings in 16-Bit Mode
        4. 7.11.2.4 Temperature Sensor Electrical Data and Timing
          1. 7.11.2.4.1 Temperature Sensor Characteristics
      3. 7.11.3 Comparator Subsystem (CMPSS)
        1. 7.11.3.1 CMPSS Electrical Data and Timing
          1. 7.11.3.1.1 Comparator Electrical Characteristics
          2. 7.11.3.1.2 CMPSS Comparator Input Referred Offset and Hysteresis
          3. 7.11.3.1.3 CMPSS DAC Static Electrical Characteristics
          4. 7.11.3.1.4 CMPSS Illustrative Graphs
          5. 7.11.3.1.5 CMPSS DAC Dynamic Error
      4. 7.11.4 Buffered Digital-to-Analog Converter (DAC)
        1. 7.11.4.1 Buffered DAC Electrical Data and Timing
          1. 7.11.4.1.1 Buffered DAC Operating Conditions
          2. 7.11.4.1.2 Buffered DAC Electrical Characteristics
          3. 7.11.4.1.3 Buffered DAC Notes and Illustrative Graphs
    12. 7.12 C28x Control Peripherals
      1. 7.12.1 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
        1. 7.12.1.1 eCAP Synchronization
        2. 7.12.1.2 eCAP Electrical Data and Timing
          1. 7.12.1.2.1 eCAP Timing Requirements
          2. 7.12.1.2.2 eCAP Switching Charcteristics
        3. 7.12.1.3 HRCAP Electrical Data and Timing
          1. 7.12.1.3.1 HRCAP Switching Characteristics
          2. 7.12.1.3.2 HRCAP Graphs
      2. 7.12.2 Enhanced Pulse Width Modulator (ePWM)
        1. 7.12.2.1 Control Peripherals Synchronization
        2. 7.12.2.2 ePWM Electrical Data and Timing
          1. 7.12.2.2.1 ePWM Timing Requirements
          2. 7.12.2.2.2 ePWM Switching Characteristics
          3. 7.12.2.2.3 Trip-Zone Input Timing
            1. 7.12.2.2.3.1 Trip-Zone Input Timing Requirements
        3. 7.12.2.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 7.12.2.3.1 External ADC Start-of-Conversion Switching Characteristics
      3. 7.12.3 High-Resolution Pulse Width Modulator (HRPWM)
        1. 7.12.3.1 HRPWM Electrical Data and Timing
          1. 7.12.3.1.1 High-Resolution PWM Characteristics
      4. 7.12.4 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.12.4.1 eQEP Electrical Data and Timing
          1. 7.12.4.1.1 eQEP Timing Requirements
          2. 7.12.4.1.2 eQEP Switching Characteristics
      5. 7.12.5 Sigma-Delta Filter Module (SDFM)
        1. 7.12.5.1 SDFM Electrical Data and Timing (Using ASYNC)
          1. 7.12.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
          2. 7.12.5.1.2 SDFM Timing Diagram
    13. 7.13 C28x Communications Peripherals
      1. 7.13.1 Controller Area Network (CAN)
      2. 7.13.2 Fast Serial Interface (FSI)
        1. 7.13.2.1 FSI Transmitter
          1. 7.13.2.1.1 FSITX Electrical Data and Timing
            1. 7.13.2.1.1.1 FSITX Switching Characteristics
            2. 7.13.2.1.1.2 FSITX Timings
        2. 7.13.2.2 FSI Receiver
          1. 7.13.2.2.1 FSIRX Electrical Data and Timing
            1. 7.13.2.2.1.1 FSIRX Timing Requirements
            2. 7.13.2.2.1.2 FSIRX Switching Characteristics
            3. 7.13.2.2.1.3 FSIRX Timing Diagram
        3. 7.13.2.3 SPI Signaling Mode
          1. 7.13.2.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 7.13.2.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 7.13.2.3.1.2 FSITX SPI Signaling Mode Timings
      3. 7.13.3 Inter-Integrated Circuit (I2C)
        1. 7.13.3.1 I2C Electrical Data and Timing
          1. 7.13.3.1.1 I2C Timing Requirements
          2. 7.13.3.1.2 I2C Switching Characteristics
          3. 7.13.3.1.3 I2C Timing Diagram
      4. 7.13.4 Multichannel Buffered Serial Port (McBSP)
        1. 7.13.4.1 McBSP Electrical Data and Timing
          1. 7.13.4.1.1 McBSP Transmit and Receive Timing
            1. 7.13.4.1.1.1 McBSP Timing Requirements
            2. 7.13.4.1.1.2 McBSP Switching Characteristics
            3. 7.13.4.1.1.3 McBSP Receive and Transmit Timing Diagrams
          2. 7.13.4.1.2 McBSP as SPI Master or Slave Timing
            1. 7.13.4.1.2.1 McBSP as SPI Master Timing Requirements
            2. 7.13.4.1.2.2 McBSP as SPI Master Switching Characteristics
            3. 7.13.4.1.2.3 McBSP as SPI Slave Timing Requirements
            4. 7.13.4.1.2.4 McBSP as SPI Slave Switching Characteristics
            5. 7.13.4.1.2.5 McBSP as SPI Master or Slave Timing Diagrams
      5. 7.13.5 Power Management Bus (PMBus)
        1. 7.13.5.1 PMBus Electrical Data and Timing
          1. 7.13.5.1.1 PMBus Electrical Characteristics
          2. 7.13.5.1.2 PMBus Fast Mode Switching Characteristics
          3. 7.13.5.1.3 PMBus Standard Mode Switching Characteristics
      6. 7.13.6 Serial Communications Interface (SCI)
      7. 7.13.7 Serial Peripheral Interface (SPI)
        1. 7.13.7.1 SPI Electrical Data and Timing
          1. 7.13.7.1.1 SPI Master Mode Timings
            1. 7.13.7.1.1.1 SPI Master Mode Timing Requirements
            2. 7.13.7.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            3. 7.13.7.1.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            4. 7.13.7.1.1.4 SPI Master Mode External Timing
          2. 7.13.7.1.2 SPI Slave Mode Timings
            1. 7.13.7.1.2.1 SPI Slave Mode Timing Requirements
            2. 7.13.7.1.2.2 SPI Slave Mode Switching Characteristics
            3. 7.13.7.1.2.3 SPI Slave Mode External Timing
      8. 7.13.8 EtherCAT Slave Controller (ESC)
        1. 7.13.8.1 ESC Features
        2. 7.13.8.2 ESC Subsystem Integrated Features
        3. 7.13.8.3 EtherCAT IP Block Diagram
        4. 7.13.8.4 EtherCAT Electrical Data and Timing
          1. 7.13.8.4.1 EtherCAT Timing Requirements
          2. 7.13.8.4.2 EtherCAT Switching Characteristics
          3. 7.13.8.4.3 EtherCAT Timing Diagrams
      9. 7.13.9 Universal Serial Bus (USB) Controller
        1. 7.13.9.1 USB Electrical Data and Timing
          1. 7.13.9.1.1 USB Input Ports DP and DM Timing Requirements
          2. 7.13.9.1.2 USB Output Ports DP and DM Switching Characteristics
    14. 7.14 Connectivity Manager (CM) Peripherals
      1. 7.14.1 Modular Controller Area Network (MCAN) [CAN FD]
      2. 7.14.2 Ethernet Media Access Controller (EMAC)
        1. 7.14.2.1 MAC Features
          1. 7.14.2.1.1 MAC Tx and Rx Features
          2. 7.14.2.1.2 MAC Tx Features
          3. 7.14.2.1.3 MAC Rx Features
        2. 7.14.2.2 Ethernet Electrical Data and Timing
          1. 7.14.2.2.1 Ethernet Timing Requirements
          2. 7.14.2.2.2 Ethernet Switching Characteristics
          3. 7.14.2.2.3 Ethernet Timing Diagrams
        3. 7.14.2.3 Ethernet REVMII Electrical Data and Timing
          1. 7.14.2.3.1 Ethernet REVMII Timing Requirements
          2. 7.14.2.3.2 Ethernet REVMII Switching Characteristics
      3. 7.14.3 Inter-Integrated Circuit (CM-I2C)
        1. 7.14.3.1 CM-I2C Electrical Data and Timing
          1. 7.14.3.1.1 CM-I2C Timing Requirements
          2. 7.14.3.1.2 CM-I2C Switching Characteristics
          3. 7.14.3.1.3 CM-I2C Timing Diagram
      4. 7.14.4 Synchronous Serial Interface (SSI)
        1. 7.14.4.1 SSI Electrical Data and Timing
          1. 7.14.4.1.1 SSI Timing Requirements
          2. 7.14.4.1.2 SSI Characteristics
          3. 7.14.4.1.3 SSI Timing Diagrams
      5. 7.14.5 Universal Asynchronous Receiver/Transmitter (CM-UART)
      6. 7.14.6 Trace Port Interface Unit (TPIU)
        1. 7.14.6.1 TPIU Electrical Data and Timing
          1. 7.14.6.1.1 Trace Port Switching Characteristics
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Memory
      1. 8.3.1 C28x Memory Map
      2. 8.3.2 C28x Flash Memory Map
      3. 8.3.3 Peripheral Registers Memory Map
      4. 8.3.4 EMIF Chip Select Memory Map
      5. 8.3.5 CM Memory Map
      6. 8.3.6 CM Flash Memory Map
      7. 8.3.7 Peripheral Registers Memory Map (CM)
      8. 8.3.8 Memory Types
        1. 8.3.8.1 Dedicated RAM (Mx and Dx RAM)
        2. 8.3.8.2 Local Shared RAM (LSx RAM)
        3. 8.3.8.3 Global Shared RAM (GSx RAM)
        4. 8.3.8.4 CPU Message RAM (CPU MSGRAM)
        5. 8.3.8.5 CLA Message RAM (CLA MSGRAM)
        6. 8.3.8.6 CLA - DMA Message RAM (CLA-DMA MSGRAM)
        7. 8.3.8.7 CPUx - CM Message RAM (CPUx-CM MSGRAM)
        8. 8.3.8.8 Dedicated RAM (C0/C1 RAM)
        9. 8.3.8.9 Shared RAM (E0 and Sx RAM)
    4. 8.4  Identification
    5. 8.5  Bus Architecture – Peripheral Connectivity
    6. 8.6  Boot ROM and Peripheral Booting
      1. 8.6.1 Device Boot
      2. 8.6.2 Device Boot Modes
      3. 8.6.3 Device Boot Configurations
      4. 8.6.4 GPIO Assignments for CPU1
    7. 8.7  Dual Code Security Module (DCSM)
    8. 8.8  C28x (CPU1/CPU2) Subsystem
      1. 8.8.1  C28x Processor
        1. 8.8.1.1 Floating-Point Unit
        2. 8.8.1.2 Trigonometric Math Unit
        3. 8.8.1.3 Fast Integer Division Unit
        4. 8.8.1.4 VCRC Unit
      2. 8.8.2  Embedded Real-Time Analysis and Diagnostic (ERAD)
      3. 8.8.3  Background CRC-32 (BGCRC)
      4. 8.8.4  Control Law Accelerator (CLA)
      5. 8.8.5  Direct Memory Access (DMA)
      6. 8.8.6  Interprocessor Communication (IPC) Module
      7. 8.8.7  C28x Timers
      8. 8.8.8  Dual-Clock Comparator (DCC)
        1. 8.8.8.1 Features
        2. 8.8.8.2 Mapping of DCCx (DCC0, DCC1, and DCC2) Clock Source Inputs
      9. 8.8.9  Nonmaskable Interrupt With Watchdog Timer (NMIWD)
      10. 8.8.10 Watchdog
      11. 8.8.11 Configurable Logic Block (CLB)
    9. 8.9  Connectivity Manager (CM) Subsystem
      1. 8.9.1  Arm Cortex-M4 Processor
      2. 8.9.2  Nested Vectored Interrupt Controller (NVIC)
      3. 8.9.3  Advance Encryption Standard (AES) Accelerator
      4. 8.9.4  Generic Cyclic Redundancy Check (GCRC) Module
      5. 8.9.5  CM Nonmaskable Interrupt (CMNMI) Module
      6. 8.9.6  Memory Protection Unit (MPU)
      7. 8.9.7  Micro Direct Memory Access (µDMA)
      8. 8.9.8  Watchdog
      9. 8.9.9  CM Clocking
        1. 8.9.9.1 CM Clock Sources
      10. 8.9.10 CM Timers
    10. 8.10 Functional Safety
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application and Implementation
    2. 9.2 Key Device Features
    3. 9.3 Application Information
      1. 9.3.1 Typical Application
        1. 9.3.1.1 High-Voltage Traction Inverter
          1. 9.3.1.1.1 System Block Diagram
          2. 9.3.1.1.2 High-Voltage Traction Inverter Resources
        2. 9.3.1.2 On-Board Charger (OBC)
          1. 9.3.1.2.1 System Block Diagram
          2. 9.3.1.2.2 OBC Resources
        3. 9.3.1.3 Servo Drive Control Module
          1. 9.3.1.3.1 System Block Diagram
          2. 9.3.1.3.2 Servo Drive Control Module Resources
        4. 9.3.1.4 Solar Micro Inverter
          1. 9.3.1.4.1 System Block Diagram
          2. 9.3.1.4.2 Solar Micro Inverter Resources
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Markings
    4. 10.4 Tools and Software
    5. 10.5 Documentation Support
    6. 10.6 Support Resources
    7. 10.7 Trademarks
    8. 10.8 Electrostatic Discharge Caution
    9. 10.9 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.2 Pin Attributes

Table 6-1 Pin Attributes
SIGNAL NAMEMUX POSITION337176PIN TYPEDESCRIPTION
ANALOG
ADCIN14T444IInput 14 to all ADCs. This pin can be used as a general purpose ADCIN pin or it can be used to calibrate all ADCs together (either single-ended or differential) from an external reference
CMPIN4PIComparator 4 positive input
ADCIN15U445IInput 15 to all ADCs. This pin can be used as a general purpose ADCIN pin or it can be used to calibrate all ADCs together (either single-ended or differential) from an external reference
CMPIN4NIComparator 4 negative input
ADCINA0U143IADC-A Input 0. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled.
DACOUTAOBuffered DAC-A Output.
ADCINA1T142IADC-A Input 1. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled.
DACOUTBOBuffered DAC-B Output.
ADCINA2U241IADC-A Input 2
CMPIN1PIComparator 1 positive input
ADCINA3T240IADC-A Input 3
CMPIN1NIComparator 1 negative input
ADCINA4U339IADC-A Input 4
CMPIN2PIComparator 2 positive input
ADCINA5T338IADC-A Input 5
CMPIN2NIComparator 2 negative input
ADCINB0V246IADC-B Input 0. There is a 100-pF capacitor to VSSA on this pin whether used for ADC input or DAC reference which cannot be disabled. If this pin is being used as a reference for the on-chip DACs, place at least a 1-µF capacitor on this pin.
VDACIOptional external reference voltage for on-chip DACs.
ADCINB1W247IADC-B Input 1. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled.
DACOUTCOBuffered DAC-C Output.
ADCINB2V348IADC-B Input 2
CMPIN3PIComparator 3 positive input
ADCINB3W349IADC-B Input 3
CMPIN3NIComparator 3 negative input
ADCINB4V4IADC-B Input 4
ADCINB5W4IADC-B Input 5
ADCINC2R331IADC-C Input 2
CMPIN6PIComparator 6 positive input
ADCINC3P330IADC-C Input 3
CMPIN6NIComparator 6 negative input
ADCINC4R429IADC-C Input 4
CMPIN5PIComparator 5 positive input
ADCINC5P4IADC-C Input 5
CMPIN5NIComparator 5 negative input
ADCIND0T556IADC-D Input 0
CMPIN7PIComparator 7 positive input
ADCIND1U557IADC-D Input 1
CMPIN7NIComparator 7 negative input
ADCIND2T658IADC-D Input 2
CMPIN8PIComparator 8 positive input
ADCIND3U659IADC-D Input 3
CMPIN8NIComparator 8 negative input
ADCIND4T760IADC-D Input 4
ADCIND5U7IADC-D Input 5
VREFHIAV137IADC-A high reference. This voltage must be driven into the pin from external circuitry. Place at least a 2.2-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIA and VREFLOA pins. NOTE: Do not load this pin externally
VREFHIBW553IADC-B high reference. This voltage must be driven into the pin from external circuitry. Place at least a 2.2-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIB and VREFLOB pins. NOTE: Do not load this pin externally
VREFHICR135IADC-C high reference. This voltage must be driven into the pin from external circuitry. Place at least a 2.2-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIC and VREFLOC pins. NOTE: Do not load this pin externally
VREFHIDV555IADC-D high reference. This voltage must be driven into the pin from external circuitry. Place at least a 2.2-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHID and VREFLOD pins. NOTE: Do not load this pin externally
VREFLOAR233IADC-A Low Reference
VREFLOBV650IADC-B Low Reference
VREFLOCP232IADC-C Low Reference
VREFLODW651IADC-D Low Reference
GPIO
GPIO00, 4, 8, 12C8160I/OGeneral-Purpose Input Output 0
EPWM1A1OePWM-1 Output A (High-res available on ePWM1-8)
I2CA_SDA6I/ODI2C-A Open-Drain Bidirectional Data
CM-I2CA_SDA9I/ODCM-I2C-A Open-Drain Bidirectional Data
ESC_GPI010IEtherCAT General-Purpose Input 0
FSITXA_D013OFSITX-A Data Output 0
GPIO10, 4, 8, 12D8161I/OGeneral-Purpose Input Output 1
EPWM1B1OePWM-1 Output B (High-res available on ePWM1-8)
MFSRB3IMcBSP-B Receive Frame Sync
I2CA_SCL6I/ODI2C-A Open-Drain Bidirectional Clock
CM-I2CA_SCL9I/ODCM-I2C-A Open-Drain Bidirectional Clock
ESC_GPI110IEtherCAT General-Purpose Input 1
FSITXA_D113OFSITX-A Data Output 1
GPIO20, 4, 8, 12A7162I/OGeneral-Purpose Input Output 2
EPWM2A1OePWM-2 Output A (High-res available on ePWM1-8)
OUTPUTXBAR15OOutput X-BAR Output 1
I2CB_SDA6I/ODI2C-B Open-Drain Bidirectional Data
ESC_GPI210IEtherCAT General-Purpose Input 2
FSITXA_CLK13OFSITX-A Output Clock
GPIO30, 4, 8, 12B7163I/OGeneral-Purpose Input Output 3
EPWM2B1OePWM-2 Output B (High-res available on ePWM1-8)
OUTPUTXBAR22, 5OOutput X-BAR Output 2
MCLKRB3IMcBSP-B Receive Clock
I2CB_SCL6I/ODI2C-B Open-Drain Bidirectional Clock
ESC_GPI310IEtherCAT General-Purpose Input 3
FSIRXA_D013IFSIRX-A Data Input 0
GPIO40, 4, 8, 12C7164I/OGeneral-Purpose Input Output 4
EPWM3A1OePWM-3 Output A (High-res available on ePWM1-8)
OUTPUTXBAR35OOutput X-BAR Output 3
CANA_TX6OCAN-A Transmit
MCAN_TX9OCAN/CAN FD Transmit
ESC_GPI410IEtherCAT General-Purpose Input 4
FSIRXA_D113IFSIRX-A Data Input 1
GPIO50, 4, 8, 12D7165I/OGeneral-Purpose Input Output 5
EPWM3B1OePWM-3 Output B (High-res available on ePWM1-8)
MFSRA2IMcBSP-A Receive Frame Sync
OUTPUTXBAR33OOutput X-BAR Output 3
CANA_RX6ICAN-A Receive
MCAN_RX9ICAN/CAN FD Receive
ESC_GPI510IEtherCAT General-Purpose Input 5
FSIRXA_CLK13IFSIRX-A Input Clock
GPIO60, 4, 8, 12A6166I/OGeneral-Purpose Input Output 6
EPWM4A1OePWM-4 Output A (High-res available on ePWM1-8)
OUTPUTXBAR42OOutput X-BAR Output 4
EXTSYNCOUT3OExternal ePWM Synchronization Pulse
EQEP3_A5IeQEP-3 Input A
CANB_TX6OCAN-B Transmit
ESC_GPI610IEtherCAT General-Purpose Input 6
FSITXB_D013OFSITX-B Data Output 0
GPIO70, 4, 8, 12B6167I/OGeneral-Purpose Input Output 7
EPWM4B1OePWM-4 Output B (High-res available on ePWM1-8)
MCLKRA2IMcBSP-A Receive Clock
OUTPUTXBAR53OOutput X-BAR Output 5
EQEP3_B5IeQEP-3 Input B
CANB_RX6ICAN-B Receive
ESC_GPI710IEtherCAT General-Purpose Input 7
FSITXB_D113OFSITX-B Data Output 1
GPIO80, 4, 8, 12G218I/OGeneral-Purpose Input Output 8
EPWM5A1OePWM-5 Output A (High-res available on ePWM1-8)
CANB_TX2OCAN-B Transmit
ADCSOCAO3OADC Start of Conversion A Output for External ADC (from ePWM modules)
EQEP3_STROBE5I/OeQEP-3 Strobe
SCIA_TX6OSCI-A Transmit Data
MCAN_TX9OCAN/CAN FD Transmit
ESC_GPO010OEtherCAT General-Purpose Output 0
FSITXB_CLK13OFSITX-B Output Clock
FSITXA_D114OFSITX-A Data Output 1
FSIRXA_D015IFSIRX-A Data Input 0
GPIO90, 4, 8, 12G319I/OGeneral-Purpose Input Output 9
EPWM5B1OePWM-5 Output B (High-res available on ePWM1-8)
SCIB_TX2OSCI-B Transmit Data
OUTPUTXBAR63OOutput X-BAR Output 6
EQEP3_INDEX5I/OeQEP-3 Index
SCIA_RX6ISCI-A Receive Data
ESC_GPO110OEtherCAT General-Purpose Output 1
FSIRXB_D013IFSIRX-B Data Input 0
FSITXA_D014OFSITX-A Data Output 0
FSIRXA_CLK15IFSIRX-A Input Clock
GPIO100, 4, 8, 12B21I/OGeneral-Purpose Input Output 10
EPWM6A1OePWM-6 Output A (High-res available on ePWM1-8)
CANB_RX2ICAN-B Receive
ADCSOCBO3OADC Start of Conversion B Output for External ADC (from ePWM modules)
EQEP1_A5IeQEP-1 Input A
SCIB_TX6OSCI-B Transmit Data
MCAN_RX9ICAN/CAN FD Receive
ESC_GPO210OEtherCAT General-Purpose Output 2
FSIRXB_D113IFSIRX-B Data Input 1
FSITXA_CLK14OFSITX-A Output Clock
FSIRXA_D115IFSIRX-A Data Input 1
GPIO110, 4, 8, 12C12I/OGeneral-Purpose Input Output 11
EPWM6B1OePWM-6 Output B (High-res available on ePWM1-8)
SCIB_RX2, 6ISCI-B Receive Data
OUTPUTXBAR73OOutput X-BAR Output 7
EQEP1_B5IeQEP-1 Input B
ESC_GPO310OEtherCAT General-Purpose Output 3
FSIRXB_CLK13IFSIRX-B Input Clock
FSIRXA_D114IFSIRX-A Data Input 1
GPIO120, 4, 8, 12C24I/OGeneral-Purpose Input Output 12
EPWM7A1OePWM-7 Output A (High-res available on ePWM1-8)
CANB_TX2OCAN-B Transmit
MDXB3OMcBSP-B Transmit Serial Data
EQEP1_STROBE5I/OeQEP-1 Strobe
SCIC_TX6OSCI-C Transmit Data
ESC_GPO410OEtherCAT General-Purpose Output 4
FSIRXC_D013IFSIRX-C Data Input 0
FSIRXA_D014IFSIRX-A Data Input 0
GPIO130, 4, 8, 12D15I/OGeneral-Purpose Input Output 13
EPWM7B1OePWM-7 Output B (High-res available on ePWM1-8)
CANB_RX2ICAN-B Receive
MDRB3IMcBSP-B Receive Serial Data
EQEP1_INDEX5I/OeQEP-1 Index
SCIC_RX6ISCI-C Receive Data
ESC_GPO510OEtherCAT General-Purpose Output 5
FSIRXC_D113IFSIRX-C Data Input 1
FSIRXA_CLK14IFSIRX-A Input Clock
GPIO140, 4, 8, 12D26I/OGeneral-Purpose Input Output 14
EPWM8A1OePWM-8 Output A (High-res available on ePWM1-8)
SCIB_TX2OSCI-B Transmit Data
MCLKXB3OMcBSP-B Transmit Clock
OUTPUTXBAR36OOutput X-BAR Output 3
ESC_GPO610OEtherCAT General-Purpose Output 6
FSIRXC_CLK13IFSIRX-C Input Clock
GPIO150, 4, 8, 12D37I/OGeneral-Purpose Input Output 15
EPWM8B1OePWM-8 Output B (High-res available on ePWM1-8)
SCIB_RX2ISCI-B Receive Data
MFSXB3OMcBSP-B Transmit Frame Sync
OUTPUTXBAR46OOutput X-BAR Output 4
ESC_GPO710OEtherCAT General-Purpose Output 7
FSIRXD_D013IFSIRX-D Data Input 0
GPIO160, 4, 8, 12E18I/OGeneral-Purpose Input Output 16
SPIA_SIMO1I/OSPI-A Slave In, Master Out (SIMO)
CANB_TX2OCAN-B Transmit
OUTPUTXBAR73OOutput X-BAR Output 7
EPWM9A5OePWM-9 Output A (High-res available on ePWM1-8)
SD1_D17ISDFM-1 Channel 1 Data Input
SSIA_TX11I/OSSI-A Serial Data Transmit
FSIRXD_D113IFSIRX-D Data Input 1
GPIO170, 4, 8, 12E29I/OGeneral-Purpose Input Output 17
SPIA_SOMI1I/OSPI-A Slave Out, Master In (SOMI)
CANB_RX2ICAN-B Receive
OUTPUTXBAR83OOutput X-BAR Output 8
EPWM9B5OePWM-9 Output B (High-res available on ePWM1-8)
SD1_C17ISDFM-1 Channel 1 Clock Input
SSIA_RX11I/OSSI-A Serial Data Receive
FSIRXD_CLK13IFSIRX-D Input Clock
GPIO180, 4, 8, 12E310I/OGeneral-Purpose Input Output 18
SPIA_CLK1I/OSPI-A Clock
SCIB_TX2OSCI-B Transmit Data
CANA_RX3ICAN-A Receive
EPWM10A5OePWM-10 Output A (High-res available on ePWM1-8)
SD1_D27ISDFM-1 Channel 2 Data Input
MCAN_RX9ICAN/CAN FD Receive
EMIF1_CS2n10OExternal memory interface 1 chip select 2
SSIA_CLK11I/OSSI-A Clock
FSIRXE_D013IFSIRX-E Data Input 0
GPIO190, 4, 8, 12E412I/OGeneral-Purpose Input Output 19
SPIA_STEn1I/OSPI-A Slave Transmit Enable (STE)
SCIB_RX2ISCI-B Receive Data
CANA_TX3OCAN-A Transmit
EPWM10B5OePWM-10 Output B (High-res available on ePWM1-8)
SD1_C27ISDFM-1 Channel 2 Clock Input
MCAN_TX9OCAN/CAN FD Transmit
EMIF1_CS3n10OExternal memory interface 1 chip select 3
SSIA_FSS11I/OSSI-A Frame Sync
FSIRXE_D113IFSIRX-E Data Input 1
GPIO200, 4, 8, 12F213I/OGeneral-Purpose Input Output 20
EQEP1_A1IeQEP-1 Input A
MDXA2OMcBSP-A Transmit Serial Data
CANB_TX3OCAN-B Transmit
EPWM11A5OePWM-11 Output A (High-res available on ePWM1-8)
SD1_D37ISDFM-1 Channel 3 Data Input
EMIF1_BA010OExternal memory interface 1 bank address 0
TRACE_DATA011OTrace Data 0
FSIRXE_CLK13IFSIRX-E Input Clock
SPIC_SIMO14I/OSPI-C Slave In, Master Out (SIMO)
GPIO210, 4, 8, 12F314I/OGeneral-Purpose Input Output 21
EQEP1_B1IeQEP-1 Input B
MDRA2IMcBSP-A Receive Serial Data
CANB_RX3ICAN-B Receive
EPWM11B5OePWM-11 Output B (High-res available on ePWM1-8)
SD1_C37ISDFM-1 Channel 3 Clock Input
EMIF1_BA110OExternal memory interface 1 bank address 1
TRACE_DATA111OTrace Data 1
FSIRXF_D013IFSIRX-F Data Input 0
SPIC_SOMI14I/OSPI-C Slave Out, Master In (SOMI)
GPIO220, 4, 8, 12J422I/OGeneral-Purpose Input Output 22
EQEP1_STROBE1I/OeQEP-1 Strobe
MCLKXA2OMcBSP-A Transmit Clock
SCIB_TX3OSCI-B Transmit Data
EPWM12A5OePWM-12 Output A (High-res available on ePWM1-8)
SPIB_CLK6I/OSPI-B Clock
SD1_D47ISDFM-1 Channel 4 Data Input
MCAN_TX9OCAN/CAN FD Transmit
EMIF1_RAS10OExternal memory interface 1 row address strobe
TRACE_DATA211OTrace Data 2
FSIRXF_D113IFSIRX-F Data Input 1
SPIC_CLK14I/OSPI-C Clock
GPIO230, 4, 8, 12K423I/OGeneral-Purpose Input Output 23
EQEP1_INDEX1I/OeQEP-1 Index
MFSXA2OMcBSP-A Transmit Frame Sync
SCIB_RX3ISCI-B Receive Data
EPWM12B5OePWM-12 Output B (High-res available on ePWM1-8)
SPIB_STEn6I/OSPI-B Slave Transmit Enable (STE)
SD1_C47ISDFM-1 Channel 4 Clock Input
MCAN_RX9ICAN/CAN FD Receive
EMIF1_CAS10OExternal memory interface 1 column address strobe
TRACE_DATA311OTrace Data 3
FSIRXF_CLK13IFSIRX-F Input Clock
SPIC_STEn14I/OSPI-C Slave Transmit Enable (STE)
GPIO240, 4, 8, 12K324I/OGeneral-Purpose Input Output 24
OUTPUTXBAR11OOutput X-BAR Output 1
EQEP2_A2IeQEP-2 Input A
MDXB3OMcBSP-B Transmit Serial Data
SPIB_SIMO6I/OSPI-B Slave In, Master Out (SIMO)
SD2_D17ISDFM-2 Channel 1 Data Input
PMBUSA_SCL9I/ODPMBus-A Open-Drain Bidirectional Clock
EMIF1_DQM010OExternal memory interface 1 Input/output mask for byte 0
TRACE_CLK11OTrace Clock
EPWM13A13OePWM-13 Output A (High-res available on ePWM1-8)
FSIRXG_D015IFSIRX-G Data Input 0
GPIO250, 4, 8, 12K225I/OGeneral-Purpose Input Output 25
OUTPUTXBAR21OOutput X-BAR Output 2
EQEP2_B2IeQEP-2 Input B
MDRB3IMcBSP-B Receive Serial Data
SPIB_SOMI6I/OSPI-B Slave Out, Master In (SOMI)
SD2_C17ISDFM-2 Channel 1 Clock Input
PMBUSA_SDA9I/ODPMBus-A Open-Drain Bidirectional Data
EMIF1_DQM110OExternal memory interface 1 Input/output mask for byte 1
TRACE_SWO11OTrace Single Wire Out
EPWM13B13OePWM-13 Output B (High-res available on ePWM1-8)
FSITXA_D114OFSITX-A Data Output 1
FSIRXG_D115IFSIRX-G Data Input 1
GPIO260, 4, 8, 12K127I/OGeneral-Purpose Input Output 26
OUTPUTXBAR31, 5OOutput X-BAR Output 3
EQEP2_INDEX2I/OeQEP-2 Index
MCLKXB3OMcBSP-B Transmit Clock
SPIB_CLK6I/OSPI-B Clock
SD2_D27ISDFM-2 Channel 2 Data Input
PMBUSA_ALERT9I/ODPMBus-A Open-Drain Bidirectional Alert Signal
EMIF1_DQM210OExternal memory interface 1 Input/output mask for byte 2
ESC_MDIO_CLK11OEtherCAT MDIO Clock
EPWM14A13OePWM-14 Output A (High-res available on ePWM1-8)
FSITXA_D014OFSITX-A Data Output 0
FSIRXG_CLK15IFSIRX-G Input Clock
GPIO270, 4, 8, 12L128I/OGeneral-Purpose Input Output 27
OUTPUTXBAR41, 5OOutput X-BAR Output 4
EQEP2_STROBE2I/OeQEP-2 Strobe
MFSXB3OMcBSP-B Transmit Frame Sync
SPIB_STEn6I/OSPI-B Slave Transmit Enable (STE)
SD2_C27ISDFM-2 Channel 2 Clock Input
PMBUSA_CTL9IPMBus-A Control Signal
EMIF1_DQM310OExternal memory interface 1 Input/output mask for byte 3
ESC_MDIO_DATA11I/OEtherCAT MDIO Data
EPWM14B13OePWM-14 Output B (High-res available on ePWM1-8)
FSITXA_CLK14OFSITX-A Output Clock
FSIRXH_D015IFSIRX-H Data Input 0
GPIO280, 4, 8, 12V1164I/OGeneral-Purpose Input Output 28
SCIA_RX1ISCI-A Receive Data
EMIF1_CS4n2OExternal memory interface 1 chip select 4
OUTPUTXBAR55OOutput X-BAR Output 5
EQEP3_A6IeQEP-3 Input A
SD2_D37ISDFM-2 Channel 3 Data Input
EMIF1_CS2n9OExternal memory interface 1 chip select 2
EPWM15A13OePWM-15 Output A (High-res available on ePWM1-8)
FSIRXH_D115IFSIRX-H Data Input 1
GPIO290, 4, 8, 12W1165I/OGeneral-Purpose Input Output 29
SCIA_TX1OSCI-A Transmit Data
EMIF1_SDCKE2OExternal memory interface 1 SDRAM clock enable
OUTPUTXBAR65OOutput X-BAR Output 6
EQEP3_B6IeQEP-3 Input B
SD2_C37ISDFM-2 Channel 3 Clock Input
EMIF1_CS3n9OExternal memory interface 1 chip select 3
ESC_LATCH010IEtherCAT LatchSignal Input 0
ESC_I2C_SDA11I/OCEtherCAT I2C Data
EPWM15B13OePWM-15 Output B (High-res available on ePWM1-8)
ESC_SYNC014OEtherCAT SyncSignal Output 0
FSIRXH_CLK15IFSIRX-H Input Clock
GPIO300, 4, 8, 12T1163I/OGeneral-Purpose Input Output 30
CANA_RX1ICAN-A Receive
EMIF1_CLK2OExternal memory interface 1 clock
MCAN_RX3ICAN/CAN FD Receive
OUTPUTXBAR75OOutput X-BAR Output 7
EQEP3_STROBE6I/OeQEP-3 Strobe
SD2_D47ISDFM-2 Channel 4 Data Input
EMIF1_CS4n9OExternal memory interface 1 chip select 4
ESC_LATCH110IEtherCAT LatchSignal Input 1
ESC_I2C_SCL11I/OCEtherCAT I2C Clock
EPWM16A13OePWM-16 Output A (High-res available on ePWM1-8)
ESC_SYNC114OEtherCAT SyncSignal Output 1
SPID_SIMO15I/OSPI-D Slave In, Master Out (SIMO)
GPIO310, 4, 8, 12U1166I/OGeneral-Purpose Input Output 31
CANA_TX1OCAN-A Transmit
EMIF1_WEn2OExternal memory interface 1 write enable
MCAN_TX3OCAN/CAN FD Transmit
OUTPUTXBAR85OOutput X-BAR Output 8
EQEP3_INDEX6I/OeQEP-3 Index
SD2_C47ISDFM-2 Channel 4 Clock Input
EMIF1_RNW9OExternal memory interface 1 read not write
I2CA_SDA10I/ODI2C-A Open-Drain Bidirectional Data
CM-I2CA_SDA11I/ODCM-I2C-A Open-Drain Bidirectional Data
EPWM16B13OePWM-16 Output B (High-res available on ePWM1-8)
SPID_SOMI15I/OSPI-D Slave Out, Master In (SOMI)
GPIO320, 4, 8, 12U1367I/OGeneral-Purpose Input Output 32
I2CA_SDA1I/ODI2C-A Open-Drain Bidirectional Data
EMIF1_CS0n2OExternal memory interface 1 chip select 0
SPIA_SIMO3I/OSPI-A Slave In, Master Out (SIMO)
CLB_OUTPUTXBAR17OCLB Output X-BAR Output 1
EMIF1_OEn9OExternal memory interface 1 output enable
I2CA_SCL10I/ODI2C-A Open-Drain Bidirectional Clock
CM-I2CA_SCL11I/ODCM-I2C-A Open-Drain Bidirectional Clock
SPID_CLK15I/OSPI-D Clock
GPIO330, 4, 8, 12T1369I/OGeneral-Purpose Input Output 33
I2CA_SCL1I/ODI2C-A Open-Drain Bidirectional Clock
EMIF1_RNW2OExternal memory interface 1 read not write
SPIA_SOMI3I/OSPI-A Slave Out, Master In (SOMI)
CLB_OUTPUTXBAR27OCLB Output X-BAR Output 2
EMIF1_BA09OExternal memory interface 1 bank address 0
SPID_STEn15I/OSPI-D Slave Transmit Enable (STE)
GPIO340, 4, 8, 12U1470I/OGeneral-Purpose Input Output 34
OUTPUTXBAR11OOutput X-BAR Output 1
EMIF1_CS2n2OExternal memory interface 1 chip select 2
SPIA_CLK3I/OSPI-A Clock
I2CB_SDA6I/ODI2C-B Open-Drain Bidirectional Data
CLB_OUTPUTXBAR37OCLB Output X-BAR Output 3
EMIF1_BA19OExternal memory interface 1 bank address 1
ESC_LATCH010IEtherCAT LatchSignal Input 0
ENET_MII_CRS11IEMAC MII carrier sense
SCIA_TX13OSCI-A Transmit Data
ESC_SYNC014OEtherCAT SyncSignal Output 0
GPIO350, 4, 8, 12T1471I/OGeneral-Purpose Input Output 35
SCIA_RX1ISCI-A Receive Data
EMIF1_CS3n2OExternal memory interface 1 chip select 3
SPIA_STEn3I/OSPI-A Slave Transmit Enable (STE)
I2CB_SCL6I/ODI2C-B Open-Drain Bidirectional Clock
CLB_OUTPUTXBAR47OCLB Output X-BAR Output 4
EMIF1_A09OExternal memory interface 1 address line 0
ESC_LATCH110IEtherCAT LatchSignal Input 1
ENET_MII_COL11IEMAC MII collision detect
ESC_SYNC114OEtherCAT SyncSignal Output 1
GPIO360, 4, 8, 12V1683I/OGeneral-Purpose Input Output 36
SCIA_TX1OSCI-A Transmit Data
EMIF1_WAIT2IExternal memory interface 1 Asynchronous SRAM WAIT
CANA_RX6ICAN-A Receive
CLB_OUTPUTXBAR57OCLB Output X-BAR Output 5
EMIF1_A19OExternal memory interface 1 address line 1
MCAN_RX10ICAN/CAN FD Receive
SD1_D113ISDFM-1 Channel 1 Data Input
GPIO370, 4, 8, 12U1684I/OGeneral-Purpose Input Output 37
OUTPUTXBAR21OOutput X-BAR Output 2
EMIF1_OEn2OExternal memory interface 1 output enable
CANA_TX6OCAN-A Transmit
CLB_OUTPUTXBAR67OCLB Output X-BAR Output 6
EMIF1_A29OExternal memory interface 1 address line 2
MCAN_TX10OCAN/CAN FD Transmit
SD1_D213ISDFM-1 Channel 2 Data Input
GPIO380, 4, 8, 12T1685I/OGeneral-Purpose Input Output 38
EMIF1_A02OExternal memory interface 1 address line 0
SCIC_TX5OSCI-C Transmit Data
CANB_TX6OCAN-B Transmit
CLB_OUTPUTXBAR77OCLB Output X-BAR Output 7
EMIF1_A39OExternal memory interface 1 address line 3
ENET_MII_RX_DV10IEMAC MII receive data valid (or) RMII carrier sense/ receive data valid
ENET_MII_CRS11IEMAC MII carrier sense
SD1_D313ISDFM-1 Channel 3 Data Input
GPIO390, 4, 8, 12W1786I/OGeneral-Purpose Input Output 39
EMIF1_A12OExternal memory interface 1 address line 1
SCIC_RX5ISCI-C Receive Data
CANB_RX6ICAN-B Receive
CLB_OUTPUTXBAR87OCLB Output X-BAR Output 8
EMIF1_A49OExternal memory interface 1 address line 4
ENET_MII_RX_ERR10IEMAC MII / RMII receive error
ENET_MII_COL11IEMAC MII collision detect
SD1_D413ISDFM-1 Channel 4 Data Input
GPIO400, 4, 8, 12V1787I/OGeneral-Purpose Input Output 40
EMIF1_A22OExternal memory interface 1 address line 2
I2CB_SDA6I/ODI2C-B Open-Drain Bidirectional Data
ENET_MII_CRS11IEMAC MII carrier sense
ESC_I2C_SDA14I/OCEtherCAT I2C Data
GPIO410, 4, 8, 12U1789I/OGeneral-Purpose Input Output 41
EMIF1_A32OExternal memory interface 1 address line 3
I2CB_SCL6I/ODI2C-B Open-Drain Bidirectional Clock
ENET_REVMII_MDIO_RST10IEMAC REVMII MDIO reset
ENET_MII_COL11IEMAC MII collision detect
ESC_I2C_SCL14I/OCEtherCAT I2C Clock
GPIO420, 4, 8, 12D19130I/OGeneral-Purpose Input Output 42
I2CA_SDA6I/ODI2C-A Open-Drain Bidirectional Data
ENET_MDIO_CLK10I/OEMAC management data clock, Output in MII/RMII modes, Input in RevMII mode
UARTA_TX11I/OUART-A Serial Data Transmit
SCIA_TX15OSCI-A Transmit Data
USB0DMALTOUSB-0 PHY differential data
GPIO430, 4, 8, 12C19131I/OGeneral-Purpose Input Output 43
I2CA_SCL6I/ODI2C-A Open-Drain Bidirectional Clock
ENET_MDIO_DATA10I/OEMAC management data
UARTA_RX11I/OUART-A Serial Data Receive
SCIA_RX15ISCI-A Receive Data
USB0DPALTOUSB-0 PHY differential data
GPIO440, 4, 8, 12K18113I/OGeneral-Purpose Input Output 44
EMIF1_A42OExternal memory interface 1 address line 4
ENET_MII_TX_CLK11IEMAC MII transmit clock
ESC_TX1_CLK14IEtherCAT MII Transmit-1 Clock
GPIO450, 4, 8, 12K19115I/OGeneral-Purpose Input Output 45
EMIF1_A52OExternal memory interface 1 address line 5
ENET_MII_TX_EN11OEMAC MII / RMII transmit enable
ESC_TX1_ENA14OEtherCAT MII Transmit-1 Enable
GPIO460, 4, 8, 12E19128I/OGeneral-Purpose Input Output 46
EMIF1_A62OExternal memory interface 1 address line 6
SCID_RX6ISCI-D Receive Data
ENET_MII_TX_ERR11OEMAC MII transmit error
ESC_MDIO_CLK14OEtherCAT MDIO Clock
GPIO470, 4, 8, 12E18129I/OGeneral-Purpose Input Output 47
EMIF1_A72OExternal memory interface 1 address line 7
SCID_TX6OSCI-D Transmit Data
ENET_PPS011OEMAC Pulse Per Second Output 0
ESC_MDIO_DATA14I/OEtherCAT MDIO Data
GPIO480, 4, 8, 12R1690I/OGeneral-Purpose Input Output 48
OUTPUTXBAR31OOutput X-BAR Output 3
EMIF1_A82OExternal memory interface 1 address line 8
SCIA_TX6OSCI-A Transmit Data
SD1_D17ISDFM-1 Channel 1 Data Input
ENET_PPS111OEMAC Pulse Per Second Output 1
ESC_PHY_CLK14OEtherCAT PHY Clock
GPIO490, 4, 8, 12R1793I/OGeneral-Purpose Input Output 49
OUTPUTXBAR41OOutput X-BAR Output 4
EMIF1_A92OExternal memory interface 1 address line 9
SCIA_RX6ISCI-A Receive Data
SD1_C17ISDFM-1 Channel 1 Clock Input
EMIF1_A59OExternal memory interface 1 address line 5
ENET_MII_RX_CLK11IEMAC MII receive clock
SD2_D113ISDFM-2 Channel 1 Data Input
FSITXA_D014OFSITX-A Data Output 0
GPIO500, 4, 8, 12R1894I/OGeneral-Purpose Input Output 50
EQEP1_A1IeQEP-1 Input A
EMIF1_A102OExternal memory interface 1 address line 10
SPIC_SIMO6I/OSPI-C Slave In, Master Out (SIMO)
SD1_D27ISDFM-1 Channel 2 Data Input
EMIF1_A69OExternal memory interface 1 address line 6
ENET_MII_RX_DV11IEMAC MII receive data valid (or) RMII carrier sense/ receive data valid
SD2_D213ISDFM-2 Channel 2 Data Input
FSITXA_D114OFSITX-A Data Output 1
GPIO510, 4, 8, 12R1995I/OGeneral-Purpose Input Output 51
EQEP1_B1IeQEP-1 Input B
EMIF1_A112OExternal memory interface 1 address line 11
SPIC_SOMI6I/OSPI-C Slave Out, Master In (SOMI)
SD1_C27ISDFM-1 Channel 2 Clock Input
EMIF1_A79OExternal memory interface 1 address line 7
ENET_MII_RX_ERR11IEMAC MII / RMII receive error
SD2_D313ISDFM-2 Channel 3 Data Input
FSITXA_CLK14OFSITX-A Output Clock
GPIO520, 4, 8, 12P1696I/OGeneral-Purpose Input Output 52
EQEP1_STROBE1I/OeQEP-1 Strobe
EMIF1_A122OExternal memory interface 1 address line 12
SPIC_CLK6I/OSPI-C Clock
SD1_D37ISDFM-1 Channel 3 Data Input
EMIF1_A89OExternal memory interface 1 address line 8
ENET_MII_RX_DATA011IEMAC MII / RMII receive data 0
SD2_D413ISDFM-2 Channel 4 Data Input
FSIRXA_D014IFSIRX-A Data Input 0
GPIO530, 4, 8, 12P1797I/OGeneral-Purpose Input Output 53
EQEP1_INDEX1I/OeQEP-1 Index
EMIF1_D312I/OExternal memory interface 1 data line 31
EMIF2_D153I/OExternal memory interface 2 data line 15
SPIC_STEn6I/OSPI-C Slave Transmit Enable (STE)
SD1_C37ISDFM-1 Channel 3 Clock Input
EMIF1_A99OExternal memory interface 1 address line 9
ENET_MII_RX_DATA111IEMAC MII / RMII receive data 1
SD1_C113ISDFM-1 Channel 1 Clock Input
FSIRXA_D114IFSIRX-A Data Input 1
GPIO540, 4, 8, 12P1898I/OGeneral-Purpose Input Output 54
SPIA_SIMO1I/OSPI-A Slave In, Master Out (SIMO)
EMIF1_D302I/OExternal memory interface 1 data line 30
EMIF2_D143I/OExternal memory interface 2 data line 14
EQEP2_A5IeQEP-2 Input A
SCIB_TX6OSCI-B Transmit Data
SD1_D47ISDFM-1 Channel 4 Data Input
EMIF1_A109OExternal memory interface 1 address line 10
ENET_MII_RX_DATA211IEMAC MII receive data 2
SD1_C213ISDFM-1 Channel 2 Clock Input
FSIRXA_CLK14IFSIRX-A Input Clock
SSIA_TX15I/OSSI-A Serial Data Transmit
GPIO550, 4, 8, 12P19100I/OGeneral-Purpose Input Output 55
SPIA_SOMI1I/OSPI-A Slave Out, Master In (SOMI)
EMIF1_D292I/OExternal memory interface 1 data line 29
EMIF2_D133I/OExternal memory interface 2 data line 13
EQEP2_B5IeQEP-2 Input B
SCIB_RX6ISCI-B Receive Data
SD1_C47ISDFM-1 Channel 4 Clock Input
EMIF1_D09I/OExternal memory interface 1 data line 0
ENET_MII_RX_DATA311IEMAC MII receive data 3
SD1_C313ISDFM-1 Channel 3 Clock Input
FSITXB_D014OFSITX-B Data Output 0
SSIA_RX15I/OSSI-A Serial Data Receive
GPIO560, 4, 8, 12N16101I/OGeneral-Purpose Input Output 56
SPIA_CLK1I/OSPI-A Clock
EMIF1_D282I/OExternal memory interface 1 data line 28
EMIF2_D123I/OExternal memory interface 2 data line 12
EQEP2_STROBE5I/OeQEP-2 Strobe
SCIC_TX6OSCI-C Transmit Data
SD2_D17ISDFM-2 Channel 1 Data Input
EMIF1_D19I/OExternal memory interface 1 data line 1
I2CA_SDA10I/ODI2C-A Open-Drain Bidirectional Data
ENET_MII_TX_EN11OEMAC MII / RMII transmit enable
SD1_C413ISDFM-1 Channel 4 Clock Input
FSITXB_CLK14OFSITX-B Output Clock
SSIA_CLK15I/OSSI-A Clock
GPIO570, 4, 8, 12N18102I/OGeneral-Purpose Input Output 57
SPIA_STEn1I/OSPI-A Slave Transmit Enable (STE)
EMIF1_D272I/OExternal memory interface 1 data line 27
EMIF2_D113I/OExternal memory interface 2 data line 11
EQEP2_INDEX5I/OeQEP-2 Index
SCIC_RX6ISCI-C Receive Data
SD2_C17ISDFM-2 Channel 1 Clock Input
EMIF1_D29I/OExternal memory interface 1 data line 2
I2CA_SCL10I/ODI2C-A Open-Drain Bidirectional Clock
ENET_MII_TX_ERR11OEMAC MII transmit error
FSITXB_D114OFSITX-B Data Output 1
SSIA_FSS15I/OSSI-A Frame Sync
GPIO580, 4, 8, 12N17103I/OGeneral-Purpose Input Output 58
MCLKRA1IMcBSP-A Receive Clock
EMIF1_D262I/OExternal memory interface 1 data line 26
EMIF2_D103I/OExternal memory interface 2 data line 10
OUTPUTXBAR15OOutput X-BAR Output 1
SPIB_CLK6I/OSPI-B Clock
SD2_D27ISDFM-2 Channel 2 Data Input
EMIF1_D39I/OExternal memory interface 1 data line 3
ESC_LED_LINK0_ACTIVE10OEtherCAT Link-0 Active
ENET_MII_TX_CLK11IEMAC MII transmit clock
SD2_C213ISDFM-2 Channel 2 Clock Input
FSIRXB_D014IFSIRX-B Data Input 0
SPIA_SIMO15I/OSPI-A Slave In, Master Out (SIMO)
GPIO590, 4, 8, 12M16104I/OGeneral-Purpose Input Output 59
MFSRA1IMcBSP-A Receive Frame Sync
EMIF1_D252I/OExternal memory interface 1 data line 25
EMIF2_D93I/OExternal memory interface 2 data line 9
OUTPUTXBAR25OOutput X-BAR Output 2
SPIB_STEn6I/OSPI-B Slave Transmit Enable (STE)
SD2_C27ISDFM-2 Channel 2 Clock Input
EMIF1_D49I/OExternal memory interface 1 data line 4
ESC_LED_LINK1_ACTIVE10OEtherCAT Link-1 Active
ENET_MII_TX_DATA011OEMAC MII / RMII transmit data 0
SD2_C313ISDFM-2 Channel 3 Clock Input
FSIRXB_D114IFSIRX-B Data Input 1
SPIA_SOMI15I/OSPI-A Slave Out, Master In (SOMI)
GPIO600, 4, 8, 12M17105I/OGeneral-Purpose Input Output 60
MCLKRB1IMcBSP-B Receive Clock
EMIF1_D242I/OExternal memory interface 1 data line 24
EMIF2_D83I/OExternal memory interface 2 data line 8
OUTPUTXBAR35OOutput X-BAR Output 3
SPIB_SIMO6I/OSPI-B Slave In, Master Out (SIMO)
SD2_D37ISDFM-2 Channel 3 Data Input
EMIF1_D59I/OExternal memory interface 1 data line 5
ESC_LED_ERR10OEtherCAT Error LED
ENET_MII_TX_DATA111OEMAC MII / RMII transmit data 1
SD2_C413ISDFM-2 Channel 4 Clock Input
FSIRXB_CLK14IFSIRX-B Input Clock
SPIA_CLK15I/OSPI-A Clock
GPIO610, 4, 8, 12L16107I/OGeneral-Purpose Input Output 61
MFSRB1IMcBSP-B Receive Frame Sync
EMIF1_D232I/OExternal memory interface 1 data line 23
EMIF2_D73I/OExternal memory interface 2 data line 7
OUTPUTXBAR45OOutput X-BAR Output 4
SPIB_SOMI6I/OSPI-B Slave Out, Master In (SOMI)
SD2_C37ISDFM-2 Channel 3 Clock Input
EMIF1_D69I/OExternal memory interface 1 data line 6
ESC_LED_RUN10OEtherCAT Run LED
ENET_MII_TX_DATA211OEMAC MII transmit data 2
CANA_RX14ICAN-A Receive
SPIA_STEn15I/OSPI-A Slave Transmit Enable (STE)
GPIO620, 4, 8, 12J17108I/OGeneral-Purpose Input Output 62
SCIC_RX1ISCI-C Receive Data
EMIF1_D222I/OExternal memory interface 1 data line 22
EMIF2_D63I/OExternal memory interface 2 data line 6
EQEP3_A5IeQEP-3 Input A
CANA_RX6ICAN-A Receive
SD2_D47ISDFM-2 Channel 4 Data Input
EMIF1_D79I/OExternal memory interface 1 data line 7
ESC_LED_STATE_RUN10OEtherCAT State Run
ENET_MII_TX_DATA311OEMAC MII transmit data 3
CANA_TX14OCAN-A Transmit
GPIO630, 4, 8, 12J16109I/OGeneral-Purpose Input Output 63
SCIC_TX1OSCI-C Transmit Data
EMIF1_D212I/OExternal memory interface 1 data line 21
EMIF2_D53I/OExternal memory interface 2 data line 5
EQEP3_B5IeQEP-3 Input B
CANA_TX6OCAN-A Transmit
SD2_C47ISDFM-2 Channel 4 Clock Input
SSIA_TX9I/OSSI-A Serial Data Transmit
ENET_MII_RX_DATA011IEMAC MII / RMII receive data 0
SD1_D113ISDFM-1 Channel 1 Data Input
ESC_RX1_DATA014IEtherCAT MII Receive-1 Data-0
SPIB_SIMO15I/OSPI-B Slave In, Master Out (SIMO)
GPIO640, 4, 8, 12L17110I/OGeneral-Purpose Input Output 64
EMIF1_D202I/OExternal memory interface 1 data line 20
EMIF2_D43I/OExternal memory interface 2 data line 4
EQEP3_STROBE5I/OeQEP-3 Strobe
SCIA_RX6ISCI-A Receive Data
SSIA_RX9I/OSSI-A Serial Data Receive
ENET_MII_RX_DV10IEMAC MII receive data valid (or) RMII carrier sense/ receive data valid
ENET_MII_RX_DATA111IEMAC MII / RMII receive data 1
SD1_C113ISDFM-1 Channel 1 Clock Input
ESC_RX1_DATA114IEtherCAT MII Receive-1 Data-1
SPIB_SOMI15I/OSPI-B Slave Out, Master In (SOMI)
GPIO650, 4, 8, 12K16111I/OGeneral-Purpose Input Output 65
EMIF1_D192I/OExternal memory interface 1 data line 19
EMIF2_D33I/OExternal memory interface 2 data line 3
EQEP3_INDEX5I/OeQEP-3 Index
SCIA_TX6OSCI-A Transmit Data
SSIA_CLK9I/OSSI-A Clock
ENET_MII_RX_ERR10IEMAC MII / RMII receive error
ENET_MII_RX_DATA211IEMAC MII receive data 2
SD1_D213ISDFM-1 Channel 2 Data Input
ESC_RX1_DATA214IEtherCAT MII Receive-1 Data-2
SPIB_CLK15I/OSPI-B Clock
GPIO660, 4, 8, 12K17112I/OGeneral-Purpose Input Output 66
EMIF1_D182I/OExternal memory interface 1 data line 18
EMIF2_D23I/OExternal memory interface 2 data line 2
I2CB_SDA6I/ODI2C-B Open-Drain Bidirectional Data
SSIA_FSS9I/OSSI-A Frame Sync
ENET_MII_RX_DATA010IEMAC MII / RMII receive data 0
ENET_MII_RX_DATA311IEMAC MII receive data 3
SD1_C213ISDFM-1 Channel 2 Clock Input
ESC_RX1_DATA314IEtherCAT MII Receive-1 Data-3
SPIB_STEn15I/OSPI-B Slave Transmit Enable (STE)
GPIO670, 4, 8, 12B19132I/OGeneral-Purpose Input Output 67
EMIF1_D172I/OExternal memory interface 1 data line 17
EMIF2_D13I/OExternal memory interface 2 data line 1
ENET_MII_RX_CLK10IEMAC MII receive clock
ENET_REVMII_MDIO_RST11IEMAC REVMII MDIO reset
SD1_D313ISDFM-1 Channel 3 Data Input
GPIO680, 4, 8, 12C18133I/OGeneral-Purpose Input Output 68
EMIF1_D162I/OExternal memory interface 1 data line 16
EMIF2_D03I/OExternal memory interface 2 data line 0
ENET_MII_INTR11I/OEMAC PHY interrupt, Input in MII/RMII mode, Output in RevMII mode
SD1_C313ISDFM-1 Channel 3 Clock Input
ESC_PHY1_LINKSTATUS14IEtherCAT PHY-1 Link Status
GPIO690, 4, 8, 12B18134I/OGeneral-Purpose Input Output 69
EMIF1_D152I/OExternal memory interface 1 data line 15
I2CB_SCL6I/ODI2C-B Open-Drain Bidirectional Clock
ENET_MII_TX_EN10OEMAC MII / RMII transmit enable
ENET_MII_RX_CLK11IEMAC MII receive clock
SD1_D413ISDFM-1 Channel 4 Data Input
ESC_RX1_CLK14IEtherCAT MII Receive-1 Clock
SPIC_SIMO15I/OSPI-C Slave In, Master Out (SIMO)
GPIO700, 4, 8, 12A17135I/OGeneral-Purpose Input Output 70
EMIF1_D142I/OExternal memory interface 1 data line 14
CANA_RX5ICAN-A Receive
SCIB_TX6OSCI-B Transmit Data
MCAN_RX9ICAN/CAN FD Receive
ENET_MII_RX_DV11IEMAC MII receive data valid (or) RMII carrier sense/ receive data valid
SD1_C413ISDFM-1 Channel 4 Clock Input
ESC_RX1_DV14IEtherCAT MII Receive-1 Data Valid
SPIC_SOMI15I/OSPI-C Slave Out, Master In (SOMI)
GPIO710, 4, 8, 12B17136I/OGeneral-Purpose Input Output 71
EMIF1_D132I/OExternal memory interface 1 data line 13
CANA_TX5OCAN-A Transmit
SCIB_RX6ISCI-B Receive Data
MCAN_TX9OCAN/CAN FD Transmit
ENET_MII_RX_DATA010IEMAC MII / RMII receive data 0
ENET_MII_RX_ERR11IEMAC MII / RMII receive error
ESC_RX1_ERR14IEtherCAT MII Receive-1 Error
SPIC_CLK15I/OSPI-C Clock
GPIO720, 4, 8, 12B16139I/OGeneral-Purpose Input Output 72
EMIF1_D122I/OExternal memory interface 1 data line 12
CANB_TX5OCAN-B Transmit
SCIC_TX6OSCI-C Transmit Data
ENET_MII_RX_DATA110IEMAC MII / RMII receive data 1
ENET_MII_TX_DATA311OEMAC MII transmit data 3
ESC_TX1_DATA314OEtherCAT MII Transmit-1 Data-3
SPIC_STEn15I/OSPI-C Slave Transmit Enable (STE)
GPIO730, 4, 8, 12A16140I/OGeneral-Purpose Input Output 73
EMIF1_D112I/OExternal memory interface 1 data line 11
XCLKOUT3OExternal Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
CANB_RX5ICAN-B Receive
SCIC_RX6ISCI-C Receive Data
ENET_RMII_CLK10I/OEMAC RMII clock
ENET_MII_TX_DATA211OEMAC MII transmit data 2
SD2_D213ISDFM-2 Channel 2 Data Input
ESC_TX1_DATA214OEtherCAT MII Transmit-1 Data-2
GPIO740, 4, 8, 12C17141I/OGeneral-Purpose Input Output 74
EMIF1_D102I/OExternal memory interface 1 data line 10
MCAN_TX9OCAN/CAN FD Transmit
ENET_MII_TX_DATA111OEMAC MII / RMII transmit data 1
SD2_C213ISDFM-2 Channel 2 Clock Input
ESC_TX1_DATA114OEtherCAT MII Transmit-1 Data-1
GPIO750, 4, 8, 12D16142I/OGeneral-Purpose Input Output 75
EMIF1_D92I/OExternal memory interface 1 data line 9
MCAN_RX9ICAN/CAN FD Receive
ENET_MII_TX_DATA011OEMAC MII / RMII transmit data 0
SD2_D313ISDFM-2 Channel 3 Data Input
ESC_TX1_DATA014OEtherCAT MII Transmit-1 Data-0
GPIO760, 4, 8, 12C16143I/OGeneral-Purpose Input Output 76
EMIF1_D82I/OExternal memory interface 1 data line 8
SCID_TX6OSCI-D Transmit Data
ENET_MII_RX_ERR10IEMAC MII / RMII receive error
SD2_C313ISDFM-2 Channel 3 Clock Input
ESC_PHY_RESETn14OEtherCAT PHY Active Low Reset
GPIO770, 4, 8, 12A15144I/OGeneral-Purpose Input Output 77
EMIF1_D72I/OExternal memory interface 1 data line 7
SCID_RX6ISCI-D Receive Data
SD2_D413ISDFM-2 Channel 4 Data Input
ESC_RX0_CLK14IEtherCAT MII Receive-0 Clock
GPIO780, 4, 8, 12B15145I/OGeneral-Purpose Input Output 78
EMIF1_D62I/OExternal memory interface 1 data line 6
EQEP2_A6IeQEP-2 Input A
SD2_C413ISDFM-2 Channel 4 Clock Input
ESC_RX0_DV14IEtherCAT MII Receive-0 Data Valid
GPIO790, 4, 8, 12C15146I/OGeneral-Purpose Input Output 79
EMIF1_D52I/OExternal memory interface 1 data line 5
EQEP2_B6IeQEP-2 Input B
SD2_D113ISDFM-2 Channel 1 Data Input
ESC_RX0_ERR14IEtherCAT MII Receive-0 Error
GPIO800, 4, 8, 12D15148I/OGeneral-Purpose Input Output 80
EMIF1_D42I/OExternal memory interface 1 data line 4
EQEP2_STROBE6I/OeQEP-2 Strobe
SD2_C113ISDFM-2 Channel 1 Clock Input
ESC_RX0_DATA014IEtherCAT MII Receive-0 Data-0
GPIO810, 4, 8, 12A14149I/OGeneral-Purpose Input Output 81
EMIF1_D32I/OExternal memory interface 1 data line 3
EQEP2_INDEX6I/OeQEP-2 Index
ESC_RX0_DATA114IEtherCAT MII Receive-0 Data-1
GPIO820, 4, 8, 12B14150I/OGeneral-Purpose Input Output 82
EMIF1_D22I/OExternal memory interface 1 data line 2
ESC_RX0_DATA214IEtherCAT MII Receive-0 Data-2
GPIO830, 4, 8, 12C14151I/OGeneral-Purpose Input Output 83
EMIF1_D12I/OExternal memory interface 1 data line 1
ESC_RX0_DATA314IEtherCAT MII Receive-0 Data-3
GPIO840, 4, 8, 12A11154I/OGeneral-Purpose Input Output 84
SCIA_TX5OSCI-A Transmit Data
MDXB6OMcBSP-B Transmit Serial Data
UARTA_TX11I/OUART-A Serial Data Transmit
ESC_TX0_ENA14OEtherCAT MII Transmit-0 Enable
MDXA15OMcBSP-A Transmit Serial Data
GPIO850, 4, 8, 12B11155I/OGeneral-Purpose Input Output 85
EMIF1_D02I/OExternal memory interface 1 data line 0
SCIA_RX5ISCI-A Receive Data
MDRB6IMcBSP-B Receive Serial Data
UARTA_RX11I/OUART-A Serial Data Receive
ESC_TX0_CLK14IEtherCAT MII Transmit-0 Clock
MDRA15IMcBSP-A Receive Serial Data
GPIO860, 4, 8, 12C11156I/OGeneral-Purpose Input Output 86
EMIF1_A132OExternal memory interface 1 address line 13
EMIF1_CAS3OExternal memory interface 1 column address strobe
SCIB_TX5OSCI-B Transmit Data
MCLKXB6OMcBSP-B Transmit Clock
ESC_PHY0_LINKSTATUS14IEtherCAT PHY-0 Link Status
MCLKXA15OMcBSP-A Transmit Clock
GPIO870, 4, 8, 12D11157I/OGeneral-Purpose Input Output 87
EMIF1_A142OExternal memory interface 1 address line 14
EMIF1_RAS3OExternal memory interface 1 row address strobe
SCIB_RX5ISCI-B Receive Data
MFSXB6OMcBSP-B Transmit Frame Sync
EMIF1_DQM39OExternal memory interface 1 Input/output mask for byte 3
ESC_TX0_DATA014OEtherCAT MII Transmit-0 Data-0
MFSXA15OMcBSP-A Transmit Frame Sync
GPIO880, 4, 8, 12C6170I/OGeneral-Purpose Input Output 88
EMIF1_A152OExternal memory interface 1 address line 15
EMIF1_DQM03OExternal memory interface 1 Input/output mask for byte 0
EMIF1_DQM19OExternal memory interface 1 Input/output mask for byte 1
ESC_TX0_DATA114OEtherCAT MII Transmit-0 Data-1
GPIO890, 4, 8, 12D6171I/OGeneral-Purpose Input Output 89
EMIF1_A162OExternal memory interface 1 address line 16
EMIF1_DQM13OExternal memory interface 1 Input/output mask for byte 1
SCIC_TX6OSCI-C Transmit Data
EMIF1_CAS9OExternal memory interface 1 column address strobe
ESC_TX0_DATA214OEtherCAT MII Transmit-0 Data-2
GPIO900, 4, 8, 12A5172I/OGeneral-Purpose Input Output 90
EMIF1_A172OExternal memory interface 1 address line 17
EMIF1_DQM23OExternal memory interface 1 Input/output mask for byte 2
SCIC_RX6ISCI-C Receive Data
EMIF1_RAS9OExternal memory interface 1 row address strobe
ESC_TX0_DATA314OEtherCAT MII Transmit-0 Data-3
GPIO910, 4, 8, 12B5173I/OGeneral-Purpose Input Output 91
EMIF1_A182OExternal memory interface 1 address line 18
EMIF1_DQM33OExternal memory interface 1 Input/output mask for byte 3
I2CA_SDA6I/ODI2C-A Open-Drain Bidirectional Data
EMIF1_DQM29OExternal memory interface 1 Input/output mask for byte 2
PMBUSA_SCL10I/ODPMBus-A Open-Drain Bidirectional Clock
SSIA_TX11I/OSSI-A Serial Data Transmit
FSIRXF_D013IFSIRX-F Data Input 0
CLB_OUTPUTXBAR114OCLB Output X-BAR Output 1
SPID_SIMO15I/OSPI-D Slave In, Master Out (SIMO)
GPIO920, 4, 8, 12A4174I/OGeneral-Purpose Input Output 92
EMIF1_A192OExternal memory interface 1 address line 19
EMIF1_BA13OExternal memory interface 1 bank address 1
I2CA_SCL6I/ODI2C-A Open-Drain Bidirectional Clock
EMIF1_DQM09OExternal memory interface 1 Input/output mask for byte 0
PMBUSA_SDA10I/ODPMBus-A Open-Drain Bidirectional Data
SSIA_RX11I/OSSI-A Serial Data Receive
FSIRXF_D113IFSIRX-F Data Input 1
CLB_OUTPUTXBAR214OCLB Output X-BAR Output 2
SPID_SOMI15I/OSPI-D Slave Out, Master In (SOMI)
GPIO930, 4, 8, 12B4175I/OGeneral-Purpose Input Output 93
EMIF1_BA03OExternal memory interface 1 bank address 0
SCID_TX6OSCI-D Transmit Data
PMBUSA_ALERT10I/ODPMBus-A Open-Drain Bidirectional Alert Signal
SSIA_CLK11I/OSSI-A Clock
FSIRXF_CLK13IFSIRX-F Input Clock
CLB_OUTPUTXBAR314OCLB Output X-BAR Output 3
SPID_CLK15I/OSPI-D Clock
GPIO940, 4, 8, 12A3176I/OGeneral-Purpose Input Output 94
SCID_RX6ISCI-D Receive Data
EMIF1_BA19OExternal memory interface 1 bank address 1
PMBUSA_CTL10IPMBus-A Control Signal
SSIA_FSS11I/OSSI-A Frame Sync
FSIRXG_D013IFSIRX-G Data Input 0
CLB_OUTPUTXBAR414OCLB Output X-BAR Output 4
SPID_STEn15I/OSPI-D Slave Transmit Enable (STE)
GPIO950, 4, 8, 12B3I/OGeneral-Purpose Input Output 95
EMIF2_A123OExternal memory interface 2 address line 12
FSIRXG_D113IFSIRX-G Data Input 1
CLB_OUTPUTXBAR514OCLB Output X-BAR Output 5
GPIO960, 4, 8, 12C3I/OGeneral-Purpose Input Output 96
EMIF2_DQM13OExternal memory interface 2 Input/output mask for byte 1
EQEP1_A5IeQEP-1 Input A
FSIRXG_CLK13IFSIRX-G Input Clock
CLB_OUTPUTXBAR614OCLB Output X-BAR Output 6
GPIO970, 4, 8, 12A2I/OGeneral-Purpose Input Output 97
EMIF2_DQM03OExternal memory interface 2 Input/output mask for byte 0
EQEP1_B5IeQEP-1 Input B
FSIRXH_D013IFSIRX-H Data Input 0
CLB_OUTPUTXBAR714OCLB Output X-BAR Output 7
GPIO980, 4, 8, 12F1I/OGeneral-Purpose Input Output 98
EMIF2_A03OExternal memory interface 2 address line 0
EQEP1_STROBE5I/OeQEP-1 Strobe
FSIRXH_D113IFSIRX-H Data Input 1
CLB_OUTPUTXBAR814OCLB Output X-BAR Output 8
GPIO990, 4, 8, 12G117I/OGeneral-Purpose Input Output 99
EMIF2_A13OExternal memory interface 2 address line 1
EQEP1_INDEX5I/OeQEP-1 Index
FSIRXH_CLK13IFSIRX-H Input Clock
GPIO1000, 4, 8, 12H1I/OGeneral-Purpose Input Output 100
EMIF2_A23OExternal memory interface 2 address line 2
EQEP2_A5IeQEP-2 Input A
SPIC_SIMO6I/OSPI-C Slave In, Master Out (SIMO)
ESC_GPI010IEtherCAT General-Purpose Input 0
FSITXA_D013OFSITX-A Data Output 0
GPIO1010, 4, 8, 12H2I/OGeneral-Purpose Input Output 101
EMIF2_A33OExternal memory interface 2 address line 3
EQEP2_B5IeQEP-2 Input B
SPIC_SOMI6I/OSPI-C Slave Out, Master In (SOMI)
ESC_GPI110IEtherCAT General-Purpose Input 1
FSITXA_D113OFSITX-A Data Output 1
GPIO1020, 4, 8, 12H3I/OGeneral-Purpose Input Output 102
EMIF2_A43OExternal memory interface 2 address line 4
EQEP2_STROBE5I/OeQEP-2 Strobe
SPIC_CLK6I/OSPI-C Clock
ESC_GPI210IEtherCAT General-Purpose Input 2
FSITXA_CLK13OFSITX-A Output Clock
GPIO1030, 4, 8, 12J1I/OGeneral-Purpose Input Output 103
EMIF2_A53OExternal memory interface 2 address line 5
EQEP2_INDEX5I/OeQEP-2 Index
SPIC_STEn6I/OSPI-C Slave Transmit Enable (STE)
ESC_GPI310IEtherCAT General-Purpose Input 3
FSIRXA_D013IFSIRX-A Data Input 0
GPIO1040, 4, 8, 12J2I/OGeneral-Purpose Input Output 104
I2CA_SDA1I/ODI2C-A Open-Drain Bidirectional Data
EMIF2_A63OExternal memory interface 2 address line 6
EQEP3_A5IeQEP-3 Input A
SCID_TX6OSCI-D Transmit Data
ESC_GPI410IEtherCAT General-Purpose Input 4
CM-I2CA_SDA11I/ODCM-I2C-A Open-Drain Bidirectional Data
FSIRXA_D113IFSIRX-A Data Input 1
GPIO1050, 4, 8, 12J3I/OGeneral-Purpose Input Output 105
I2CA_SCL1I/ODI2C-A Open-Drain Bidirectional Clock
EMIF2_A73OExternal memory interface 2 address line 7
EQEP3_B5IeQEP-3 Input B
SCID_RX6ISCI-D Receive Data
ESC_GPI510IEtherCAT General-Purpose Input 5
CM-I2CA_SCL11I/ODCM-I2C-A Open-Drain Bidirectional Clock
FSIRXA_CLK13IFSIRX-A Input Clock
ENET_MDIO_CLK14I/OEMAC management data clock, Output in MII/RMII modes, Input in RevMII mode
GPIO1060, 4, 8, 12L2I/OGeneral-Purpose Input Output 106
EMIF2_A83OExternal memory interface 2 address line 8
EQEP3_STROBE5I/OeQEP-3 Strobe
SCIC_TX6OSCI-C Transmit Data
ESC_GPI610IEtherCAT General-Purpose Input 6
FSITXB_D013OFSITX-B Data Output 0
ENET_MDIO_DATA14I/OEMAC management data
GPIO1070, 4, 8, 12L3I/OGeneral-Purpose Input Output 107
EMIF2_A93OExternal memory interface 2 address line 9
EQEP3_INDEX5I/OeQEP-3 Index
SCIC_RX6ISCI-C Receive Data
ESC_GPI710IEtherCAT General-Purpose Input 7
FSITXB_D113OFSITX-B Data Output 1
ENET_REVMII_MDIO_RST14IEMAC REVMII MDIO reset
GPIO1080, 4, 8, 12L4I/OGeneral-Purpose Input Output 108
EMIF2_A103OExternal memory interface 2 address line 10
ESC_GPI810IEtherCAT General-Purpose Input 8
FSITXB_CLK13OFSITX-B Output Clock
ENET_MII_INTR14I/OEMAC PHY interrupt, Input in MII/RMII mode, Output in RevMII mode
GPIO1090, 4, 8, 12N2I/OGeneral-Purpose Input Output 109
EMIF2_A113OExternal memory interface 2 address line 11
ESC_GPI910IEtherCAT General-Purpose Input 9
ENET_MII_CRS14IEMAC MII carrier sense
GPIO1100, 4, 8, 12M2I/OGeneral-Purpose Input Output 110
EMIF2_WAIT3IExternal memory interface 2 Asynchronous SRAM WAIT
ESC_GPI1010IEtherCAT General-Purpose Input 10
FSIRXB_D013IFSIRX-B Data Input 0
ENET_MII_COL14IEMAC MII collision detect
GPIO1110, 4, 8, 12M4I/OGeneral-Purpose Input Output 111
EMIF2_BA03OExternal memory interface 2 bank address 0
ESC_GPI1110IEtherCAT General-Purpose Input 11
FSIRXB_D113IFSIRX-B Data Input 1
ENET_MII_RX_CLK14IEMAC MII receive clock
GPIO1120, 4, 8, 12M3I/OGeneral-Purpose Input Output 112
EMIF2_BA13OExternal memory interface 2 bank address 1
ESC_GPI1210IEtherCAT General-Purpose Input 12
FSIRXB_CLK13IFSIRX-B Input Clock
ENET_MII_RX_DV14IEMAC MII receive data valid (or) RMII carrier sense/ receive data valid
GPIO1130, 4, 8, 12N4I/OGeneral-Purpose Input Output 113
EMIF2_CAS3OExternal memory interface 2 column address strobe
ESC_GPI1310IEtherCAT General-Purpose Input 13
ENET_MII_RX_ERR14IEMAC MII / RMII receive error
GPIO1140, 4, 8, 12N3I/OGeneral-Purpose Input Output 114
EMIF2_RAS3OExternal memory interface 2 row address strobe
ESC_GPI1410IEtherCAT General-Purpose Input 14
ENET_MII_RX_DATA014IEMAC MII / RMII receive data 0
GPIO1150, 4, 8, 12V12I/OGeneral-Purpose Input Output 115
EMIF2_CS0n3OExternal memory interface 2 chip select 0
OUTPUTXBAR55OOutput X-BAR Output 5
ESC_GPI1510IEtherCAT General-Purpose Input 15
FSIRXC_D013IFSIRX-C Data Input 0
ENET_MII_RX_DATA114IEMAC MII / RMII receive data 1
GPIO1160, 4, 8, 12W10I/OGeneral-Purpose Input Output 116
EMIF2_CS2n3OExternal memory interface 2 chip select 2
OUTPUTXBAR65OOutput X-BAR Output 6
ESC_GPI1610IEtherCAT General-Purpose Input 16
FSIRXC_D113IFSIRX-C Data Input 1
ENET_MII_RX_DATA214IEMAC MII receive data 2
GPIO1170, 4, 8, 12U12I/OGeneral-Purpose Input Output 117
EMIF2_SDCKE3OExternal memory interface 2 SDRAM clock enable
ESC_GPI1710IEtherCAT General-Purpose Input 17
FSIRXC_CLK13IFSIRX-C Input Clock
ENET_MII_RX_DATA314IEMAC MII receive data 3
GPIO1180, 4, 8, 12T12I/OGeneral-Purpose Input Output 118
EMIF2_CLK3OExternal memory interface 2 clock
ESC_GPI1810IEtherCAT General-Purpose Input 18
FSIRXD_D013IFSIRX-D Data Input 0
ENET_MII_TX_EN14OEMAC MII / RMII transmit enable
GPIO1190, 4, 8, 12T15I/OGeneral-Purpose Input Output 119
EMIF2_RNW3OExternal memory interface 2 read not write
ESC_GPI1910IEtherCAT General-Purpose Input 19
FSIRXD_D113IFSIRX-D Data Input 1
ENET_MII_TX_ERR14OEMAC MII transmit error
GPIO1200, 4, 8, 12U15I/OGeneral-Purpose Input Output 120
EMIF2_WEn3OExternal memory interface 2 write enable
ESC_GPI2010IEtherCAT General-Purpose Input 20
FSIRXD_CLK13IFSIRX-D Input Clock
ENET_MII_TX_CLK14IEMAC MII transmit clock
GPIO1210, 4, 8, 12W16I/OGeneral-Purpose Input Output 121
EMIF2_OEn3OExternal memory interface 2 output enable
ESC_GPI2110IEtherCAT General-Purpose Input 21
FSIRXE_D013IFSIRX-E Data Input 0
ENET_MII_TX_DATA014OEMAC MII / RMII transmit data 0
GPIO1220, 4, 8, 12T8I/OGeneral-Purpose Input Output 122
EMIF2_D153I/OExternal memory interface 2 data line 15
SPIC_SIMO6I/OSPI-C Slave In, Master Out (SIMO)
SD1_D17ISDFM-1 Channel 1 Data Input
ESC_GPI2210IEtherCAT General-Purpose Input 22
ENET_MII_TX_DATA114OEMAC MII / RMII transmit data 1
GPIO1230, 4, 8, 12U8I/OGeneral-Purpose Input Output 123
EMIF2_D143I/OExternal memory interface 2 data line 14
SPIC_SOMI6I/OSPI-C Slave Out, Master In (SOMI)
SD1_C17ISDFM-1 Channel 1 Clock Input
ESC_GPI2310IEtherCAT General-Purpose Input 23
ENET_MII_TX_DATA214OEMAC MII transmit data 2
GPIO1240, 4, 8, 12V8I/OGeneral-Purpose Input Output 124
EMIF2_D133I/OExternal memory interface 2 data line 13
SPIC_CLK6I/OSPI-C Clock
SD1_D27ISDFM-1 Channel 2 Data Input
ESC_GPI2410IEtherCAT General-Purpose Input 24
ENET_MII_TX_DATA314OEMAC MII transmit data 3
GPIO1250, 4, 8, 12T9I/OGeneral-Purpose Input Output 125
EMIF2_D123I/OExternal memory interface 2 data line 12
SPIC_STEn6I/OSPI-C Slave Transmit Enable (STE)
SD1_C27ISDFM-1 Channel 2 Clock Input
ESC_GPI2510IEtherCAT General-Purpose Input 25
FSIRXE_D113IFSIRX-E Data Input 1
ESC_LATCH014IEtherCAT LatchSignal Input 0
GPIO1260, 4, 8, 12U9I/OGeneral-Purpose Input Output 126
EMIF2_D113I/OExternal memory interface 2 data line 11
SD1_D37ISDFM-1 Channel 3 Data Input
ESC_GPI2610IEtherCAT General-Purpose Input 26
FSIRXE_CLK13IFSIRX-E Input Clock
ESC_LATCH114IEtherCAT LatchSignal Input 1
GPIO1270, 4, 8, 12V9I/OGeneral-Purpose Input Output 127
EMIF2_D103I/OExternal memory interface 2 data line 10
SD1_C37ISDFM-1 Channel 3 Clock Input
ESC_GPI2710IEtherCAT General-Purpose Input 27
ESC_SYNC014OEtherCAT SyncSignal Output 0
GPIO1280, 4, 8, 12W9I/OGeneral-Purpose Input Output 128
EMIF2_D93I/OExternal memory interface 2 data line 9
SD1_D47ISDFM-1 Channel 4 Data Input
ESC_GPI2810IEtherCAT General-Purpose Input 28
ESC_SYNC114OEtherCAT SyncSignal Output 1
GPIO1290, 4, 8, 12T10I/OGeneral-Purpose Input Output 129
EMIF2_D83I/OExternal memory interface 2 data line 8
SD1_C47ISDFM-1 Channel 4 Clock Input
ESC_GPI2910IEtherCAT General-Purpose Input 29
ESC_TX1_ENA14OEtherCAT MII Transmit-1 Enable
GPIO1300, 4, 8, 12U10I/OGeneral-Purpose Input Output 130
EMIF2_D73I/OExternal memory interface 2 data line 7
SD2_D17ISDFM-2 Channel 1 Data Input
ESC_GPI3010IEtherCAT General-Purpose Input 30
ESC_TX1_CLK14IEtherCAT MII Transmit-1 Clock
GPIO1310, 4, 8, 12V10I/OGeneral-Purpose Input Output 131
EMIF2_D63I/OExternal memory interface 2 data line 6
SD2_C17ISDFM-2 Channel 1 Clock Input
ESC_GPI3110IEtherCAT General-Purpose Input 31
ESC_TX1_DATA014OEtherCAT MII Transmit-1 Data-0
GPIO1320, 4, 8, 12W18I/OGeneral-Purpose Input Output 132
EMIF2_D53I/OExternal memory interface 2 data line 5
SD2_D27ISDFM-2 Channel 2 Data Input
ESC_GPO010OEtherCAT General-Purpose Output 0
ESC_TX1_DATA114OEtherCAT MII Transmit-1 Data-1
GPIO1330, 4, 8, 12G18118I/OGeneral-Purpose Input Output 133
SD2_C27ISDFM-2 Channel 2 Clock Input
AUXCLKINALTIAuxiliary Clock Input
GPIO1340, 4, 8, 12V18I/OGeneral-Purpose Input Output 134
EMIF2_D43I/OExternal memory interface 2 data line 4
SD2_D37ISDFM-2 Channel 3 Data Input
ESC_GPO110OEtherCAT General-Purpose Output 1
ESC_TX1_DATA214OEtherCAT MII Transmit-1 Data-2
GPIO1350, 4, 8, 12U18I/OGeneral-Purpose Input Output 135
EMIF2_D33I/OExternal memory interface 2 data line 3
SCIA_TX6OSCI-A Transmit Data
SD2_C37ISDFM-2 Channel 3 Clock Input
ESC_GPO210OEtherCAT General-Purpose Output 2
ESC_TX1_DATA314OEtherCAT MII Transmit-1 Data-3
GPIO1360, 4, 8, 12T17I/OGeneral-Purpose Input Output 136
EMIF2_D23I/OExternal memory interface 2 data line 2
SCIA_RX6ISCI-A Receive Data
SD2_D47ISDFM-2 Channel 4 Data Input
ESC_GPO310OEtherCAT General-Purpose Output 3
ESC_RX1_DV14IEtherCAT MII Receive-1 Data Valid
GPIO1370, 4, 8, 12T18I/OGeneral-Purpose Input Output 137
EPWM13A1OePWM-13 Output A (High-res available on ePWM1-8)
EMIF2_D13I/OExternal memory interface 2 data line 1
SCIB_TX6OSCI-B Transmit Data
SD2_C47ISDFM-2 Channel 4 Clock Input
ESC_GPO410OEtherCAT General-Purpose Output 4
ESC_RX1_CLK14IEtherCAT MII Receive-1 Clock
GPIO1380, 4, 8, 12T19I/OGeneral-Purpose Input Output 138
EPWM13B1OePWM-13 Output B (High-res available on ePWM1-8)
EMIF2_D03I/OExternal memory interface 2 data line 0
SCIB_RX6ISCI-B Receive Data
ESC_GPO510OEtherCAT General-Purpose Output 5
ESC_RX1_ERR14IEtherCAT MII Receive-1 Error
GPIO1390, 4, 8, 12N19I/OGeneral-Purpose Input Output 139
EPWM14A1OePWM-14 Output A (High-res available on ePWM1-8)
SCIC_RX6ISCI-C Receive Data
ESC_GPO610OEtherCAT General-Purpose Output 6
ESC_RX1_DATA014IEtherCAT MII Receive-1 Data-0
GPIO1400, 4, 8, 12M19I/OGeneral-Purpose Input Output 140
EPWM14B1OePWM-14 Output B (High-res available on ePWM1-8)
SCIC_TX6OSCI-C Transmit Data
ESC_GPO710OEtherCAT General-Purpose Output 7
ESC_RX1_DATA114IEtherCAT MII Receive-1 Data-1
GPIO1410, 4, 8, 12M18I/OGeneral-Purpose Input Output 141
EPWM15A1OePWM-15 Output A (High-res available on ePWM1-8)
SCID_RX6ISCI-D Receive Data
ESC_GPO810OEtherCAT General-Purpose Output 8
ESC_RX1_DATA214IEtherCAT MII Receive-1 Data-2
GPIO1420, 4, 8, 12L19I/OGeneral-Purpose Input Output 142
EPWM15B1OePWM-15 Output B (High-res available on ePWM1-8)
SCID_TX6OSCI-D Transmit Data
ESC_GPO910OEtherCAT General-Purpose Output 9
ESC_RX1_DATA314IEtherCAT MII Receive-1 Data-3
GPIO1430, 4, 8, 12F18I/OGeneral-Purpose Input Output 143
EPWM16A1OePWM-16 Output A (High-res available on ePWM1-8)
ESC_GPO1010OEtherCAT General-Purpose Output 10
ESC_LED_LINK0_ACTIVE14OEtherCAT Link-0 Active
GPIO1440, 4, 8, 12F17I/OGeneral-Purpose Input Output 144
EPWM16B1OePWM-16 Output B (High-res available on ePWM1-8)
ESC_GPO1110OEtherCAT General-Purpose Output 11
ESC_LED_LINK1_ACTIVE14OEtherCAT Link-1 Active
GPIO1450, 4, 8, 12E17I/OGeneral-Purpose Input Output 145
EPWM1A1OePWM-1 Output A (High-res available on ePWM1-8)
ESC_GPO1210OEtherCAT General-Purpose Output 12
ESC_LED_ERR14OEtherCAT Error LED
GPIO1460, 4, 8, 12D18I/OGeneral-Purpose Input Output 146
EPWM1B1OePWM-1 Output B (High-res available on ePWM1-8)
ESC_GPO1310OEtherCAT General-Purpose Output 13
ESC_LED_RUN14OEtherCAT Run LED
GPIO1470, 4, 8, 12D17I/OGeneral-Purpose Input Output 147
EPWM2A1OePWM-2 Output A (High-res available on ePWM1-8)
ESC_GPO1410OEtherCAT General-Purpose Output 14
ESC_LED_STATE_RUN14OEtherCAT State Run
GPIO1480, 4, 8, 12D14I/OGeneral-Purpose Input Output 148
EPWM2B1OePWM-2 Output B (High-res available on ePWM1-8)
ESC_GPO1510OEtherCAT General-Purpose Output 15
ESC_PHY0_LINKSTATUS14IEtherCAT PHY-0 Link Status
GPIO1490, 4, 8, 12A13I/OGeneral-Purpose Input Output 149
EPWM3A1OePWM-3 Output A (High-res available on ePWM1-8)
ESC_GPO1610OEtherCAT General-Purpose Output 16
ESC_PHY1_LINKSTATUS14IEtherCAT PHY-1 Link Status
GPIO1500, 4, 8, 12B13I/OGeneral-Purpose Input Output 150
EPWM3B1OePWM-3 Output B (High-res available on ePWM1-8)
ESC_GPO1710OEtherCAT General-Purpose Output 17
ESC_I2C_SDA14I/OCEtherCAT I2C Data
GPIO1510, 4, 8, 12C13I/OGeneral-Purpose Input Output 151
EPWM4A1OePWM-4 Output A (High-res available on ePWM1-8)
ESC_GPO1810OEtherCAT General-Purpose Output 18
ESC_I2C_SCL14I/OCEtherCAT I2C Clock
GPIO1520, 4, 8, 12D13I/OGeneral-Purpose Input Output 152
EPWM4B1OePWM-4 Output B (High-res available on ePWM1-8)
ESC_GPO1910OEtherCAT General-Purpose Output 19
ESC_MDIO_CLK14OEtherCAT MDIO Clock
GPIO1530, 4, 8, 12A12I/OGeneral-Purpose Input Output 153
EPWM5A1OePWM-5 Output A (High-res available on ePWM1-8)
ESC_GPO2010OEtherCAT General-Purpose Output 20
ESC_MDIO_DATA14I/OEtherCAT MDIO Data
GPIO1540, 4, 8, 12B12I/OGeneral-Purpose Input Output 154
EPWM5B1OePWM-5 Output B (High-res available on ePWM1-8)
ESC_GPO2110OEtherCAT General-Purpose Output 21
ESC_PHY_CLK14OEtherCAT PHY Clock
GPIO1550, 4, 8, 12C12I/OGeneral-Purpose Input Output 155
EPWM6A1OePWM-6 Output A (High-res available on ePWM1-8)
ESC_GPO2210OEtherCAT General-Purpose Output 22
ESC_PHY_RESETn14OEtherCAT PHY Active Low Reset
GPIO1560, 4, 8, 12D12I/OGeneral-Purpose Input Output 156
EPWM6B1OePWM-6 Output B (High-res available on ePWM1-8)
ESC_GPO2310OEtherCAT General-Purpose Output 23
ESC_TX0_ENA14OEtherCAT MII Transmit-0 Enable
GPIO1570, 4, 8, 12B10I/OGeneral-Purpose Input Output 157
EPWM7A1OePWM-7 Output A (High-res available on ePWM1-8)
ESC_GPO2410OEtherCAT General-Purpose Output 24
ESC_TX0_CLK14IEtherCAT MII Transmit-0 Clock
GPIO1580, 4, 8, 12C10I/OGeneral-Purpose Input Output 158
EPWM7B1OePWM-7 Output B (High-res available on ePWM1-8)
ESC_GPO2510OEtherCAT General-Purpose Output 25
ESC_TX0_DATA014OEtherCAT MII Transmit-0 Data-0
GPIO1590, 4, 8, 12D10I/OGeneral-Purpose Input Output 159
EPWM8A1OePWM-8 Output A (High-res available on ePWM1-8)
ESC_GPO2610OEtherCAT General-Purpose Output 26
ESC_TX0_DATA114OEtherCAT MII Transmit-0 Data-1
GPIO1600, 4, 8, 12B9I/OGeneral-Purpose Input Output 160
EPWM8B1OePWM-8 Output B (High-res available on ePWM1-8)
ESC_GPO2710OEtherCAT General-Purpose Output 27
ESC_TX0_DATA214OEtherCAT MII Transmit-0 Data-2
GPIO1610, 4, 8, 12C9I/OGeneral-Purpose Input Output 161
EPWM9A1OePWM-9 Output A (High-res available on ePWM1-8)
ESC_GPO2810OEtherCAT General-Purpose Output 28
ESC_TX0_DATA314OEtherCAT MII Transmit-0 Data-3
GPIO1620, 4, 8, 12D9I/OGeneral-Purpose Input Output 162
EPWM9B1OePWM-9 Output B (High-res available on ePWM1-8)
ESC_GPO2910OEtherCAT General-Purpose Output 29
ESC_RX0_DV14IEtherCAT MII Receive-0 Data Valid
GPIO1630, 4, 8, 12A8I/OGeneral-Purpose Input Output 163
EPWM10A1OePWM-10 Output A (High-res available on ePWM1-8)
ESC_GPO3010OEtherCAT General-Purpose Output 30
ESC_RX0_CLK14IEtherCAT MII Receive-0 Clock
GPIO1640, 4, 8, 12B8I/OGeneral-Purpose Input Output 164
EPWM10B1OePWM-10 Output B (High-res available on ePWM1-8)
ESC_GPO3110OEtherCAT General-Purpose Output 31
ESC_RX0_ERR14IEtherCAT MII Receive-0 Error
GPIO1650, 4, 8, 12C5I/OGeneral-Purpose Input Output 165
EPWM11A1OePWM-11 Output A (High-res available on ePWM1-8)
MDXA10OMcBSP-A Transmit Serial Data
ESC_RX0_DATA014IEtherCAT MII Receive-0 Data-0
GPIO1660, 4, 8, 12D5I/OGeneral-Purpose Input Output 166
EPWM11B1OePWM-11 Output B (High-res available on ePWM1-8)
MDRA10IMcBSP-A Receive Serial Data
ESC_RX0_DATA114IEtherCAT MII Receive-0 Data-1
GPIO1670, 4, 8, 12C4I/OGeneral-Purpose Input Output 167
EPWM12A1OePWM-12 Output A (High-res available on ePWM1-8)
MCLKXA10OMcBSP-A Transmit Clock
ESC_RX0_DATA214IEtherCAT MII Receive-0 Data-2
GPIO1680, 4, 8, 12D4I/OGeneral-Purpose Input Output 168
EPWM12B1OePWM-12 Output B (High-res available on ePWM1-8)
MFSXA10OMcBSP-A Transmit Frame Sync
ESC_RX0_DATA314IEtherCAT MII Receive-0 Data-3
TEST, JTAG, AND RESET
ERRORSTSU1992OError Status Output. When used, this signal requires an external pulldown.
FLT1W1273I/OFlash test pin 1. Reserved for TI. Must be left unconnected.
FLT2V1374I/OFlash test pin 2. Reserved for TI. Must be left unconnected.
NC1H4No Connection. This pin is not internally connected to the device. This pin may be left open or connected to any voltage within the maximum operating conditions.
NC2J18119No Connection. This pin is not internally connected in the device and may be left open or tied to VSS or VDDIO. NOTE: On other C2000 devices with an internal voltage regulator (VREG), this pin will be VREGENZ (internal voltage regulator enable). To enable PCB compatibility across C2000 devices this pin should be connected to VDDIO (3.3v). This will ensure the internal VREG, when present on other devices, would be disabled and not conflict with an external VREG which must be used with this device.
TCKV1581IJTAG test clock with internal pullup.
TDIW1377IJTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.
TDOW1578OJTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK.
TMSW1480IJTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. An external pullup resistor (recommended 2.2 kΩ) on the TMS pin to VDDIO should be placed on the board to keep JTAG in reset during normal operation.
TRSTnV1479I

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST must be maintained low at all times during normal device operation, so an external pulldown resistor is required on this pin for protection against noise spikes. The value of this resistor should be as small as possible, so long as the JTAG debug probe is still able to drive the TRST pin high. A resistor between 2.2 kΩ and 10 kΩ generally offers adequate protection. Since the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debug probe and the application. This pin has an internal 50-ns (nominal) glitch filter.

X1G19123ICrystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock.
X2J19121OCrystal oscillator output.
XRSnF19124I/ODDevice Reset (in) and Watchdog Reset (out). During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRSn pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor between 2.2 kΩ and 10 kΩ should be placed between XRSn and VDDIO. If a capacitor is placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. The output buffer of this pin is an open-drain with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device.
POWER AND GROUND
VDDE9, E11, F9, F11, G14, G15, J14, J15, K5, K6, P10, P13, R10, R1361, 76, 117, 126, 137, 153, 158, 169, 16, 211.2-V Digital Logic Power Pins. TI recommends placing a decoupling capacitor near each VDD pin with a minimum total capacitance of approximately 20 µF. The exact value of the decoupling capacitance should be determined by your system voltage regulation solution. A single 56Ω resistor (10% tolerance) should be placed between VDD and VSS. This resistor provides a load to consume an internal VDD3VFL to VDD current source and avoid VDD voltage rising during low power device conditions.
VDD3VFLR11, R12723.3-V Flash power pin. Place a minimum 0.1-µF decoupling capacitor on each pin
VDDAP6, R654, 363.3-V Analog Power Pins. Place a minimum 2.2-µF decoupling capacitor to VSSA on each pin.
VDDIOA9, A18, B1, E7, E10, E13, F7, F10, F13, G5, G6, H5, H6, L14, L15, M1, M5, M6, N14, N15, P9, R9, V19, W8, F4, G4, E16, F1662, 68, 75, 82, 88, 91, 99, 106, 114, 116, 127, 138, 147, 152, 159, 168, 3, 11, 15, 20, 263.3-V Digital I/O Power Pins. Place a minimum 0.1-µF decoupling capacitor on each pin.
VDDOSCH16, H17120, 125Power pins for the 3.3-V on-chip crystal oscillator (X1 and X2) and the two zero-pin internal oscillators (INTOSC). Place a 0.1-µF (minimum) decoupling capacitor on each pin.
VSSA1, A10, A19, E5, E6, E8, E12, E14, E15, F5, F6, F8, F12, F14, F15, G16, G17, H8, H9, H10, H11, H12, H14, H15, J5, J6, J8, J9, J10, J11, J12, K8, K9, K10, K11, K12, K14, K15, L5, L6, L8, L9, L10, L11, L12, L18, M8, M9, M10, M11, M12, M14, M15, N1, N5, N6, P7, P8, P11, P12, P14, P15, R7, R8, R14, R15, W7, W19PADDevice ground. For Quad Flatpacks (QFPs), the PowerPAD on the bottom of the package must be soldered to the ground plane of the PCB.
VSSAP1, P5, R5, V7, W152, 34Analog Ground
VSSOSCH18, H19122Crystal oscillator (X1 and X2) ground pin. When using an external crystal, do not connect this pin to the board ground. Instead, connect it to the ground reference of the external crystal oscillator circuit. If an external crystal is not used, this pin may be connected to the board ground.