SPRSP14E may 2019 – june 2023 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
On every reset, the device executes a boot sequence in the ROM, depending on the reset type and boot configuration. This sequence initializes the device to run the application code. For CPU1, the boot ROM also contains peripheral bootloaders that can be used to load an application into RAM. These bootloaders can be disabled for safety or security purposes.
Table 8-13 summarizes available boot features across CPU1, CPU2, and CM. Table 8-14 lists the sizes of the various ROMs on the device.
BOOT FEATURE | CPU1 (MASTER) | CPU2 | CM |
---|---|---|---|
Initiate boot process | Device Reset | CPU1 Application | CPU1 Application |
Boot mode selection | GPIOs | IPC Register | IPC Register |
Supported boot modes:
| Yes | Yes | Yes |
Boot to User OTP | No | Yes | Yes |
Copy from IPC Message RAM and boot to RAM | No | Yes | Yes |
Peripheral boot loader support | Yes | No | No |
ROM | CPU1 SIZE | CPU2 SIZE | CM SIZE |
---|---|---|---|
Unsecure boot ROM | 192KB | 64KB | 64KB |
Secure ROM | 64KB | 64KB | 32KB |
CLA data ROM | 8KB | 8KB | N/A |