SPRSP14E may   2019  – june 2023 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Revision History
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1 Analog Signals
      2. 6.3.2 Digital Signals
      3. 6.3.3 Power and Ground
      4. 6.3.4 Test, JTAG, and Reset
    4. 6.4 Pins With Internal Pullup and Pulldown
    5. 6.5 Pin Multiplexing
      1. 6.5.1 GPIO Muxed Pins Table
      2. 6.5.2 Input X-BAR
      3. 6.5.3 Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
      4. 6.5.4 USB Pin Muxing
      5. 6.5.5 High-Speed SPI Pin Muxing
      6. 6.5.6 High-Speed SSI Pin Muxing
    6. 6.6 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 System Current Consumption (External Supply)
      2. 7.5.2 Operating Mode Test Description
      3. 7.5.3 Current Consumption Graphs
      4. 7.5.4 Reducing Current Consumption
        1. 7.5.4.1 Typical Current Reduction per Disabled Peripheral
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics for ZWT Package
    8. 7.8  Thermal Resistance Characteristics for PTP Package
    9. 7.9  Thermal Design Considerations
    10. 7.10 System
      1. 7.10.1  Power Management Module (PMM)
        1. 7.10.1.1 Introduction
        2. 7.10.1.2 Overview
          1. 7.10.1.2.1 Power Rail Monitors
          2. 7.10.1.2.2 I/O POR (Power-On Reset) Monitor
          3. 7.10.1.2.3 VDD POR (Power-On Reset) Monitor
          4. 7.10.1.2.4 External Supervisor Usage
          5. 7.10.1.2.5 Delay Blocks
        3. 7.10.1.3 External Components
          1. 7.10.1.3.1 Decoupling Capacitors
          2. 7.10.1.3.2 VDDIO Decoupling
        4. 7.10.1.4 Power Sequencing
          1. 7.10.1.4.1 Supply Pins Ganging
          2. 7.10.1.4.2 Signal Pins Power Sequence
          3. 7.10.1.4.3 Supply Pins Power Sequence
            1. 7.10.1.4.3.1 Power Supply Sequence
            2. 7.10.1.4.3.2 Supply Sequencing Summary and Effects of Violations
            3. 7.10.1.4.3.3 Supply Slew Rate
        5. 7.10.1.5 Power Management Module Electrical Data and Timing
          1. 7.10.1.5.1 Power Management Module Operating Conditions
          2. 7.10.1.5.2 Power Management Module Characteristics
      2. 7.10.2  Reset Timing
        1. 7.10.2.1 Reset Sources
        2. 7.10.2.2 Reset Electrical Data and Timing
          1. 7.10.2.2.1 Reset (XRSn) Timing Requirements
          2. 7.10.2.2.2 Reset (XRSn) Switching Characteristics
          3. 7.10.2.2.3 Reset Timing Diagrams
      3. 7.10.3  Clock Specifications
        1. 7.10.3.1 Clock Sources
        2. 7.10.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 7.10.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 7.10.3.2.1.1 Input Clock Frequency
            2. 7.10.3.2.1.2 XTAL Oscillator Characteristics
            3. 7.10.3.2.1.3 X1 Timing Requirements
            4. 7.10.3.2.1.4 AUXCLKIN Timing Requirements
            5. 7.10.3.2.1.5 APLL Characteristics
          2. 7.10.3.2.2 Internal Clock Frequencies
            1. 7.10.3.2.2.1 Internal Clock Frequencies
          3. 7.10.3.2.3 Output Clock Frequency and Switching Characteristics
            1. 7.10.3.2.3.1 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        3. 7.10.3.3 Input Clocks
        4. 7.10.3.4 XTAL Oscillator
          1. 7.10.3.4.1 Introduction
          2. 7.10.3.4.2 Overview
            1. 7.10.3.4.2.1 Electrical Oscillator
              1. 7.10.3.4.2.1.1 Modes of Operation
                1. 7.10.3.4.2.1.1.1 Crystal Mode of Operation
                2. 7.10.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 7.10.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 7.10.3.4.2.2 Quartz Crystal
            3. 7.10.3.4.2.3 GPIO Modes of Operation
          3. 7.10.3.4.3 Functional Operation
            1. 7.10.3.4.3.1 ESR – Effective Series Resistance
            2. 7.10.3.4.3.2 Rneg – Negative Resistance
            3. 7.10.3.4.3.3 Start-up Time
              1. 7.10.3.4.3.3.1 X1/X2 Precondition
            4. 7.10.3.4.3.4 DL – Drive Level
          4. 7.10.3.4.4 How to Choose a Crystal
          5. 7.10.3.4.5 Testing
          6. 7.10.3.4.6 Common Problems and Debug Tips
          7. 7.10.3.4.7 Crystal Oscillator Specifications
            1. 7.10.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 7.10.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 7.10.3.4.7.3 Crystal Oscillator Parameters
            4. 7.10.3.4.7.4 Crystal Oscillator Electrical Characteristics
        5. 7.10.3.5 Internal Oscillators
          1. 7.10.3.5.1 INTOSC Characteristics
      4. 7.10.4  Flash Parameters
        1. 7.10.4.1 Flash Parameters 
        2.       111
      5. 7.10.5  RAM Specifications
      6. 7.10.6  ROM Specifications
      7. 7.10.7  Emulation/JTAG
        1. 7.10.7.1 JTAG Electrical Data and Timing
          1. 7.10.7.1.1 JTAG Timing Requirements
          2. 7.10.7.1.2 JTAG Switching Characteristics
          3. 7.10.7.1.3 JTAG Timing
      8. 7.10.8  GPIO Electrical Data and Timing
        1. 7.10.8.1 GPIO - Output Timing
          1. 7.10.8.1.1 General-Purpose Output Switching Characteristics
          2. 7.10.8.1.2 General-Purpose Output Timing
        2. 7.10.8.2 GPIO - Input Timing
          1. 7.10.8.2.1 General-Purpose Input Timing Requirements
          2. 7.10.8.2.2 Sampling Mode
        3. 7.10.8.3 Sampling Window Width for Input Signals
      9. 7.10.9  Interrupts
        1. 7.10.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 7.10.9.1.1 External Interrupt Timing Requirements
          2. 7.10.9.1.2 External Interrupt Switching Characteristics
          3. 7.10.9.1.3 External Interrupt Timing
      10. 7.10.10 Low-Power Modes
        1. 7.10.10.1 Clock-Gating Low-Power Modes
        2. 7.10.10.2 Low-Power Mode Wakeup Timing
          1. 7.10.10.2.1 IDLE Mode Timing Requirements
          2. 7.10.10.2.2 IDLE Mode Switching Characteristics
          3. 7.10.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 7.10.10.2.4 STANDBY Mode Timing Requirements
          5. 7.10.10.2.5 STANDBY Mode Switching Characteristics
          6. 7.10.10.2.6 STANDBY Entry and Exit Timing Diagram
      11. 7.10.11 External Memory Interface (EMIF)
        1. 7.10.11.1 Asynchronous Memory Support
        2. 7.10.11.2 Synchronous DRAM Support
        3. 7.10.11.3 EMIF Electrical Data and Timing
          1. 7.10.11.3.1 Asynchronous RAM
            1. 7.10.11.3.1.1 EMIF Asynchronous Memory Timing Requirements
            2. 7.10.11.3.1.2 EMIF Asynchronous Memory Switching Characteristics
            3. 7.10.11.3.1.3 EMIF Asynchronous Memory Timing Diagrams
          2. 7.10.11.3.2 Synchronous RAM
            1. 7.10.11.3.2.1 EMIF Synchronous Memory Timing Requirements
            2. 7.10.11.3.2.2 EMIF Synchronous Memory Switching Characteristics
            3. 7.10.11.3.2.3 EMIF Synchronous Memory Timing Diagrams
    11. 7.11 C28x Analog Peripherals
      1. 7.11.1 Analog Subsystem
      2. 7.11.2 Analog-to-Digital Converter (ADC)
        1. 7.11.2.1 Result Register Mapping
        2. 7.11.2.2 ADC Configurability
          1. 7.11.2.2.1 Signal Mode
        3. 7.11.2.3 ADC Electrical Data and Timing
          1. 7.11.2.3.1 ADC Operating Conditions (16-bit Differential)
            1. 7.11.2.3.1.1 ADC Operating Conditions (16-bit Differential) Notes
          2. 7.11.2.3.2 ADC Characteristics (16-bit Differential)
          3. 7.11.2.3.3 ADC Operating Conditions (16-bit Single-Ended)
            1. 7.11.2.3.3.1 ADC Operating Conditions (16-bit Single-Ended) Notes
          4. 7.11.2.3.4 ADC Characteristics (16-bit Single-Ended)
          5. 7.11.2.3.5 ADC Operating Conditions (12-bit Single-Ended)
            1. 7.11.2.3.5.1 ADC Operating Conditions (12-bit Single-Ended) Notes
          6. 7.11.2.3.6 ADC Characteristics (12-bit Single-Ended)
          7. 7.11.2.3.7 ADCEXTSOC Timing Requirements
          8. 7.11.2.3.8 ADC Input Models
            1. 7.11.2.3.8.1 Single-Ended Input Model Parameters (12-bit Resolution)
            2. 7.11.2.3.8.2 Single-Ended Input Model Parameters (16-bit Resolution)
            3. 7.11.2.3.8.3 Single-Ended Input Model
            4. 7.11.2.3.8.4 Differential Input Model Parameters (16-bit Resolution)
            5. 7.11.2.3.8.5 Differential Input Model
          9. 7.11.2.3.9 ADC Timing Diagrams
            1. 7.11.2.3.9.1 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
            2. 7.11.2.3.9.2 ADC Timings in 16-Bit Mode
        4. 7.11.2.4 Temperature Sensor Electrical Data and Timing
          1. 7.11.2.4.1 Temperature Sensor Characteristics
      3. 7.11.3 Comparator Subsystem (CMPSS)
        1. 7.11.3.1 CMPSS Electrical Data and Timing
          1. 7.11.3.1.1 Comparator Electrical Characteristics
          2. 7.11.3.1.2 CMPSS Comparator Input Referred Offset and Hysteresis
          3. 7.11.3.1.3 CMPSS DAC Static Electrical Characteristics
          4. 7.11.3.1.4 CMPSS Illustrative Graphs
          5. 7.11.3.1.5 CMPSS DAC Dynamic Error
      4. 7.11.4 Buffered Digital-to-Analog Converter (DAC)
        1. 7.11.4.1 Buffered DAC Electrical Data and Timing
          1. 7.11.4.1.1 Buffered DAC Operating Conditions
          2. 7.11.4.1.2 Buffered DAC Electrical Characteristics
          3. 7.11.4.1.3 Buffered DAC Notes and Illustrative Graphs
    12. 7.12 C28x Control Peripherals
      1. 7.12.1 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
        1. 7.12.1.1 eCAP Synchronization
        2. 7.12.1.2 eCAP Electrical Data and Timing
          1. 7.12.1.2.1 eCAP Timing Requirements
          2. 7.12.1.2.2 eCAP Switching Charcteristics
        3. 7.12.1.3 HRCAP Electrical Data and Timing
          1. 7.12.1.3.1 HRCAP Switching Characteristics
          2. 7.12.1.3.2 HRCAP Graphs
      2. 7.12.2 Enhanced Pulse Width Modulator (ePWM)
        1. 7.12.2.1 Control Peripherals Synchronization
        2. 7.12.2.2 ePWM Electrical Data and Timing
          1. 7.12.2.2.1 ePWM Timing Requirements
          2. 7.12.2.2.2 ePWM Switching Characteristics
          3. 7.12.2.2.3 Trip-Zone Input Timing
            1. 7.12.2.2.3.1 Trip-Zone Input Timing Requirements
        3. 7.12.2.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 7.12.2.3.1 External ADC Start-of-Conversion Switching Characteristics
      3. 7.12.3 High-Resolution Pulse Width Modulator (HRPWM)
        1. 7.12.3.1 HRPWM Electrical Data and Timing
          1. 7.12.3.1.1 High-Resolution PWM Characteristics
      4. 7.12.4 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.12.4.1 eQEP Electrical Data and Timing
          1. 7.12.4.1.1 eQEP Timing Requirements
          2. 7.12.4.1.2 eQEP Switching Characteristics
      5. 7.12.5 Sigma-Delta Filter Module (SDFM)
        1. 7.12.5.1 SDFM Electrical Data and Timing (Using ASYNC)
          1. 7.12.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
          2. 7.12.5.1.2 SDFM Timing Diagram
    13. 7.13 C28x Communications Peripherals
      1. 7.13.1 Controller Area Network (CAN)
      2. 7.13.2 Fast Serial Interface (FSI)
        1. 7.13.2.1 FSI Transmitter
          1. 7.13.2.1.1 FSITX Electrical Data and Timing
            1. 7.13.2.1.1.1 FSITX Switching Characteristics
            2. 7.13.2.1.1.2 FSITX Timings
        2. 7.13.2.2 FSI Receiver
          1. 7.13.2.2.1 FSIRX Electrical Data and Timing
            1. 7.13.2.2.1.1 FSIRX Timing Requirements
            2. 7.13.2.2.1.2 FSIRX Switching Characteristics
            3. 7.13.2.2.1.3 FSIRX Timing Diagram
        3. 7.13.2.3 SPI Signaling Mode
          1. 7.13.2.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 7.13.2.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 7.13.2.3.1.2 FSITX SPI Signaling Mode Timings
      3. 7.13.3 Inter-Integrated Circuit (I2C)
        1. 7.13.3.1 I2C Electrical Data and Timing
          1. 7.13.3.1.1 I2C Timing Requirements
          2. 7.13.3.1.2 I2C Switching Characteristics
          3. 7.13.3.1.3 I2C Timing Diagram
      4. 7.13.4 Multichannel Buffered Serial Port (McBSP)
        1. 7.13.4.1 McBSP Electrical Data and Timing
          1. 7.13.4.1.1 McBSP Transmit and Receive Timing
            1. 7.13.4.1.1.1 McBSP Timing Requirements
            2. 7.13.4.1.1.2 McBSP Switching Characteristics
            3. 7.13.4.1.1.3 McBSP Receive and Transmit Timing Diagrams
          2. 7.13.4.1.2 McBSP as SPI Master or Slave Timing
            1. 7.13.4.1.2.1 McBSP as SPI Master Timing Requirements
            2. 7.13.4.1.2.2 McBSP as SPI Master Switching Characteristics
            3. 7.13.4.1.2.3 McBSP as SPI Slave Timing Requirements
            4. 7.13.4.1.2.4 McBSP as SPI Slave Switching Characteristics
            5. 7.13.4.1.2.5 McBSP as SPI Master or Slave Timing Diagrams
      5. 7.13.5 Power Management Bus (PMBus)
        1. 7.13.5.1 PMBus Electrical Data and Timing
          1. 7.13.5.1.1 PMBus Electrical Characteristics
          2. 7.13.5.1.2 PMBus Fast Mode Switching Characteristics
          3. 7.13.5.1.3 PMBus Standard Mode Switching Characteristics
      6. 7.13.6 Serial Communications Interface (SCI)
      7. 7.13.7 Serial Peripheral Interface (SPI)
        1. 7.13.7.1 SPI Electrical Data and Timing
          1. 7.13.7.1.1 SPI Master Mode Timings
            1. 7.13.7.1.1.1 SPI Master Mode Timing Requirements
            2. 7.13.7.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            3. 7.13.7.1.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            4. 7.13.7.1.1.4 SPI Master Mode External Timing
          2. 7.13.7.1.2 SPI Slave Mode Timings
            1. 7.13.7.1.2.1 SPI Slave Mode Timing Requirements
            2. 7.13.7.1.2.2 SPI Slave Mode Switching Characteristics
            3. 7.13.7.1.2.3 SPI Slave Mode External Timing
      8. 7.13.8 EtherCAT Slave Controller (ESC)
        1. 7.13.8.1 ESC Features
        2. 7.13.8.2 ESC Subsystem Integrated Features
        3. 7.13.8.3 EtherCAT IP Block Diagram
        4. 7.13.8.4 EtherCAT Electrical Data and Timing
          1. 7.13.8.4.1 EtherCAT Timing Requirements
          2. 7.13.8.4.2 EtherCAT Switching Characteristics
          3. 7.13.8.4.3 EtherCAT Timing Diagrams
      9. 7.13.9 Universal Serial Bus (USB) Controller
        1. 7.13.9.1 USB Electrical Data and Timing
          1. 7.13.9.1.1 USB Input Ports DP and DM Timing Requirements
          2. 7.13.9.1.2 USB Output Ports DP and DM Switching Characteristics
    14. 7.14 Connectivity Manager (CM) Peripherals
      1. 7.14.1 Modular Controller Area Network (MCAN) [CAN FD]
      2. 7.14.2 Ethernet Media Access Controller (EMAC)
        1. 7.14.2.1 MAC Features
          1. 7.14.2.1.1 MAC Tx and Rx Features
          2. 7.14.2.1.2 MAC Tx Features
          3. 7.14.2.1.3 MAC Rx Features
        2. 7.14.2.2 Ethernet Electrical Data and Timing
          1. 7.14.2.2.1 Ethernet Timing Requirements
          2. 7.14.2.2.2 Ethernet Switching Characteristics
          3. 7.14.2.2.3 Ethernet Timing Diagrams
        3. 7.14.2.3 Ethernet REVMII Electrical Data and Timing
          1. 7.14.2.3.1 Ethernet REVMII Timing Requirements
          2. 7.14.2.3.2 Ethernet REVMII Switching Characteristics
      3. 7.14.3 Inter-Integrated Circuit (CM-I2C)
        1. 7.14.3.1 CM-I2C Electrical Data and Timing
          1. 7.14.3.1.1 CM-I2C Timing Requirements
          2. 7.14.3.1.2 CM-I2C Switching Characteristics
          3. 7.14.3.1.3 CM-I2C Timing Diagram
      4. 7.14.4 Synchronous Serial Interface (SSI)
        1. 7.14.4.1 SSI Electrical Data and Timing
          1. 7.14.4.1.1 SSI Timing Requirements
          2. 7.14.4.1.2 SSI Characteristics
          3. 7.14.4.1.3 SSI Timing Diagrams
      5. 7.14.5 Universal Asynchronous Receiver/Transmitter (CM-UART)
      6. 7.14.6 Trace Port Interface Unit (TPIU)
        1. 7.14.6.1 TPIU Electrical Data and Timing
          1. 7.14.6.1.1 Trace Port Switching Characteristics
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Memory
      1. 8.3.1 C28x Memory Map
      2. 8.3.2 C28x Flash Memory Map
      3. 8.3.3 Peripheral Registers Memory Map
      4. 8.3.4 EMIF Chip Select Memory Map
      5. 8.3.5 CM Memory Map
      6. 8.3.6 CM Flash Memory Map
      7. 8.3.7 Peripheral Registers Memory Map (CM)
      8. 8.3.8 Memory Types
        1. 8.3.8.1 Dedicated RAM (Mx and Dx RAM)
        2. 8.3.8.2 Local Shared RAM (LSx RAM)
        3. 8.3.8.3 Global Shared RAM (GSx RAM)
        4. 8.3.8.4 CPU Message RAM (CPU MSGRAM)
        5. 8.3.8.5 CLA Message RAM (CLA MSGRAM)
        6. 8.3.8.6 CLA - DMA Message RAM (CLA-DMA MSGRAM)
        7. 8.3.8.7 CPUx - CM Message RAM (CPUx-CM MSGRAM)
        8. 8.3.8.8 Dedicated RAM (C0/C1 RAM)
        9. 8.3.8.9 Shared RAM (E0 and Sx RAM)
    4. 8.4  Identification
    5. 8.5  Bus Architecture – Peripheral Connectivity
    6. 8.6  Boot ROM and Peripheral Booting
      1. 8.6.1 Device Boot
      2. 8.6.2 Device Boot Modes
      3. 8.6.3 Device Boot Configurations
      4. 8.6.4 GPIO Assignments for CPU1
    7. 8.7  Dual Code Security Module (DCSM)
    8. 8.8  C28x (CPU1/CPU2) Subsystem
      1. 8.8.1  C28x Processor
        1. 8.8.1.1 Floating-Point Unit
        2. 8.8.1.2 Trigonometric Math Unit
        3. 8.8.1.3 Fast Integer Division Unit
        4. 8.8.1.4 VCRC Unit
      2. 8.8.2  Embedded Real-Time Analysis and Diagnostic (ERAD)
      3. 8.8.3  Background CRC-32 (BGCRC)
      4. 8.8.4  Control Law Accelerator (CLA)
      5. 8.8.5  Direct Memory Access (DMA)
      6. 8.8.6  Interprocessor Communication (IPC) Module
      7. 8.8.7  C28x Timers
      8. 8.8.8  Dual-Clock Comparator (DCC)
        1. 8.8.8.1 Features
        2. 8.8.8.2 Mapping of DCCx (DCC0, DCC1, and DCC2) Clock Source Inputs
      9. 8.8.9  Nonmaskable Interrupt With Watchdog Timer (NMIWD)
      10. 8.8.10 Watchdog
      11. 8.8.11 Configurable Logic Block (CLB)
    9. 8.9  Connectivity Manager (CM) Subsystem
      1. 8.9.1  Arm Cortex-M4 Processor
      2. 8.9.2  Nested Vectored Interrupt Controller (NVIC)
      3. 8.9.3  Advance Encryption Standard (AES) Accelerator
      4. 8.9.4  Generic Cyclic Redundancy Check (GCRC) Module
      5. 8.9.5  CM Nonmaskable Interrupt (CMNMI) Module
      6. 8.9.6  Memory Protection Unit (MPU)
      7. 8.9.7  Micro Direct Memory Access (µDMA)
      8. 8.9.8  Watchdog
      9. 8.9.9  CM Clocking
        1. 8.9.9.1 CM Clock Sources
      10. 8.9.10 CM Timers
    10. 8.10 Functional Safety
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application and Implementation
    2. 9.2 Key Device Features
    3. 9.3 Application Information
      1. 9.3.1 Typical Application
        1. 9.3.1.1 High-Voltage Traction Inverter
          1. 9.3.1.1.1 System Block Diagram
          2. 9.3.1.1.2 High-Voltage Traction Inverter Resources
        2. 9.3.1.2 On-Board Charger (OBC)
          1. 9.3.1.2.1 System Block Diagram
          2. 9.3.1.2.2 OBC Resources
        3. 9.3.1.3 Servo Drive Control Module
          1. 9.3.1.3.1 System Block Diagram
          2. 9.3.1.3.2 Servo Drive Control Module Resources
        4. 9.3.1.4 Solar Micro Inverter
          1. 9.3.1.4.1 System Block Diagram
          2. 9.3.1.4.2 Solar Micro Inverter Resources
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Markings
    4. 10.4 Tools and Software
    5. 10.5 Documentation Support
    6. 10.6 Support Resources
    7. 10.7 Trademarks
    8. 10.8 Electrostatic Discharge Caution
    9. 10.9 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZWT|337
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2 Key Device Features

Table 9-1 Key Device Features
MODULE FEATURE SYSTEM BENEFIT
C28x PROCESSING
Real-time control CPUs

Up to 800 MIPS

Two C28x cores: 400 MIPS (2 x 200 MIPS)

Two CLA cores: 400 MIPS (2 x 200 MIPS)

Flash: Up to 1 MB (512KB on each C28x CPU)

RAM : Up to 216 KB

64-bit Floating Point Unit (FPU64)

Trigonometric Math Unit (TMU)

CRC engine and instructions (VCRC)

Fast Integer Division (FINTDIV)

TI’s two 32-bit C28x DSP cores, provides 400 MHz of signal-processing performance for floating- or fixed-point code running from either on-chip flash or SRAM

Provides 400 MHz of signal-processing performance for floating- or fixed-point code running from either on-chip flash or SRAM.

CLA: Allows user to execute time-critical control loops concurrently with main CPU

FPU64: Native hardware support for IEEE-754 double-precision floating-point operations

TMU: Accelerators used to speed up execution of trigonometric and arithmetic operations for faster computation (such as PLL and DQ transform) optimized for control applications. Helps in achieving faster control loops, resulting in higher efficiency and better component sizing.

Special instructions to support nonlinear PID control algorithms

VCRC: Provides a straightforward method for verifying data integrity over large data blocks, communication packets, or code sections.

FINTDIV: Supports linear division operations such as Euclidean and Modulus division used in control algorithms

See Real-time Benchmarks Showcasing C2000™ControlMCU's Optimized Signal Chain.
SENSING
Analog-to-Digital Converter (ADC) (configurable 12-bit or 16-bit)

Four ADC modules

16-bit mode: (1.1 MSPS)

Single-ended mode: Up to 24 channels

Differential mode : Up to 12 channels

12-bit mode: (3.5 MSPS)

Single-ended mode: Up to 24 channels

ADC provides precise and concurrent sampling of all three-phase currents and DC bus with zero jitter.

ADC post-processing – On-chip hardware reduces ADC ISR complexity and shortens current loop cycles.

More ADCs help in multiphase applications. Provide better effective MSPS (oversampling) and typical ENOB for better control-loop performance.

Comparator Subsystem (CMPSS) CMPSS

8 windowed comparators

Three 12-bit DACs

60-ns detection to trip time

DAC ramp generation

Low DAC output on external pin

Digital filters

Slope compensation

System protection without false alarms:

Comparator Subsystem (CMPSS) modules are useful for applications such as peak-current mode control, switched-mode power, power factor correction, and voltage trip monitoring.

PWM trip-triggering and removal of unwanted noise are easy with blanking window and filtering features provided with the analog comparator subsystems.

Provides better control accuracy. No need for further CPU configuration to control the PWM with the comparator and 12-bit DAC (CMPSS).

Enables protection and control using the same pin.
Sigma Delta Filter Module (SDFM)

Up to 8 independently configurable digital comparator filter channels

Up to 8 independently configurable digital data filter channels

Enables galvanic isolation with reinforced delta sigma modulators.

SDFMs interface with external delta sigma modulator ADCs, which is ideal for signals that may require isolation.

Comparator filter supports overcurrent and undercurrent protection but tripping the PWM without CPU intervention

Digital data filter provides higher ENOBs for better control-loop performance
Enhanced Quadrature Encoder Pulse (eQEP) 3 eQEP modules Used for direct interface with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine used in a high-performance motion and position-control system. Also can be used in other applications to count input pulses from an external device (such as a sensor).
Enhanced Capture (eCAP)/High Resolution Enhanced Capture (HRCAP)

7 eCAP modules (2 with HRCAP capability)

Measures elapsed time between events (up to 4 time-stamped events).

Connects to any GPIO through the input X-BAR.

When not used in capture mode, the eCAP module can be configured as a single-channel PWM output (APWM).

Applications for eCAP include:

Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall sensors)

Elapsed time measurements between position sensor pulses

Period and duty-cycle measurements of pulse train signals

Decoding current or voltage amplitude derived from duty-cycle encoded current/voltage sensors

2 HRCAP channels

Provides the capability to measure the width of external pulses with a typical resolution of 300 ps.

Applications for HRCAP include:

High-resolution period and duty-cycle measurements of pulse train cycles

Instantaneous speed measurements

Instantaneous frequency measurements

Voltage measurements across an isolation boundary

Distance/sonar measurement and scanning

Flow measurements

Capacitive touch applications
ACTUATION
Enhanced Pulse Width Modulation (ePWM)/High-Resolution Pulse Width Modulation (HRPWM)

Up to 32 ePWM channels

Ability to generate high-side/low-side PWMs with deadband

Supports Valley switching (ability to switch PWM output at valley point) and features like blanking window

Flexible PWM waveform generation with best power topology coverage.

Shadowed Dead band itself and shadowed action qualifier enable adaptive PWM generation and protection for improved control accuracy and reduced power loss.

Enables improvement in Power Factor (PF) and Total Harmonic Distortion (THD), which is especially relevant in Power Factor Correction (PFC) applications. Improves light load efficiency.

HRPWM capability:

All the 16 channels provide high-resolution capability (150 ps)

Provides 150-ps steps for duty cycle, period, deadband, and phase offsets for 99% greater precision

Beneficial for accurate control and enables better-performance high-frequency power conversion.

Achieves cleaner waveforms and avoids oscillations/limit cycle at output.

One-shot and global reload feature

Critical for variable-frequency and multiphase DC-DC applications and helps in attaining high-frequency control loops (>2 MHz).

Enables control of interleaved LLC topologies at high frequencies

Independent PWM action on a Cycle-by-Cycle (CBC) trip event and an One-Shot Trip (OST) trip event

 Provides cycle-by-cycle protection and complete shutoff of PWM under fault condition. Helps implement multiphase PFC or DC-DC control.
Load on SYNC (support for shadow-to-active load on a SYNC event) Enables variable-frequency applications (allows LLC control in power conversion).
Ability to shut down the PWMs without software intervention (no ISR latency) Fast protection under fault condition
Delayed Trip Functionality Helps implement the deadband with Peak Current Mode Control (PCMC) Phase-Shifted Full Bride (PSFB) DC-DC easily without occupying much CPU resources (even on trigger events based on comparator, trip, or sync-in events).
Dead band Generator (DB) submodule Prevents simultaneous ON conditions of High- and Low-side gates by adding programmable delay to rising (RED) and falling (FED) PWM signal edges.
Flexible PWM Phase Relationships and Timer Synchronization Each ePWM module can be synchronized with other ePWM modules or other peripherals. Keeps PWM edges perfectly in synchronization with certain events.

Supports flexible ADC scheduling with specific sampling window in synchronization with power device switching.
CONNECTIVITY
Fast Serial Interface (FSI) Up to 2 FSI transmitters and 8 FSI receivers

Serial communication peripheral capable of reliable high-speed communication (up to 200 MHz) across isolation devices

 More flexible communications options. Fast serial interface can be useful for low-pin count, high-speed communication even across isolation boundary at up to 200Mbps.
Serial Peripheral Interface (SPI) 4 high-speed SPI port Supports 50 MHz
Serial Communication Interface (SCI) 4 SCI (UART) modules Interfaces with controllers
Controller Area Network (CAN/DCAN) 2 DCAN module

(can be assigned to Connectivity Manager (M4))

 Provides compatibility with classic CAN modules
Controller Area Network (CAN FD/MCAN) 1 CAN FD/MCAN module

[can be assigned to Connectivity Manager (M4)]

 CAN FD (flexible data-rate) is an enhancement to the classic CAN protocol. CAN FD facilitates dynamic switching to higher bit rates (>1 Mbps) for the data segment and allows for up to 64 bytes compared to 8 bytes in classic CAN. This is done without having to change the physical layer. This results in a bandwidth gain over traditional CAN. Systems using CAN FD benefit from faster in-the-field flash updates.
Inter-Integrated Circuit (I2C) 2 I2C modules Interfaces with external EEPROMs, sensors, or controllers
Multichannel Buffered Serial Port (McBSP) Up to 2 McBSP modules Interface to high-speed external ADC or additional SPI peripheral
Power-Management Bus (PMBus)

1 PMBus module

Compliance with the SMI Forum PMBus Specification (Part I v1.0 and Part II v1.1)

 Seamless HW-based host communication
External Memory Interfaces (EMIFs) with ASRAM and SDRAM support Two EMIF modules, to have a dedicated EMIF for each CPU subsystem. Interface with External ASRAM and SDRAM
OTHER SYSTEM FEATURES
Configurable Logic Block (CLB)

Collection of configurable blocks that can be inter-connected using software to implement custom digital logic functions

User customized PWM protection features, custom logic to off-load complex algorithms/state machines, custom peripherals, and used to implement absolute encoders used in servo drives

User also used for protection of multilevel inverter/PFC or multilevel DC-DC

Provides the ability to build logic around existing IPs like ETPWM, ECAP, QEP and GPIOs.

Enables development of unique IP such as PWM Safety modules, Encoder engines, etc.
Security enhancers

Dual-zone Code Security Module (DCSM)

Secure Boot

JTAGLOCK

AES acceleration

BackGround CRC (BGCRC)

Generic CRC (GCRC)

Watchdog

Write Protection on Register

Missing Clock Detection Logic (MCD)

Error Correction Code (ECC) and parity

Dual-Clock Comparator (DCC)

DCSM: Prevents duplication and reverse-engineering of proprietary code

Secure Boot: Uses AES128 CMAC algorithm to ensure code that runs on the device is authentic

JTAGLOCK: Ability to block emulation of the device

AES acceleration: The hardware accelerator vastly improves the cycle time of processing cryptographic messages while freeing up the CPU bandwidth

BGCRC: Checks memory integrity with no CPU overhead or system performance impact

GCRC: Designated Connectivity Manager module for computing the CRC value on a configurable block of memory

Watchdog: Generates reset if CPU gets stuck in endless loops of execution

Write Protection on Registers:

LOCK protection on system configuration registers

Protection against spurious CPU writes

MCD: Automatic clock failure detection

ECC and parity: Single-bit error correction and double-bit error detection

DCC: Used to detect faults in clock source
Crossbars (XBARs)

Provides flexibility to connect device inputs, outputs, and internal resources in a variety of configurations.

• Input X-BAR

• Output X-BAR

• ePWM X-BAR

• CLB Input X-BAR

• CLB Output X-BAR

• CLB X-BAR

Enhances hardware design versatility:

Input X-BAR: Routes signals from any GPIO to multiple IP blocks within the chip

Output XBAR: Routes internal signals onto designated GPIO pins

ePWM X-BAR: Routes internal signals from various IP blocks to ePWM

CLB Input X-BAR: Allows user to route signals directly from any GPIO to Configurable Logic Block (CLB)

CLB Output X-BAR: Allows user to bring signals from CLB tiles to designated GPIO pins

CLB X-BAR: Allows user to bring signals from various IP blocks to CLB
M4 PROCESSING
Real-time connectivity

Dedicated, fully programmable

communications sub-system Arm® Cortex®-M4

Up to 125 MIPS

Flash: 512KB

RAM : 96KB

 Enables communication in parallel with real-time control. This increases overall system performance without sacrificing critical timing within the real-time control subsystem.
Micro Direct Memory Access (μDMA) controller 32-channels The direct memory access (DMA) module provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up CPU bandwidth for other system functions.
Ethernet MAC Supports Industrial networking and factory automation
EtherCAT Integrated EtherCAT® Slave Controller (ESC) IP invented by Beckhoff Automation™ Develop Industrial Ethernet-based fieldbus systems with low latency and cycle times. Takes advantage of the "on-the-fly" frame processing and forwarding nature of EtherCAT hardware. Run an EtherCAT slave stack and application software to implement an EtherCAT slave node.
USB Useful for system datalogging and boot to USB for updating on-chip flash