SPRSP14E may 2019 – june 2023 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
NO. | PARAMETER | (BRR + 1) CONDITION(1) | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
General | ||||||
1 | tc(SPC)M | Cycle time, SPICLK | Even | 4tc(LSPCLK) | 128tc(LSPCLK) | ns |
Odd | 5tc(LSPCLK) | 127tc(LSPCLK) | ||||
2 | tw(SPC1)M | Pulse duration, SPICLK, first pulse | Even | 0.5tc(SPC)M – 1 | 0.5tc(SPC)M + 1 | ns |
Odd | 0.5tc(SPC)M +0.5tc(LSPCLK) – 1 | 0.5tc(SPC)M +0.5tc(LSPCLK) + 1 | ||||
3 | tw(SPC2)M | Pulse duration, SPICLK, second pulse | Even | 0.5tc(SPC)M – 1 | 0.5tc(SPC)M + 1 | ns |
Odd | 0.5tc(SPC)M –0.5tc(LSPCLK) – 1 | 0.5tc(SPC)M –0.5tc(LSPCLK) + 1 | ||||
23 | td(SPC)M | Delay time, SPISTE active to SPICLK | Even | 1.5tc(SPC)M –3tc(SYSCLK) – 3 | 1.5tc(SPC)M –3tc(SYSCLK) + 3 | ns |
Odd | 1.5tc(SPC)M –4tc(SYSCLK) – 3 | 1.5tc(SPC)M –4tc(SYSCLK) + 3 | ||||
24 | tv(STE)M | Valid time, SPICLK to SPISTE inactive | Even | 0.5tc(SPC)M – 3 | 0.5tc(SPC)M + 3 | ns |
Odd | 0.5tc(SPC)M –0.5tc(LSPCLK) – 3 | 0.5tc(SPC)M –0.5tc(LSPCLK) + 3 | ||||
High-Speed Mode | ||||||
4 | td(SIMO)M | Delay time, SPICLK to SPISIMO valid | Even, Odd | 1 | ns | |
5 | tv(SIMO)M | Valid time, SPISIMO valid after SPICLK | Even | 0.5tc(SPC)M – 1 | ns | |
Odd | 0.5tc(SPC)M –0.5tc(LSPCLK) – 1 | |||||
Normal Mode | ||||||
4 | td(SIMO)M | Delay time, SPICLK to SPISIMO valid | Even, Odd | 5 | ns | |
5 | tv(SIMO)M | Valid time, SPISIMO valid after SPICLK | Even | 0.5tc(SPC)M – 3 | ns | |
Odd | 0.5tc(SPC)M –0.5tc(LSPCLK) – 3 |