SPRSP14E may   2019  – june 2023 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Revision History
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1 Analog Signals
      2. 6.3.2 Digital Signals
      3. 6.3.3 Power and Ground
      4. 6.3.4 Test, JTAG, and Reset
    4. 6.4 Pins With Internal Pullup and Pulldown
    5. 6.5 Pin Multiplexing
      1. 6.5.1 GPIO Muxed Pins Table
      2. 6.5.2 Input X-BAR
      3. 6.5.3 Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
      4. 6.5.4 USB Pin Muxing
      5. 6.5.5 High-Speed SPI Pin Muxing
      6. 6.5.6 High-Speed SSI Pin Muxing
    6. 6.6 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 System Current Consumption (External Supply)
      2. 7.5.2 Operating Mode Test Description
      3. 7.5.3 Current Consumption Graphs
      4. 7.5.4 Reducing Current Consumption
        1. 7.5.4.1 Typical Current Reduction per Disabled Peripheral
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics for ZWT Package
    8. 7.8  Thermal Resistance Characteristics for PTP Package
    9. 7.9  Thermal Design Considerations
    10. 7.10 System
      1. 7.10.1  Power Management Module (PMM)
        1. 7.10.1.1 Introduction
        2. 7.10.1.2 Overview
          1. 7.10.1.2.1 Power Rail Monitors
          2. 7.10.1.2.2 I/O POR (Power-On Reset) Monitor
          3. 7.10.1.2.3 VDD POR (Power-On Reset) Monitor
          4. 7.10.1.2.4 External Supervisor Usage
          5. 7.10.1.2.5 Delay Blocks
        3. 7.10.1.3 External Components
          1. 7.10.1.3.1 Decoupling Capacitors
          2. 7.10.1.3.2 VDDIO Decoupling
        4. 7.10.1.4 Power Sequencing
          1. 7.10.1.4.1 Supply Pins Ganging
          2. 7.10.1.4.2 Signal Pins Power Sequence
          3. 7.10.1.4.3 Supply Pins Power Sequence
            1. 7.10.1.4.3.1 Power Supply Sequence
            2. 7.10.1.4.3.2 Supply Sequencing Summary and Effects of Violations
            3. 7.10.1.4.3.3 Supply Slew Rate
        5. 7.10.1.5 Power Management Module Electrical Data and Timing
          1. 7.10.1.5.1 Power Management Module Operating Conditions
          2. 7.10.1.5.2 Power Management Module Characteristics
      2. 7.10.2  Reset Timing
        1. 7.10.2.1 Reset Sources
        2. 7.10.2.2 Reset Electrical Data and Timing
          1. 7.10.2.2.1 Reset (XRSn) Timing Requirements
          2. 7.10.2.2.2 Reset (XRSn) Switching Characteristics
          3. 7.10.2.2.3 Reset Timing Diagrams
      3. 7.10.3  Clock Specifications
        1. 7.10.3.1 Clock Sources
        2. 7.10.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 7.10.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 7.10.3.2.1.1 Input Clock Frequency
            2. 7.10.3.2.1.2 XTAL Oscillator Characteristics
            3. 7.10.3.2.1.3 X1 Timing Requirements
            4. 7.10.3.2.1.4 AUXCLKIN Timing Requirements
            5. 7.10.3.2.1.5 APLL Characteristics
          2. 7.10.3.2.2 Internal Clock Frequencies
            1. 7.10.3.2.2.1 Internal Clock Frequencies
          3. 7.10.3.2.3 Output Clock Frequency and Switching Characteristics
            1. 7.10.3.2.3.1 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        3. 7.10.3.3 Input Clocks
        4. 7.10.3.4 XTAL Oscillator
          1. 7.10.3.4.1 Introduction
          2. 7.10.3.4.2 Overview
            1. 7.10.3.4.2.1 Electrical Oscillator
              1. 7.10.3.4.2.1.1 Modes of Operation
                1. 7.10.3.4.2.1.1.1 Crystal Mode of Operation
                2. 7.10.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 7.10.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 7.10.3.4.2.2 Quartz Crystal
            3. 7.10.3.4.2.3 GPIO Modes of Operation
          3. 7.10.3.4.3 Functional Operation
            1. 7.10.3.4.3.1 ESR – Effective Series Resistance
            2. 7.10.3.4.3.2 Rneg – Negative Resistance
            3. 7.10.3.4.3.3 Start-up Time
              1. 7.10.3.4.3.3.1 X1/X2 Precondition
            4. 7.10.3.4.3.4 DL – Drive Level
          4. 7.10.3.4.4 How to Choose a Crystal
          5. 7.10.3.4.5 Testing
          6. 7.10.3.4.6 Common Problems and Debug Tips
          7. 7.10.3.4.7 Crystal Oscillator Specifications
            1. 7.10.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 7.10.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 7.10.3.4.7.3 Crystal Oscillator Parameters
            4. 7.10.3.4.7.4 Crystal Oscillator Electrical Characteristics
        5. 7.10.3.5 Internal Oscillators
          1. 7.10.3.5.1 INTOSC Characteristics
      4. 7.10.4  Flash Parameters
        1. 7.10.4.1 Flash Parameters 
        2.       111
      5. 7.10.5  RAM Specifications
      6. 7.10.6  ROM Specifications
      7. 7.10.7  Emulation/JTAG
        1. 7.10.7.1 JTAG Electrical Data and Timing
          1. 7.10.7.1.1 JTAG Timing Requirements
          2. 7.10.7.1.2 JTAG Switching Characteristics
          3. 7.10.7.1.3 JTAG Timing
      8. 7.10.8  GPIO Electrical Data and Timing
        1. 7.10.8.1 GPIO - Output Timing
          1. 7.10.8.1.1 General-Purpose Output Switching Characteristics
          2. 7.10.8.1.2 General-Purpose Output Timing
        2. 7.10.8.2 GPIO - Input Timing
          1. 7.10.8.2.1 General-Purpose Input Timing Requirements
          2. 7.10.8.2.2 Sampling Mode
        3. 7.10.8.3 Sampling Window Width for Input Signals
      9. 7.10.9  Interrupts
        1. 7.10.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 7.10.9.1.1 External Interrupt Timing Requirements
          2. 7.10.9.1.2 External Interrupt Switching Characteristics
          3. 7.10.9.1.3 External Interrupt Timing
      10. 7.10.10 Low-Power Modes
        1. 7.10.10.1 Clock-Gating Low-Power Modes
        2. 7.10.10.2 Low-Power Mode Wakeup Timing
          1. 7.10.10.2.1 IDLE Mode Timing Requirements
          2. 7.10.10.2.2 IDLE Mode Switching Characteristics
          3. 7.10.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 7.10.10.2.4 STANDBY Mode Timing Requirements
          5. 7.10.10.2.5 STANDBY Mode Switching Characteristics
          6. 7.10.10.2.6 STANDBY Entry and Exit Timing Diagram
      11. 7.10.11 External Memory Interface (EMIF)
        1. 7.10.11.1 Asynchronous Memory Support
        2. 7.10.11.2 Synchronous DRAM Support
        3. 7.10.11.3 EMIF Electrical Data and Timing
          1. 7.10.11.3.1 Asynchronous RAM
            1. 7.10.11.3.1.1 EMIF Asynchronous Memory Timing Requirements
            2. 7.10.11.3.1.2 EMIF Asynchronous Memory Switching Characteristics
            3. 7.10.11.3.1.3 EMIF Asynchronous Memory Timing Diagrams
          2. 7.10.11.3.2 Synchronous RAM
            1. 7.10.11.3.2.1 EMIF Synchronous Memory Timing Requirements
            2. 7.10.11.3.2.2 EMIF Synchronous Memory Switching Characteristics
            3. 7.10.11.3.2.3 EMIF Synchronous Memory Timing Diagrams
    11. 7.11 C28x Analog Peripherals
      1. 7.11.1 Analog Subsystem
      2. 7.11.2 Analog-to-Digital Converter (ADC)
        1. 7.11.2.1 Result Register Mapping
        2. 7.11.2.2 ADC Configurability
          1. 7.11.2.2.1 Signal Mode
        3. 7.11.2.3 ADC Electrical Data and Timing
          1. 7.11.2.3.1 ADC Operating Conditions (16-bit Differential)
            1. 7.11.2.3.1.1 ADC Operating Conditions (16-bit Differential) Notes
          2. 7.11.2.3.2 ADC Characteristics (16-bit Differential)
          3. 7.11.2.3.3 ADC Operating Conditions (16-bit Single-Ended)
            1. 7.11.2.3.3.1 ADC Operating Conditions (16-bit Single-Ended) Notes
          4. 7.11.2.3.4 ADC Characteristics (16-bit Single-Ended)
          5. 7.11.2.3.5 ADC Operating Conditions (12-bit Single-Ended)
            1. 7.11.2.3.5.1 ADC Operating Conditions (12-bit Single-Ended) Notes
          6. 7.11.2.3.6 ADC Characteristics (12-bit Single-Ended)
          7. 7.11.2.3.7 ADCEXTSOC Timing Requirements
          8. 7.11.2.3.8 ADC Input Models
            1. 7.11.2.3.8.1 Single-Ended Input Model Parameters (12-bit Resolution)
            2. 7.11.2.3.8.2 Single-Ended Input Model Parameters (16-bit Resolution)
            3. 7.11.2.3.8.3 Single-Ended Input Model
            4. 7.11.2.3.8.4 Differential Input Model Parameters (16-bit Resolution)
            5. 7.11.2.3.8.5 Differential Input Model
          9. 7.11.2.3.9 ADC Timing Diagrams
            1. 7.11.2.3.9.1 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
            2. 7.11.2.3.9.2 ADC Timings in 16-Bit Mode
        4. 7.11.2.4 Temperature Sensor Electrical Data and Timing
          1. 7.11.2.4.1 Temperature Sensor Characteristics
      3. 7.11.3 Comparator Subsystem (CMPSS)
        1. 7.11.3.1 CMPSS Electrical Data and Timing
          1. 7.11.3.1.1 Comparator Electrical Characteristics
          2. 7.11.3.1.2 CMPSS Comparator Input Referred Offset and Hysteresis
          3. 7.11.3.1.3 CMPSS DAC Static Electrical Characteristics
          4. 7.11.3.1.4 CMPSS Illustrative Graphs
          5. 7.11.3.1.5 CMPSS DAC Dynamic Error
      4. 7.11.4 Buffered Digital-to-Analog Converter (DAC)
        1. 7.11.4.1 Buffered DAC Electrical Data and Timing
          1. 7.11.4.1.1 Buffered DAC Operating Conditions
          2. 7.11.4.1.2 Buffered DAC Electrical Characteristics
          3. 7.11.4.1.3 Buffered DAC Notes and Illustrative Graphs
    12. 7.12 C28x Control Peripherals
      1. 7.12.1 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
        1. 7.12.1.1 eCAP Synchronization
        2. 7.12.1.2 eCAP Electrical Data and Timing
          1. 7.12.1.2.1 eCAP Timing Requirements
          2. 7.12.1.2.2 eCAP Switching Charcteristics
        3. 7.12.1.3 HRCAP Electrical Data and Timing
          1. 7.12.1.3.1 HRCAP Switching Characteristics
          2. 7.12.1.3.2 HRCAP Graphs
      2. 7.12.2 Enhanced Pulse Width Modulator (ePWM)
        1. 7.12.2.1 Control Peripherals Synchronization
        2. 7.12.2.2 ePWM Electrical Data and Timing
          1. 7.12.2.2.1 ePWM Timing Requirements
          2. 7.12.2.2.2 ePWM Switching Characteristics
          3. 7.12.2.2.3 Trip-Zone Input Timing
            1. 7.12.2.2.3.1 Trip-Zone Input Timing Requirements
        3. 7.12.2.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 7.12.2.3.1 External ADC Start-of-Conversion Switching Characteristics
      3. 7.12.3 High-Resolution Pulse Width Modulator (HRPWM)
        1. 7.12.3.1 HRPWM Electrical Data and Timing
          1. 7.12.3.1.1 High-Resolution PWM Characteristics
      4. 7.12.4 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.12.4.1 eQEP Electrical Data and Timing
          1. 7.12.4.1.1 eQEP Timing Requirements
          2. 7.12.4.1.2 eQEP Switching Characteristics
      5. 7.12.5 Sigma-Delta Filter Module (SDFM)
        1. 7.12.5.1 SDFM Electrical Data and Timing (Using ASYNC)
          1. 7.12.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
          2. 7.12.5.1.2 SDFM Timing Diagram
    13. 7.13 C28x Communications Peripherals
      1. 7.13.1 Controller Area Network (CAN)
      2. 7.13.2 Fast Serial Interface (FSI)
        1. 7.13.2.1 FSI Transmitter
          1. 7.13.2.1.1 FSITX Electrical Data and Timing
            1. 7.13.2.1.1.1 FSITX Switching Characteristics
            2. 7.13.2.1.1.2 FSITX Timings
        2. 7.13.2.2 FSI Receiver
          1. 7.13.2.2.1 FSIRX Electrical Data and Timing
            1. 7.13.2.2.1.1 FSIRX Timing Requirements
            2. 7.13.2.2.1.2 FSIRX Switching Characteristics
            3. 7.13.2.2.1.3 FSIRX Timing Diagram
        3. 7.13.2.3 SPI Signaling Mode
          1. 7.13.2.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 7.13.2.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 7.13.2.3.1.2 FSITX SPI Signaling Mode Timings
      3. 7.13.3 Inter-Integrated Circuit (I2C)
        1. 7.13.3.1 I2C Electrical Data and Timing
          1. 7.13.3.1.1 I2C Timing Requirements
          2. 7.13.3.1.2 I2C Switching Characteristics
          3. 7.13.3.1.3 I2C Timing Diagram
      4. 7.13.4 Multichannel Buffered Serial Port (McBSP)
        1. 7.13.4.1 McBSP Electrical Data and Timing
          1. 7.13.4.1.1 McBSP Transmit and Receive Timing
            1. 7.13.4.1.1.1 McBSP Timing Requirements
            2. 7.13.4.1.1.2 McBSP Switching Characteristics
            3. 7.13.4.1.1.3 McBSP Receive and Transmit Timing Diagrams
          2. 7.13.4.1.2 McBSP as SPI Master or Slave Timing
            1. 7.13.4.1.2.1 McBSP as SPI Master Timing Requirements
            2. 7.13.4.1.2.2 McBSP as SPI Master Switching Characteristics
            3. 7.13.4.1.2.3 McBSP as SPI Slave Timing Requirements
            4. 7.13.4.1.2.4 McBSP as SPI Slave Switching Characteristics
            5. 7.13.4.1.2.5 McBSP as SPI Master or Slave Timing Diagrams
      5. 7.13.5 Power Management Bus (PMBus)
        1. 7.13.5.1 PMBus Electrical Data and Timing
          1. 7.13.5.1.1 PMBus Electrical Characteristics
          2. 7.13.5.1.2 PMBus Fast Mode Switching Characteristics
          3. 7.13.5.1.3 PMBus Standard Mode Switching Characteristics
      6. 7.13.6 Serial Communications Interface (SCI)
      7. 7.13.7 Serial Peripheral Interface (SPI)
        1. 7.13.7.1 SPI Electrical Data and Timing
          1. 7.13.7.1.1 SPI Master Mode Timings
            1. 7.13.7.1.1.1 SPI Master Mode Timing Requirements
            2. 7.13.7.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            3. 7.13.7.1.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            4. 7.13.7.1.1.4 SPI Master Mode External Timing
          2. 7.13.7.1.2 SPI Slave Mode Timings
            1. 7.13.7.1.2.1 SPI Slave Mode Timing Requirements
            2. 7.13.7.1.2.2 SPI Slave Mode Switching Characteristics
            3. 7.13.7.1.2.3 SPI Slave Mode External Timing
      8. 7.13.8 EtherCAT Slave Controller (ESC)
        1. 7.13.8.1 ESC Features
        2. 7.13.8.2 ESC Subsystem Integrated Features
        3. 7.13.8.3 EtherCAT IP Block Diagram
        4. 7.13.8.4 EtherCAT Electrical Data and Timing
          1. 7.13.8.4.1 EtherCAT Timing Requirements
          2. 7.13.8.4.2 EtherCAT Switching Characteristics
          3. 7.13.8.4.3 EtherCAT Timing Diagrams
      9. 7.13.9 Universal Serial Bus (USB) Controller
        1. 7.13.9.1 USB Electrical Data and Timing
          1. 7.13.9.1.1 USB Input Ports DP and DM Timing Requirements
          2. 7.13.9.1.2 USB Output Ports DP and DM Switching Characteristics
    14. 7.14 Connectivity Manager (CM) Peripherals
      1. 7.14.1 Modular Controller Area Network (MCAN) [CAN FD]
      2. 7.14.2 Ethernet Media Access Controller (EMAC)
        1. 7.14.2.1 MAC Features
          1. 7.14.2.1.1 MAC Tx and Rx Features
          2. 7.14.2.1.2 MAC Tx Features
          3. 7.14.2.1.3 MAC Rx Features
        2. 7.14.2.2 Ethernet Electrical Data and Timing
          1. 7.14.2.2.1 Ethernet Timing Requirements
          2. 7.14.2.2.2 Ethernet Switching Characteristics
          3. 7.14.2.2.3 Ethernet Timing Diagrams
        3. 7.14.2.3 Ethernet REVMII Electrical Data and Timing
          1. 7.14.2.3.1 Ethernet REVMII Timing Requirements
          2. 7.14.2.3.2 Ethernet REVMII Switching Characteristics
      3. 7.14.3 Inter-Integrated Circuit (CM-I2C)
        1. 7.14.3.1 CM-I2C Electrical Data and Timing
          1. 7.14.3.1.1 CM-I2C Timing Requirements
          2. 7.14.3.1.2 CM-I2C Switching Characteristics
          3. 7.14.3.1.3 CM-I2C Timing Diagram
      4. 7.14.4 Synchronous Serial Interface (SSI)
        1. 7.14.4.1 SSI Electrical Data and Timing
          1. 7.14.4.1.1 SSI Timing Requirements
          2. 7.14.4.1.2 SSI Characteristics
          3. 7.14.4.1.3 SSI Timing Diagrams
      5. 7.14.5 Universal Asynchronous Receiver/Transmitter (CM-UART)
      6. 7.14.6 Trace Port Interface Unit (TPIU)
        1. 7.14.6.1 TPIU Electrical Data and Timing
          1. 7.14.6.1.1 Trace Port Switching Characteristics
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Memory
      1. 8.3.1 C28x Memory Map
      2. 8.3.2 C28x Flash Memory Map
      3. 8.3.3 Peripheral Registers Memory Map
      4. 8.3.4 EMIF Chip Select Memory Map
      5. 8.3.5 CM Memory Map
      6. 8.3.6 CM Flash Memory Map
      7. 8.3.7 Peripheral Registers Memory Map (CM)
      8. 8.3.8 Memory Types
        1. 8.3.8.1 Dedicated RAM (Mx and Dx RAM)
        2. 8.3.8.2 Local Shared RAM (LSx RAM)
        3. 8.3.8.3 Global Shared RAM (GSx RAM)
        4. 8.3.8.4 CPU Message RAM (CPU MSGRAM)
        5. 8.3.8.5 CLA Message RAM (CLA MSGRAM)
        6. 8.3.8.6 CLA - DMA Message RAM (CLA-DMA MSGRAM)
        7. 8.3.8.7 CPUx - CM Message RAM (CPUx-CM MSGRAM)
        8. 8.3.8.8 Dedicated RAM (C0/C1 RAM)
        9. 8.3.8.9 Shared RAM (E0 and Sx RAM)
    4. 8.4  Identification
    5. 8.5  Bus Architecture – Peripheral Connectivity
    6. 8.6  Boot ROM and Peripheral Booting
      1. 8.6.1 Device Boot
      2. 8.6.2 Device Boot Modes
      3. 8.6.3 Device Boot Configurations
      4. 8.6.4 GPIO Assignments for CPU1
    7. 8.7  Dual Code Security Module (DCSM)
    8. 8.8  C28x (CPU1/CPU2) Subsystem
      1. 8.8.1  C28x Processor
        1. 8.8.1.1 Floating-Point Unit
        2. 8.8.1.2 Trigonometric Math Unit
        3. 8.8.1.3 Fast Integer Division Unit
        4. 8.8.1.4 VCRC Unit
      2. 8.8.2  Embedded Real-Time Analysis and Diagnostic (ERAD)
      3. 8.8.3  Background CRC-32 (BGCRC)
      4. 8.8.4  Control Law Accelerator (CLA)
      5. 8.8.5  Direct Memory Access (DMA)
      6. 8.8.6  Interprocessor Communication (IPC) Module
      7. 8.8.7  C28x Timers
      8. 8.8.8  Dual-Clock Comparator (DCC)
        1. 8.8.8.1 Features
        2. 8.8.8.2 Mapping of DCCx (DCC0, DCC1, and DCC2) Clock Source Inputs
      9. 8.8.9  Nonmaskable Interrupt With Watchdog Timer (NMIWD)
      10. 8.8.10 Watchdog
      11. 8.8.11 Configurable Logic Block (CLB)
    9. 8.9  Connectivity Manager (CM) Subsystem
      1. 8.9.1  Arm Cortex-M4 Processor
      2. 8.9.2  Nested Vectored Interrupt Controller (NVIC)
      3. 8.9.3  Advance Encryption Standard (AES) Accelerator
      4. 8.9.4  Generic Cyclic Redundancy Check (GCRC) Module
      5. 8.9.5  CM Nonmaskable Interrupt (CMNMI) Module
      6. 8.9.6  Memory Protection Unit (MPU)
      7. 8.9.7  Micro Direct Memory Access (µDMA)
      8. 8.9.8  Watchdog
      9. 8.9.9  CM Clocking
        1. 8.9.9.1 CM Clock Sources
      10. 8.9.10 CM Timers
    10. 8.10 Functional Safety
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application and Implementation
    2. 9.2 Key Device Features
    3. 9.3 Application Information
      1. 9.3.1 Typical Application
        1. 9.3.1.1 High-Voltage Traction Inverter
          1. 9.3.1.1.1 System Block Diagram
          2. 9.3.1.1.2 High-Voltage Traction Inverter Resources
        2. 9.3.1.2 On-Board Charger (OBC)
          1. 9.3.1.2.1 System Block Diagram
          2. 9.3.1.2.2 OBC Resources
        3. 9.3.1.3 Servo Drive Control Module
          1. 9.3.1.3.1 System Block Diagram
          2. 9.3.1.3.2 Servo Drive Control Module Resources
        4. 9.3.1.4 Solar Micro Inverter
          1. 9.3.1.4.1 System Block Diagram
          2. 9.3.1.4.2 Solar Micro Inverter Resources
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Markings
    4. 10.4 Tools and Software
    5. 10.5 Documentation Support
    6. 10.6 Support Resources
    7. 10.7 Trademarks
    8. 10.8 Electrostatic Discharge Caution
    9. 10.9 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZWT|337
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.2 Digital Signals

Table 6-3 Digital Signals
SIGNAL NAME DESCRIPTION PIN TYPE GPIO PIN 337 BGA PIN 176 Pin PIN
ADCSOCAO ADC Start of Conversion A Output for External ADC (from ePWM modules) O 8 G2 18
ADCSOCBO ADC Start of Conversion B Output for External ADC (from ePWM modules) O 10 B2 1
AUXCLKIN Auxiliary Clock Input I 133 G18 118
CANA_RX CAN-A Receive I 18, 30, 36, 5, 61, 62, 70 A17, D7, E3, J17, L16, T11, V16 10, 107, 108, 135, 165, 63, 83
CANA_TX CAN-A Transmit O 19, 31, 37, 4, 62, 63, 71 B17, C7, E4, J16, J17, U11, U16 108, 109, 12, 136, 164, 66, 84
CANB_RX CAN-B Receive I 10, 13, 17, 21, 39, 7, 73 A16, B2, B6, D1, E2, F3, W17 1, 14, 140, 167, 5, 86, 9
CANB_TX CAN-B Transmit O 12, 16, 20, 38, 6, 72, 8 A6, B16, C2, E1, F2, G2, T16 13, 139, 166, 18, 4, 8, 85
CLB_OUTPUTXBAR1 CLB Output X-BAR Output 1 O 32, 91 B5, U13 173, 67
CLB_OUTPUTXBAR2 CLB Output X-BAR Output 2 O 33, 92 A4, T13 174, 69
CLB_OUTPUTXBAR3 CLB Output X-BAR Output 3 O 34, 93 B4, U14 175, 70
CLB_OUTPUTXBAR4 CLB Output X-BAR Output 4 O 35, 94 A3, T14 176, 71
CLB_OUTPUTXBAR5 CLB Output X-BAR Output 5 O 36, 95 B3, V16 83
CLB_OUTPUTXBAR6 CLB Output X-BAR Output 6 O 37, 96 C3, U16 84
CLB_OUTPUTXBAR7 CLB Output X-BAR Output 7 O 38, 97 A2, T16 85
CLB_OUTPUTXBAR8 CLB Output X-BAR Output 8 O 39, 98 F1, W17 86
CM-I2CA_SCL CM-I2C-A Open-Drain Bidirectional Clock I/OD 1, 105, 32 D8, J3, U13 161, 67
CM-I2CA_SDA CM-I2C-A Open-Drain Bidirectional Data I/OD 104, 31 C8, J2, U11 160, 66
EMIF1_CAS External memory interface 1 column address strobe O 23, 86, 89 C11, D6, K4 156, 171, 23
EMIF1_CLK External memory interface 1 clock O 30 T11 63
EMIF1_OEn External memory interface 1 output enable O 32, 37 U13, U16 67, 84
EMIF1_RAS External memory interface 1 row address strobe O 22, 87, 90 A5, D11, J4 157, 172, 22
EMIF1_RNW External memory interface 1 read not write O 31, 33 T13, U11 66, 69
EMIF1_SDCKE External memory interface 1 SDRAM clock enable O 29 W11 65
EMIF1_WAIT External memory interface 1 Asynchronous SRAM WAIT I 36 V16 83
EMIF1_WEn External memory interface 1 write enable O 31 U11 66
EMIF2_CAS External memory interface 2 column address strobe O 113 N4
EMIF2_CLK External memory interface 2 clock O 118 T12
EMIF2_OEn External memory interface 2 output enable O 121 W16
EMIF2_RAS External memory interface 2 row address strobe O 114 N3
EMIF2_RNW External memory interface 2 read not write O 119 T15
EMIF2_SDCKE External memory interface 2 SDRAM clock enable O 117 U12
EMIF2_WAIT External memory interface 2 Asynchronous SRAM WAIT I 110 M2
EMIF2_WEn External memory interface 2 write enable O 120 U15
EMIF1_A0 External memory interface 1 address line 0 O 35, 38 T14, T16 71, 85
EMIF1_A1 External memory interface 1 address line 1 O 36, 39 V16, W17 83, 86
EMIF1_A2 External memory interface 1 address line 2 O 37, 40 U16, V17 84, 87
EMIF1_A3 External memory interface 1 address line 3 O 38, 41 T16, U17 85, 89
EMIF1_A4 External memory interface 1 address line 4 O 39, 44 K18, W17 113, 86
EMIF1_A5 External memory interface 1 address line 5 O 45, 49 K19, R17 115, 93
EMIF1_A6 External memory interface 1 address line 6 O 46, 50 E19, R18 128, 94
EMIF1_A7 External memory interface 1 address line 7 O 47, 51 E18, R19 129, 95
EMIF1_A8 External memory interface 1 address line 8 O 48, 52 P16, R16 90, 96
EMIF1_A9 External memory interface 1 address line 9 O 49, 53 P17, R17 93, 97
EMIF1_A10 External memory interface 1 address line 10 O 50, 54 P18, R18 94, 98
EMIF1_A11 External memory interface 1 address line 11 O 51 R19 95
EMIF1_A12 External memory interface 1 address line 12 O 52 P16 96
EMIF1_A13 External memory interface 1 address line 13 O 86 C11 156
EMIF1_A14 External memory interface 1 address line 14 O 87 D11 157
EMIF1_A15 External memory interface 1 address line 15 O 88 C6 170
EMIF1_A16 External memory interface 1 address line 16 O 89 D6 171
EMIF1_A17 External memory interface 1 address line 17 O 90 A5 172
EMIF1_A18 External memory interface 1 address line 18 O 91 B5 173
EMIF1_A19 External memory interface 1 address line 19 O 92 A4 174
EMIF1_BA0 External memory interface 1 bank address 0 O 20, 33, 93 B4, F2, T13 13, 175, 69
EMIF1_BA1 External memory interface 1 bank address 1 O 21, 34, 92, 94 A3, A4, F3, U14 14, 174, 176, 70
EMIF1_CS0n External memory interface 1 chip select 0 O 32 U13 67
EMIF1_CS2n External memory interface 1 chip select 2 O 18, 28, 34 E3, U14, V11 10, 64, 70
EMIF1_CS3n External memory interface 1 chip select 3 O 19, 29, 35 E4, T14, W11 12, 65, 71
EMIF1_CS4n External memory interface 1 chip select 4 O 28, 30 T11, V11 63, 64
EMIF1_D0 External memory interface 1 data line 0 I/O 55, 85 B11, P19 100, 155
EMIF1_D1 External memory interface 1 data line 1 I/O 56, 83 C14, N16 101, 151
EMIF1_D2 External memory interface 1 data line 2 I/O 57, 82 B14, N18 102, 150
EMIF1_D3 External memory interface 1 data line 3 I/O 58, 81 A14, N17 103, 149
EMIF1_D4 External memory interface 1 data line 4 I/O 59, 80 D15, M16 104, 148
EMIF1_D5 External memory interface 1 data line 5 I/O 60, 79 C15, M17 105, 146
EMIF1_D6 External memory interface 1 data line 6 I/O 61, 78 B15, L16 107, 145
EMIF1_D7 External memory interface 1 data line 7 I/O 62, 77 A15, J17 108, 144
EMIF1_D8 External memory interface 1 data line 8 I/O 76 C16 143
EMIF1_D9 External memory interface 1 data line 9 I/O 75 D16 142
EMIF1_D10 External memory interface 1 data line 10 I/O 74 C17 141
EMIF1_D11 External memory interface 1 data line 11 I/O 73 A16 140
EMIF1_D12 External memory interface 1 data line 12 I/O 72 B16 139
EMIF1_D13 External memory interface 1 data line 13 I/O 71 B17 136
EMIF1_D14 External memory interface 1 data line 14 I/O 70 A17 135
EMIF1_D15 External memory interface 1 data line 15 I/O 69 B18 134
EMIF1_D16 External memory interface 1 data line 16 I/O 68 C18 133
EMIF1_D17 External memory interface 1 data line 17 I/O 67 B19 132
EMIF1_D18 External memory interface 1 data line 18 I/O 66 K17 112
EMIF1_D19 External memory interface 1 data line 19 I/O 65 K16 111
EMIF1_D20 External memory interface 1 data line 20 I/O 64 L17 110
EMIF1_D21 External memory interface 1 data line 21 I/O 63 J16 109
EMIF1_D22 External memory interface 1 data line 22 I/O 62 J17 108
EMIF1_D23 External memory interface 1 data line 23 I/O 61 L16 107
EMIF1_D24 External memory interface 1 data line 24 I/O 60 M17 105
EMIF1_D25 External memory interface 1 data line 25 I/O 59 M16 104
EMIF1_D26 External memory interface 1 data line 26 I/O 58 N17 103
EMIF1_D27 External memory interface 1 data line 27 I/O 57 N18 102
EMIF1_D28 External memory interface 1 data line 28 I/O 56 N16 101
EMIF1_D29 External memory interface 1 data line 29 I/O 55 P19 100
EMIF1_D30 External memory interface 1 data line 30 I/O 54 P18 98
EMIF1_D31 External memory interface 1 data line 31 I/O 53 P17 97
EMIF1_DQM0 External memory interface 1 Input/output mask for byte 0 O 24, 88, 92 A4, C6, K3 170, 174, 24
EMIF1_DQM1 External memory interface 1 Input/output mask for byte 1 O 25, 88, 89 C6, D6, K2 170, 171, 25
EMIF1_DQM2 External memory interface 1 Input/output mask for byte 2 O 26, 90, 91 A5, B5, K1 172, 173, 27
EMIF1_DQM3 External memory interface 1 Input/output mask for byte 3 O 27, 87, 91 B5, D11, L1 157, 173, 28
EMIF2_A0 External memory interface 2 address line 0 O 98 F1
EMIF2_A1 External memory interface 2 address line 1 O 99 G1 17
EMIF2_A2 External memory interface 2 address line 2 O 100 H1
EMIF2_A3 External memory interface 2 address line 3 O 101 H2
EMIF2_A4 External memory interface 2 address line 4 O 102 H3
EMIF2_A5 External memory interface 2 address line 5 O 103 J1
EMIF2_A6 External memory interface 2 address line 6 O 104 J2
EMIF2_A7 External memory interface 2 address line 7 O 105 J3
EMIF2_A8 External memory interface 2 address line 8 O 106 L2
EMIF2_A9 External memory interface 2 address line 9 O 107 L3
EMIF2_A10 External memory interface 2 address line 10 O 108 L4
EMIF2_A11 External memory interface 2 address line 11 O 109 N2
EMIF2_A12 External memory interface 2 address line 12 O 95 B3
EMIF2_BA0 External memory interface 2 bank address 0 O 111 M4
EMIF2_BA1 External memory interface 2 bank address 1 O 112 M3
EMIF2_CS0n External memory interface 2 chip select 0 O 115 V12
EMIF2_CS2n External memory interface 2 chip select 2 O 116 W10
EMIF2_D0 External memory interface 2 data line 0 I/O 138, 68 C18, T19 133
EMIF2_D1 External memory interface 2 data line 1 I/O 137, 67 B19, T18 132
EMIF2_D2 External memory interface 2 data line 2 I/O 136, 66 K17, T17 112
EMIF2_D3 External memory interface 2 data line 3 I/O 135, 65 K16, U18 111
EMIF2_D4 External memory interface 2 data line 4 I/O 134, 64 L17, V18 110
EMIF2_D5 External memory interface 2 data line 5 I/O 132, 63 J16, W18 109
EMIF2_D6 External memory interface 2 data line 6 I/O 131, 62 J17, V10 108
EMIF2_D7 External memory interface 2 data line 7 I/O 130, 61 L16, U10 107
EMIF2_D8 External memory interface 2 data line 8 I/O 129, 60 M17, T10 105
EMIF2_D9 External memory interface 2 data line 9 I/O 128, 59 M16, W9 104
EMIF2_D10 External memory interface 2 data line 10 I/O 127, 58 N17, V9 103
EMIF2_D11 External memory interface 2 data line 11 I/O 126, 57 N18, U9 102
EMIF2_D12 External memory interface 2 data line 12 I/O 125, 56 N16, T9 101
EMIF2_D13 External memory interface 2 data line 13 I/O 124, 55 P19, V8 100
EMIF2_D14 External memory interface 2 data line 14 I/O 123, 54 P18, U8 98
EMIF2_D15 External memory interface 2 data line 15 I/O 122, 53 P17, T8 97
EMIF2_DQM0 External memory interface 2 Input/output mask for byte 0 O 97 A2
EMIF2_DQM1 External memory interface 2 Input/output mask for byte 1 O 96 C3
ENET_MDIO_CLK EMAC management data clock, Output in MII/RMII modes, Input in RevMII mode I/O 105, 42 D19, J3 130
ENET_MDIO_DATA EMAC management data I/O 106, 43 C19, L2 131
ENET_MII_COL EMAC MII collision detect I 110, 35, 39, 41 M2, T14, U17, W17 71, 86, 89
ENET_MII_CRS EMAC MII carrier sense I 109, 34, 38, 40 N2, T16, U14, V17 70, 85, 87
ENET_MII_INTR EMAC PHY interrupt, Input in MII/RMII mode, Output in RevMII mode I/O 108, 68 C18, L4 133
ENET_MII_RX_CLK EMAC MII receive clock I 111, 49, 67, 69 B18, B19, M4, R17 132, 134, 93
ENET_MII_RX_DATA0 EMAC MII / RMII receive data 0 I 114, 52, 63, 66, 71 B17, J16, K17, N3, P16 109, 112, 136, 96
ENET_MII_RX_DATA1 EMAC MII / RMII receive data 1 I 115, 53, 64, 72 B16, L17, P17, V12 110, 139, 97
ENET_MII_RX_DATA2 EMAC MII receive data 2 I 116, 54, 65 K16, P18, W10 111, 98
ENET_MII_RX_DATA3 EMAC MII receive data 3 I 117, 55, 66 K17, P19, U12 100, 112
ENET_MII_RX_DV EMAC MII receive data valid (or) RMII carrier sense/ receive data valid I 112, 38, 50, 64, 70 A17, L17, M3, R18, T16 110, 135, 85, 94
ENET_MII_RX_ERR EMAC MII / RMII receive error I 113, 39, 51, 65, 71, 76 B17, C16, K16, N4, R19, W17 111, 136, 143, 86, 95
ENET_MII_TX_CLK EMAC MII transmit clock I 120, 44, 58 K18, N17, U15 103, 113
ENET_MII_TX_DATA0 EMAC MII / RMII transmit data 0 O 121, 59, 75 D16, M16, W16 104, 142
ENET_MII_TX_DATA1 EMAC MII / RMII transmit data 1 O 122, 60, 74 C17, M17, T8 105, 141
ENET_MII_TX_DATA2 EMAC MII transmit data 2 O 123, 61, 73 A16, L16, U8 107, 140
ENET_MII_TX_DATA3 EMAC MII transmit data 3 O 124, 62, 72 B16, J17, V8 108, 139
ENET_MII_TX_EN EMAC MII / RMII transmit enable O 118, 45, 56, 69 B18, K19, N16, T12 101, 115, 134
ENET_MII_TX_ERR EMAC MII transmit error O 119, 46, 57 E19, N18, T15 102, 128
ENET_PPS0 EMAC Pulse Per Second Output 0 O 47 E18 129
ENET_PPS1 EMAC Pulse Per Second Output 1 O 48 R16 90
ENET_REVMII_MDIO_RST EMAC REVMII MDIO reset I 107, 41, 67 B19, L3, U17 132, 89
ENET_RMII_CLK EMAC RMII clock I/O 73 A16 140
EPWM10A ePWM-10 Output A (High-res available on ePWM1-8) O 163, 18 A8, E3 10
EPWM10B ePWM-10 Output B (High-res available on ePWM1-8) O 164, 19 B8, E4 12
EPWM11A ePWM-11 Output A (High-res available on ePWM1-8) O 165, 20 C5, F2 13
EPWM11B ePWM-11 Output B (High-res available on ePWM1-8) O 166, 21 D5, F3 14
EPWM12A ePWM-12 Output A (High-res available on ePWM1-8) O 167, 22 C4, J4 22
EPWM12B ePWM-12 Output B (High-res available on ePWM1-8) O 168, 23 D4, K4 23
EPWM13A ePWM-13 Output A (High-res available on ePWM1-8) O 137, 24 K3, T18 24
EPWM13B ePWM-13 Output B (High-res available on ePWM1-8) O 138, 25 K2, T19 25
EPWM14A ePWM-14 Output A (High-res available on ePWM1-8) O 139, 26 K1, N19 27
EPWM14B ePWM-14 Output B (High-res available on ePWM1-8) O 140, 27 L1, M19 28
EPWM15A ePWM-15 Output A (High-res available on ePWM1-8) O 141, 28 M18, V11 64
EPWM15B ePWM-15 Output B (High-res available on ePWM1-8) O 142, 29 L19, W11 65
EPWM16A ePWM-16 Output A (High-res available on ePWM1-8) O 143, 30 F18, T11 63
EPWM16B ePWM-16 Output B (High-res available on ePWM1-8) O 144, 31 F17, U11 66
EPWM1A ePWM-1 Output A (High-res available on ePWM1-8) O 145 C8, E17 160
EPWM1B ePWM-1 Output B (High-res available on ePWM1-8) O 1, 146 D18, D8 161
EPWM2A ePWM-2 Output A (High-res available on ePWM1-8) O 147, 2 A7, D17 162
EPWM2B ePWM-2 Output B (High-res available on ePWM1-8) O 148, 3 B7, D14 163
EPWM3A ePWM-3 Output A (High-res available on ePWM1-8) O 149, 4 A13, C7 164
EPWM3B ePWM-3 Output B (High-res available on ePWM1-8) O 150, 5 B13, D7 165
EPWM4A ePWM-4 Output A (High-res available on ePWM1-8) O 151, 6 A6, C13 166
EPWM4B ePWM-4 Output B (High-res available on ePWM1-8) O 152, 7 B6, D13 167
EPWM5A ePWM-5 Output A (High-res available on ePWM1-8) O 153, 8 A12, G2 18
EPWM5B ePWM-5 Output B (High-res available on ePWM1-8) O 154, 9 B12, G3 19
EPWM6A ePWM-6 Output A (High-res available on ePWM1-8) O 10, 155 B2, C12 1
EPWM6B ePWM-6 Output B (High-res available on ePWM1-8) O 11, 156 C1, D12 2
EPWM7A ePWM-7 Output A (High-res available on ePWM1-8) O 12, 157 B10, C2 4
EPWM7B ePWM-7 Output B (High-res available on ePWM1-8) O 13, 158 C10, D1 5
EPWM8A ePWM-8 Output A (High-res available on ePWM1-8) O 14, 159 D10, D2 6
EPWM8B ePWM-8 Output B (High-res available on ePWM1-8) O 15, 160 B9, D3 7
EPWM9A ePWM-9 Output A (High-res available on ePWM1-8) O 16, 161 C9, E1 8
EPWM9B ePWM-9 Output B (High-res available on ePWM1-8) O 162, 17 D9, E2 9
EQEP1_A eQEP-1 Input A I 10, 20, 50, 96 B2, C3, F2, R18 1, 13, 94
EQEP1_B eQEP-1 Input B I 11, 21, 51, 97 A2, C1, F3, R19 14, 2, 95
EQEP1_INDEX eQEP-1 Index I/O 13, 23, 53, 99 D1, G1, K4, P17 17, 23, 5, 97
EQEP1_STROBE eQEP-1 Strobe I/O 12, 22, 52, 98 C2, F1, J4, P16 22, 4, 96
EQEP2_A eQEP-2 Input A I 100, 24, 54, 78 B15, H1, K3, P18 145, 24, 98
EQEP2_B eQEP-2 Input B I 101, 25, 55, 79 C15, H2, K2, P19 100, 146, 25
EQEP2_INDEX eQEP-2 Index I/O 103, 26, 57, 81 A14, J1, K1, N18 102, 149, 27
EQEP2_STROBE eQEP-2 Strobe I/O 102, 27, 56, 80 D15, H3, L1, N16 101, 148, 28
EQEP3_A eQEP-3 Input A I 104, 28, 6, 62 A6, J17, J2, V11 108, 166, 64
EQEP3_B eQEP-3 Input B I 105, 29, 63, 7 B6, J16, J3, W11 109, 167, 65
EQEP3_INDEX eQEP-3 Index I/O 107, 31, 65, 9 G3, K16, L3, U11 111, 19, 66
EQEP3_STROBE eQEP-3 Strobe I/O 106, 30, 64, 8 G2, L17, L2, T11 110, 18, 63
ESC_GPI0 EtherCAT General-Purpose Input 0 I 100 C8, H1 160
ESC_GPI1 EtherCAT General-Purpose Input 1 I 1, 101 D8, H2 161
ESC_GPI2 EtherCAT General-Purpose Input 2 I 102, 2 A7, H3 162
ESC_GPI3 EtherCAT General-Purpose Input 3 I 103, 3 B7, J1 163
ESC_GPI4 EtherCAT General-Purpose Input 4 I 104, 4 C7, J2 164
ESC_GPI5 EtherCAT General-Purpose Input 5 I 105, 5 D7, J3 165
ESC_GPI6 EtherCAT General-Purpose Input 6 I 106, 6 A6, L2 166
ESC_GPI7 EtherCAT General-Purpose Input 7 I 107, 7 B6, L3 167
ESC_GPI8 EtherCAT General-Purpose Input 8 I 108 L4
ESC_GPI9 EtherCAT General-Purpose Input 9 I 109 N2
ESC_GPI10 EtherCAT General-Purpose Input 10 I 110 M2
ESC_GPI11 EtherCAT General-Purpose Input 11 I 111 M4
ESC_GPI12 EtherCAT General-Purpose Input 12 I 112 M3
ESC_GPI13 EtherCAT General-Purpose Input 13 I 113 N4
ESC_GPI14 EtherCAT General-Purpose Input 14 I 114 N3
ESC_GPI15 EtherCAT General-Purpose Input 15 I 115 V12
ESC_GPI16 EtherCAT General-Purpose Input 16 I 116 W10
ESC_GPI17 EtherCAT General-Purpose Input 17 I 117 U12
ESC_GPI18 EtherCAT General-Purpose Input 18 I 118 T12
ESC_GPI19 EtherCAT General-Purpose Input 19 I 119 T15
ESC_GPI20 EtherCAT General-Purpose Input 20 I 120 U15
ESC_GPI21 EtherCAT General-Purpose Input 21 I 121 W16
ESC_GPI22 EtherCAT General-Purpose Input 22 I 122 T8
ESC_GPI23 EtherCAT General-Purpose Input 23 I 123 U8
ESC_GPI24 EtherCAT General-Purpose Input 24 I 124 V8
ESC_GPI25 EtherCAT General-Purpose Input 25 I 125 T9
ESC_GPI26 EtherCAT General-Purpose Input 26 I 126 U9
ESC_GPI27 EtherCAT General-Purpose Input 27 I 127 V9
ESC_GPI28 EtherCAT General-Purpose Input 28 I 128 W9
ESC_GPI29 EtherCAT General-Purpose Input 29 I 129 T10
ESC_GPI30 EtherCAT General-Purpose Input 30 I 130 U10
ESC_GPI31 EtherCAT General-Purpose Input 31 I 131 V10
ESC_GPO0 EtherCAT General-Purpose Output 0 O 132, 8 G2, W18 18
ESC_GPO1 EtherCAT General-Purpose Output 1 O 134, 9 G3, V18 19
ESC_GPO2 EtherCAT General-Purpose Output 2 O 10, 135 B2, U18 1
ESC_GPO3 EtherCAT General-Purpose Output 3 O 11, 136 C1, T17 2
ESC_GPO4 EtherCAT General-Purpose Output 4 O 12, 137 C2, T18 4
ESC_GPO5 EtherCAT General-Purpose Output 5 O 13, 138 D1, T19 5
ESC_GPO6 EtherCAT General-Purpose Output 6 O 139, 14 D2, N19 6
ESC_GPO7 EtherCAT General-Purpose Output 7 O 140, 15 D3, M19 7
ESC_GPO8 EtherCAT General-Purpose Output 8 O 141 M18
ESC_GPO9 EtherCAT General-Purpose Output 9 O 142 L19
ESC_GPO10 EtherCAT General-Purpose Output 10 O 143 F18
ESC_GPO11 EtherCAT General-Purpose Output 11 O 144 F17
ESC_GPO12 EtherCAT General-Purpose Output 12 O 145 E17
ESC_GPO13 EtherCAT General-Purpose Output 13 O 146 D18
ESC_GPO14 EtherCAT General-Purpose Output 14 O 147 D17
ESC_GPO15 EtherCAT General-Purpose Output 15 O 148 D14
ESC_GPO16 EtherCAT General-Purpose Output 16 O 149 A13
ESC_GPO17 EtherCAT General-Purpose Output 17 O 150 B13
ESC_GPO18 EtherCAT General-Purpose Output 18 O 151 C13
ESC_GPO19 EtherCAT General-Purpose Output 19 O 152 D13
ESC_GPO20 EtherCAT General-Purpose Output 20 O 153 A12
ESC_GPO21 EtherCAT General-Purpose Output 21 O 154 B12
ESC_GPO22 EtherCAT General-Purpose Output 22 O 155 C12
ESC_GPO23 EtherCAT General-Purpose Output 23 O 156 D12
ESC_GPO24 EtherCAT General-Purpose Output 24 O 157 B10
ESC_GPO25 EtherCAT General-Purpose Output 25 O 158 C10
ESC_GPO26 EtherCAT General-Purpose Output 26 O 159 D10
ESC_GPO27 EtherCAT General-Purpose Output 27 O 160 B9
ESC_GPO28 EtherCAT General-Purpose Output 28 O 161 C9
ESC_GPO29 EtherCAT General-Purpose Output 29 O 162 D9
ESC_GPO30 EtherCAT General-Purpose Output 30 O 163 A8
ESC_GPO31 EtherCAT General-Purpose Output 31 O 164 B8
ESC_I2C_SCL EtherCAT I2C Clock I/OC 151, 30, 41 C13, T11, U17 63, 89
ESC_I2C_SDA EtherCAT I2C Data I/OC 150, 29, 40 B13, V17, W11 65, 87
ESC_LATCH0 EtherCAT LatchSignal Input 0 I 125, 29, 34 T9, U14, W11 65, 70
ESC_LATCH1 EtherCAT LatchSignal Input 1 I 126, 30, 35 T11, T14, U9 63, 71
ESC_LED_ERR EtherCAT Error LED O 145, 60 E17, M17 105
ESC_LED_LINK0_ACTIVE EtherCAT Link-0 Active O 143, 58 F18, N17 103
ESC_LED_LINK1_ACTIVE EtherCAT Link-1 Active O 144, 59 F17, M16 104
ESC_LED_RUN EtherCAT Run LED O 146, 61 D18, L16 107
ESC_LED_STATE_RUN EtherCAT State Run O 147, 62 D17, J17 108
ESC_MDIO_CLK EtherCAT MDIO Clock O 152, 26, 46 D13, E19, K1 128, 27
ESC_MDIO_DATA EtherCAT MDIO Data I/O 153, 27, 47 A12, E18, L1 129, 28
ESC_PHY0_LINKSTATUS EtherCAT PHY-0 Link Status I 148, 86 C11, D14 156
ESC_PHY1_LINKSTATUS EtherCAT PHY-1 Link Status I 149, 68 A13, C18 133
ESC_PHY_CLK EtherCAT PHY Clock O 154, 48 B12, R16 90
ESC_PHY_RESETn EtherCAT PHY Active Low Reset O 155, 76 C12, C16 143
ESC_RX0_CLK EtherCAT MII Receive-0 Clock I 163, 77 A15, A8 144
ESC_RX0_DV EtherCAT MII Receive-0 Data Valid I 162, 78 B15, D9 145
ESC_RX0_ERR EtherCAT MII Receive-0 Error I 164, 79 B8, C15 146
ESC_RX1_CLK EtherCAT MII Receive-1 Clock I 137, 69 B18, T18 134
ESC_RX1_DV EtherCAT MII Receive-1 Data Valid I 136, 70 A17, T17 135
ESC_RX1_ERR EtherCAT MII Receive-1 Error I 138, 71 B17, T19 136
ESC_RX0_DATA0 EtherCAT MII Receive-0 Data-0 I 165, 80 C5, D15 148
ESC_RX0_DATA1 EtherCAT MII Receive-0 Data-1 I 166, 81 A14, D5 149
ESC_RX0_DATA2 EtherCAT MII Receive-0 Data-2 I 167, 82 B14, C4 150
ESC_RX0_DATA3 EtherCAT MII Receive-0 Data-3 I 168, 83 C14, D4 151
ESC_RX1_DATA0 EtherCAT MII Receive-1 Data-0 I 139, 63 J16, N19 109
ESC_RX1_DATA1 EtherCAT MII Receive-1 Data-1 I 140, 64 L17, M19 110
ESC_RX1_DATA2 EtherCAT MII Receive-1 Data-2 I 141, 65 K16, M18 111
ESC_RX1_DATA3 EtherCAT MII Receive-1 Data-3 I 142, 66 K17, L19 112
ESC_SYNC0 EtherCAT SyncSignal Output 0 O 127, 29, 34 U14, V9, W11 65, 70
ESC_SYNC1 EtherCAT SyncSignal Output 1 O 128, 30, 35 T11, T14, W9 63, 71
ESC_TX0_CLK EtherCAT MII Transmit-0 Clock I 157, 85 B10, B11 155
ESC_TX0_ENA EtherCAT MII Transmit-0 Enable O 156, 84 A11, D12 154
ESC_TX1_CLK EtherCAT MII Transmit-1 Clock I 130, 44 K18, U10 113
ESC_TX1_ENA EtherCAT MII Transmit-1 Enable O 129, 45 K19, T10 115
ESC_TX0_DATA0 EtherCAT MII Transmit-0 Data-0 O 158, 87 C10, D11 157
ESC_TX0_DATA1 EtherCAT MII Transmit-0 Data-1 O 159, 88 C6, D10 170
ESC_TX0_DATA2 EtherCAT MII Transmit-0 Data-2 O 160, 89 B9, D6 171
ESC_TX0_DATA3 EtherCAT MII Transmit-0 Data-3 O 161, 90 A5, C9 172
ESC_TX1_DATA0 EtherCAT MII Transmit-1 Data-0 O 131, 75 D16, V10 142
ESC_TX1_DATA1 EtherCAT MII Transmit-1 Data-1 O 132, 74 C17, W18 141
ESC_TX1_DATA2 EtherCAT MII Transmit-1 Data-2 O 134, 73 A16, V18 140
ESC_TX1_DATA3 EtherCAT MII Transmit-1 Data-3 O 135, 72 B16, U18 139
EXTSYNCOUT External ePWM Synchronization Pulse O 6 A6 166
FSIRXA_CLK FSIRX-A Input Clock I 105, 13, 5, 54, 9 D1, D7, G3, J3, P18 165, 19, 5, 98
FSIRXA_D0 FSIRX-A Data Input 0 I 103, 12, 3, 52, 8 B7, C2, G2, J1, P16 163, 18, 4, 96
FSIRXA_D1 FSIRX-A Data Input 1 I 10, 104, 11, 4, 53 B2, C1, C7, J2, P17 1, 164, 2, 97
FSIRXB_CLK FSIRX-B Input Clock I 11, 112, 60 C1, M17, M3 105, 2
FSIRXB_D0 FSIRX-B Data Input 0 I 110, 58, 9 G3, M2, N17 103, 19
FSIRXB_D1 FSIRX-B Data Input 1 I 10, 111, 59 B2, M16, M4 1, 104
FSIRXC_CLK FSIRX-C Input Clock I 117, 14 D2, U12 6
FSIRXC_D0 FSIRX-C Data Input 0 I 115, 12 C2, V12 4
FSIRXC_D1 FSIRX-C Data Input 1 I 116, 13 D1, W10 5
FSIRXD_CLK FSIRX-D Input Clock I 120, 17 E2, U15 9
FSIRXD_D0 FSIRX-D Data Input 0 I 118, 15 D3, T12 7
FSIRXD_D1 FSIRX-D Data Input 1 I 119, 16 E1, T15 8
FSIRXE_CLK FSIRX-E Input Clock I 126, 20 F2, U9 13
FSIRXE_D0 FSIRX-E Data Input 0 I 121, 18 E3, W16 10
FSIRXE_D1 FSIRX-E Data Input 1 I 125, 19 E4, T9 12
FSIRXF_CLK FSIRX-F Input Clock I 23, 93 B4, K4 175, 23
FSIRXF_D0 FSIRX-F Data Input 0 I 21, 91 B5, F3 14, 173
FSIRXF_D1 FSIRX-F Data Input 1 I 22, 92 A4, J4 174, 22
FSIRXG_CLK FSIRX-G Input Clock I 26, 96 C3, K1 27
FSIRXG_D0 FSIRX-G Data Input 0 I 24, 94 A3, K3 176, 24
FSIRXG_D1 FSIRX-G Data Input 1 I 25, 95 B3, K2 25
FSIRXH_CLK FSIRX-H Input Clock I 29, 99 G1, W11 17, 65
FSIRXH_D0 FSIRX-H Data Input 0 I 27, 97 A2, L1 28
FSIRXH_D1 FSIRX-H Data Input 1 I 28, 98 F1, V11 64
FSITXA_CLK FSITX-A Output Clock O 10, 102, 2, 27, 51 A7, B2, H3, L1, R19 1, 162, 28, 95
FSITXA_D0 FSITX-A Data Output 0 O 100, 26, 49, 9 C8, G3, H1, K1, R17 160, 19, 27, 93
FSITXA_D1 FSITX-A Data Output 1 O 1, 101, 25, 50, 8 D8, G2, H2, K2, R18 161, 18, 25, 94
FSITXB_CLK FSITX-B Output Clock O 108, 56, 8 G2, L4, N16 101, 18
FSITXB_D0 FSITX-B Data Output 0 O 106, 55, 6 A6, L2, P19 100, 166
FSITXB_D1 FSITX-B Data Output 1 O 107, 57, 7 B6, L3, N18 102, 167
GPIO0 General-Purpose Input Output 0 I/O C8 160
GPIO1 General-Purpose Input Output 1 I/O 1 D8 161
GPIO2 General-Purpose Input Output 2 I/O 2 A7 162
GPIO3 General-Purpose Input Output 3 I/O 3 B7 163
GPIO4 General-Purpose Input Output 4 I/O 4 C7 164
GPIO5 General-Purpose Input Output 5 I/O 5 D7 165
GPIO6 General-Purpose Input Output 6 I/O 6 A6 166
GPIO7 General-Purpose Input Output 7 I/O 7 B6 167
GPIO8 General-Purpose Input Output 8 I/O 8 G2 18
GPIO9 General-Purpose Input Output 9 I/O 9 G3 19
GPIO10 General-Purpose Input Output 10 I/O 10 B2 1
GPIO11 General-Purpose Input Output 11 I/O 11 C1 2
GPIO12 General-Purpose Input Output 12 I/O 12 C2 4
GPIO13 General-Purpose Input Output 13 I/O 13 D1 5
GPIO14 General-Purpose Input Output 14 I/O 14 D2 6
GPIO15 General-Purpose Input Output 15 I/O 15 D3 7
GPIO16 General-Purpose Input Output 16 I/O 16 E1 8
GPIO17 General-Purpose Input Output 17 I/O 17 E2 9
GPIO18 General-Purpose Input Output 18 I/O 18 E3 10
GPIO19 General-Purpose Input Output 19 I/O 19 E4 12
GPIO100 General-Purpose Input Output 100 I/O 100 H1
GPIO101 General-Purpose Input Output 101 I/O 101 H2
GPIO102 General-Purpose Input Output 102 I/O 102 H3
GPIO103 General-Purpose Input Output 103 I/O 103 J1
GPIO104 General-Purpose Input Output 104 I/O 104 J2
GPIO105 General-Purpose Input Output 105 I/O 105 J3
GPIO106 General-Purpose Input Output 106 I/O 106 L2
GPIO107 General-Purpose Input Output 107 I/O 107 L3
GPIO108 General-Purpose Input Output 108 I/O 108 L4
GPIO109 General-Purpose Input Output 109 I/O 109 N2
GPIO110 General-Purpose Input Output 110 I/O 110 M2
GPIO111 General-Purpose Input Output 111 I/O 111 M4
GPIO112 General-Purpose Input Output 112 I/O 112 M3
GPIO113 General-Purpose Input Output 113 I/O 113 N4
GPIO114 General-Purpose Input Output 114 I/O 114 N3
GPIO115 General-Purpose Input Output 115 I/O 115 V12
GPIO116 General-Purpose Input Output 116 I/O 116 W10
GPIO117 General-Purpose Input Output 117 I/O 117 U12
GPIO118 General-Purpose Input Output 118 I/O 118 T12
GPIO119 General-Purpose Input Output 119 I/O 119 T15
GPIO120 General-Purpose Input Output 120 I/O 120 U15
GPIO121 General-Purpose Input Output 121 I/O 121 W16
GPIO122 General-Purpose Input Output 122 I/O 122 T8
GPIO123 General-Purpose Input Output 123 I/O 123 U8
GPIO124 General-Purpose Input Output 124 I/O 124 V8
GPIO125 General-Purpose Input Output 125 I/O 125 T9
GPIO126 General-Purpose Input Output 126 I/O 126 U9
GPIO127 General-Purpose Input Output 127 I/O 127 V9
GPIO128 General-Purpose Input Output 128 I/O 128 W9
GPIO129 General-Purpose Input Output 129 I/O 129 T10
GPIO130 General-Purpose Input Output 130 I/O 130 U10
GPIO131 General-Purpose Input Output 131 I/O 131 V10
GPIO132 General-Purpose Input Output 132 I/O 132 W18
GPIO133 General-Purpose Input Output 133 I/O 133 G18 118
GPIO134 General-Purpose Input Output 134 I/O 134 V18
GPIO135 General-Purpose Input Output 135 I/O 135 U18
GPIO136 General-Purpose Input Output 136 I/O 136 T17
GPIO137 General-Purpose Input Output 137 I/O 137 T18
GPIO138 General-Purpose Input Output 138 I/O 138 T19
GPIO139 General-Purpose Input Output 139 I/O 139 N19
GPIO140 General-Purpose Input Output 140 I/O 140 M19
GPIO141 General-Purpose Input Output 141 I/O 141 M18
GPIO142 General-Purpose Input Output 142 I/O 142 L19
GPIO143 General-Purpose Input Output 143 I/O 143 F18
GPIO144 General-Purpose Input Output 144 I/O 144 F17
GPIO145 General-Purpose Input Output 145 I/O 145 E17
GPIO146 General-Purpose Input Output 146 I/O 146 D18
GPIO147 General-Purpose Input Output 147 I/O 147 D17
GPIO148 General-Purpose Input Output 148 I/O 148 D14
GPIO149 General-Purpose Input Output 149 I/O 149 A13
GPIO150 General-Purpose Input Output 150 I/O 150 B13
GPIO151 General-Purpose Input Output 151 I/O 151 C13
GPIO152 General-Purpose Input Output 152 I/O 152 D13
GPIO153 General-Purpose Input Output 153 I/O 153 A12
GPIO154 General-Purpose Input Output 154 I/O 154 B12
GPIO155 General-Purpose Input Output 155 I/O 155 C12
GPIO156 General-Purpose Input Output 156 I/O 156 D12
GPIO157 General-Purpose Input Output 157 I/O 157 B10
GPIO158 General-Purpose Input Output 158 I/O 158 C10
GPIO159 General-Purpose Input Output 159 I/O 159 D10
GPIO160 General-Purpose Input Output 160 I/O 160 B9
GPIO161 General-Purpose Input Output 161 I/O 161 C9
GPIO162 General-Purpose Input Output 162 I/O 162 D9
GPIO163 General-Purpose Input Output 163 I/O 163 A8
GPIO164 General-Purpose Input Output 164 I/O 164 B8
GPIO165 General-Purpose Input Output 165 I/O 165 C5
GPIO166 General-Purpose Input Output 166 I/O 166 D5
GPIO167 General-Purpose Input Output 167 I/O 167 C4
GPIO168 General-Purpose Input Output 168 I/O 168 D4
GPIO20 General-Purpose Input Output 20 I/O 20 F2 13
GPIO21 General-Purpose Input Output 21 I/O 21 F3 14
GPIO22 General-Purpose Input Output 22 I/O 22 J4 22
GPIO23 General-Purpose Input Output 23 I/O 23 K4 23
GPIO24 General-Purpose Input Output 24 I/O 24 K3 24
GPIO25 General-Purpose Input Output 25 I/O 25 K2 25
GPIO26 General-Purpose Input Output 26 I/O 26 K1 27
GPIO27 General-Purpose Input Output 27 I/O 27 L1 28
GPIO28 General-Purpose Input Output 28 I/O 28 V11 64
GPIO29 General-Purpose Input Output 29 I/O 29 W11 65
GPIO30 General-Purpose Input Output 30 I/O 30 T11 63
GPIO31 General-Purpose Input Output 31 I/O 31 U11 66
GPIO32 General-Purpose Input Output 32 I/O 32 U13 67
GPIO33 General-Purpose Input Output 33 I/O 33 T13 69
GPIO34 General-Purpose Input Output 34 I/O 34 U14 70
GPIO35 General-Purpose Input Output 35 I/O 35 T14 71
GPIO36 General-Purpose Input Output 36 I/O 36 V16 83
GPIO37 General-Purpose Input Output 37 I/O 37 U16 84
GPIO38 General-Purpose Input Output 38 I/O 38 T16 85
GPIO39 General-Purpose Input Output 39 I/O 39 W17 86
GPIO40 General-Purpose Input Output 40 I/O 40 V17 87
GPIO41 General-Purpose Input Output 41 I/O 41 U17 89
GPIO42 General-Purpose Input Output 42 I/O 42 D19 130
GPIO43 General-Purpose Input Output 43 I/O 43 C19 131
GPIO44 General-Purpose Input Output 44 I/O 44 K18 113
GPIO45 General-Purpose Input Output 45 I/O 45 K19 115
GPIO46 General-Purpose Input Output 46 I/O 46 E19 128
GPIO47 General-Purpose Input Output 47 I/O 47 E18 129
GPIO48 General-Purpose Input Output 48 I/O 48 R16 90
GPIO49 General-Purpose Input Output 49 I/O 49 R17 93
GPIO50 General-Purpose Input Output 50 I/O 50 R18 94
GPIO51 General-Purpose Input Output 51 I/O 51 R19 95
GPIO52 General-Purpose Input Output 52 I/O 52 P16 96
GPIO53 General-Purpose Input Output 53 I/O 53 P17 97
GPIO54 General-Purpose Input Output 54 I/O 54 P18 98
GPIO55 General-Purpose Input Output 55 I/O 55 P19 100
GPIO56 General-Purpose Input Output 56 I/O 56 N16 101
GPIO57 General-Purpose Input Output 57 I/O 57 N18 102
GPIO58 General-Purpose Input Output 58 I/O 58 N17 103
GPIO59 General-Purpose Input Output 59 I/O 59 M16 104
GPIO60 General-Purpose Input Output 60 I/O 60 M17 105
GPIO61 General-Purpose Input Output 61 I/O 61 L16 107
GPIO62 General-Purpose Input Output 62 I/O 62 J17 108
GPIO63 General-Purpose Input Output 63 I/O 63 J16 109
GPIO64 General-Purpose Input Output 64 I/O 64 L17 110
GPIO65 General-Purpose Input Output 65 I/O 65 K16 111
GPIO66 General-Purpose Input Output 66 I/O 66 K17 112
GPIO67 General-Purpose Input Output 67 I/O 67 B19 132
GPIO68 General-Purpose Input Output 68 I/O 68 C18 133
GPIO69 General-Purpose Input Output 69 I/O 69 B18 134
GPIO70 General-Purpose Input Output 70 I/O 70 A17 135
GPIO71 General-Purpose Input Output 71 I/O 71 B17 136
GPIO72 General-Purpose Input Output 72 I/O 72 B16 139
GPIO73 General-Purpose Input Output 73 I/O 73 A16 140
GPIO74 General-Purpose Input Output 74 I/O 74 C17 141
GPIO75 General-Purpose Input Output 75 I/O 75 D16 142
GPIO76 General-Purpose Input Output 76 I/O 76 C16 143
GPIO77 General-Purpose Input Output 77 I/O 77 A15 144
GPIO78 General-Purpose Input Output 78 I/O 78 B15 145
GPIO79 General-Purpose Input Output 79 I/O 79 C15 146
GPIO80 General-Purpose Input Output 80 I/O 80 D15 148
GPIO81 General-Purpose Input Output 81 I/O 81 A14 149
GPIO82 General-Purpose Input Output 82 I/O 82 B14 150
GPIO83 General-Purpose Input Output 83 I/O 83 C14 151
GPIO84 General-Purpose Input Output 84 I/O 84 A11 154
GPIO85 General-Purpose Input Output 85 I/O 85 B11 155
GPIO86 General-Purpose Input Output 86 I/O 86 C11 156
GPIO87 General-Purpose Input Output 87 I/O 87 D11 157
GPIO88 General-Purpose Input Output 88 I/O 88 C6 170
GPIO89 General-Purpose Input Output 89 I/O 89 D6 171
GPIO90 General-Purpose Input Output 90 I/O 90 A5 172
GPIO91 General-Purpose Input Output 91 I/O 91 B5 173
GPIO92 General-Purpose Input Output 92 I/O 92 A4 174
GPIO93 General-Purpose Input Output 93 I/O 93 B4 175
GPIO94 General-Purpose Input Output 94 I/O 94 A3 176
GPIO95 General-Purpose Input Output 95 I/O 95 B3
GPIO96 General-Purpose Input Output 96 I/O 96 C3
GPIO97 General-Purpose Input Output 97 I/O 97 A2
GPIO98 General-Purpose Input Output 98 I/O 98 F1
GPIO99 General-Purpose Input Output 99 I/O 99 G1 17
I2CA_SCL I2C-A Open-Drain Bidirectional Clock I/OD 1, 105, 32, 33, 43, 57, 92 A4, C19, D8, J3, N18, T13, U13 102, 131, 161, 174, 67, 69
I2CA_SDA I2C-A Open-Drain Bidirectional Data I/OD 104, 31, 32, 42, 56, 91 B5, C8, D19, J2, N16, U11, U13 101, 130, 160, 173, 66, 67
I2CB_SCL I2C-B Open-Drain Bidirectional Clock I/OD 3, 35, 41, 69 B18, B7, T14, U17 134, 163, 71, 89
I2CB_SDA I2C-B Open-Drain Bidirectional Data I/OD 2, 34, 40, 66 A7, K17, U14, V17 112, 162, 70, 87
MCAN_RX CAN/CAN FD Receive I 10, 18, 23, 30, 36, 5, 70, 75 A17, B2, D16, D7, E3, K4, T11, V16 1, 10, 135, 142, 165, 23, 63, 83
MCAN_TX CAN/CAN FD Transmit O 19, 22, 31, 37, 4, 71, 74, 8 B17, C17, C7, E4, G2, J4, U11, U16 12, 136, 141, 164, 18, 22, 66, 84
MCLKRA McBSP-A Receive Clock I 58, 7 B6, N17 103, 167
MCLKRB McBSP-B Receive Clock I 3, 60 B7, M17 105, 163
MCLKXA McBSP-A Transmit Clock O 167, 22, 86 C11, C4, J4 156, 22
MCLKXB McBSP-B Transmit Clock O 14, 26, 86 C11, D2, K1 156, 27, 6
MDRA McBSP-A Receive Serial Data I 166, 21, 85 B11, D5, F3 14, 155
MDRB McBSP-B Receive Serial Data I 13, 25, 85 B11, D1, K2 155, 25, 5
MDXA McBSP-A Transmit Serial Data O 165, 20, 84 A11, C5, F2 13, 154
MDXB McBSP-B Transmit Serial Data O 12, 24, 84 A11, C2, K3 154, 24, 4
MFSRA McBSP-A Receive Frame Sync I 5, 59 D7, M16 104, 165
MFSRB McBSP-B Receive Frame Sync I 1, 61 D8, L16 107, 161
MFSXA McBSP-A Transmit Frame Sync O 168, 23, 87 D11, D4, K4 157, 23
MFSXB McBSP-B Transmit Frame Sync O 15, 27, 87 D11, D3, L1 157, 28, 7
OUTPUTXBAR1 Output X-BAR Output 1 O 2, 24, 34, 58 A7, K3, N17, U14 103, 162, 24, 70
OUTPUTXBAR2 Output X-BAR Output 2 O 25, 3, 37, 59 B7, K2, M16, U16 104, 163, 25, 84
OUTPUTXBAR3 Output X-BAR Output 3 O 14, 26, 4, 48, 5, 60 C7, D2, D7, K1, M17, R16 105, 164, 165, 27, 6, 90
OUTPUTXBAR4 Output X-BAR Output 4 O 15, 27, 49, 6, 61 A6, D3, L1, L16, R17 107, 166, 28, 7, 93
OUTPUTXBAR5 Output X-BAR Output 5 O 115, 28, 7 B6, V11, V12 167, 64
OUTPUTXBAR6 Output X-BAR Output 6 O 116, 29, 9 G3, W10, W11 19, 65
OUTPUTXBAR7 Output X-BAR Output 7 O 11, 16, 30 C1, E1, T11 2, 63, 8
OUTPUTXBAR8 Output X-BAR Output 8 O 17, 31 E2, U11 66, 9
PMBUSA_ALERT PMBus-A Open-Drain Bidirectional Alert Signal I/OD 26, 93 B4, K1 175, 27
PMBUSA_CTL PMBus-A Control Signal I 27, 94 A3, L1 176, 28
PMBUSA_SCL PMBus-A Open-Drain Bidirectional Clock I/OD 24, 91 B5, K3 173, 24
PMBUSA_SDA PMBus-A Open-Drain Bidirectional Data I/OD 25, 92 A4, K2 174, 25
SCIA_RX SCI-A Receive Data I 136, 28, 35, 43, 49, 64, 85, 9 B11, C19, G3, L17, R17, T14, T17, V11 110, 131, 155, 19, 64, 71, 93
SCIA_TX SCI-A Transmit Data O 135, 29, 34, 36, 42, 48, 65, 8, 84 A11, D19, G2, K16, R16, U14, U18, V16, W11 111, 130, 154, 18, 65, 70, 83, 90
SCIB_RX SCI-B Receive Data I 11, 138, 15, 19, 23, 55, 71, 87 B17, C1, D11, D3, E4, K4, P19, T19 100, 12, 136, 157, 2, 23, 7
SCIB_TX SCI-B Transmit Data O 10, 137, 14, 18, 22, 54, 70, 86, 9 A17, B2, C11, D2, E3, G3, J4, P18, T18 1, 10, 135, 156, 19, 22, 6, 98
SCIC_RX SCI-C Receive Data I 107, 13, 139, 39, 57, 62, 73, 90 A16, A5, D1, J17, L3, N18, N19, W17 102, 108, 140, 172, 5, 86
SCIC_TX SCI-C Transmit Data O 106, 12, 140, 38, 56, 63, 72, 89 B16, C2, D6, J16, L2, M19, N16, T16 101, 109, 139, 171, 4, 85
SCID_RX SCI-D Receive Data I 105, 141, 46, 77, 94 A15, A3, E19, J3, M18 128, 144, 176
SCID_TX SCI-D Transmit Data O 104, 142, 47, 76, 93 B4, C16, E18, J2, L19 129, 143, 175
SD1_C1 SDFM-1 Channel 1 Clock Input I 123, 17, 49, 53, 64 E2, L17, P17, R17, U8 110, 9, 93, 97
SD1_C2 SDFM-1 Channel 2 Clock Input I 125, 19, 51, 54, 66 E4, K17, P18, R19, T9 112, 12, 95, 98
SD1_C3 SDFM-1 Channel 3 Clock Input I 127, 21, 53, 55, 68 C18, F3, P17, P19, V9 100, 133, 14, 97
SD1_C4 SDFM-1 Channel 4 Clock Input I 129, 23, 55, 56, 70 A17, K4, N16, P19, T10 100, 101, 135, 23
SD1_D1 SDFM-1 Channel 1 Data Input I 122, 16, 36, 48, 63 E1, J16, R16, T8, V16 109, 8, 83, 90
SD1_D2 SDFM-1 Channel 2 Data Input I 124, 18, 37, 50, 65 E3, K16, R18, U16, V8 10, 111, 84, 94
SD1_D3 SDFM-1 Channel 3 Data Input I 126, 20, 38, 52, 67 B19, F2, P16, T16, U9 13, 132, 85, 96
SD1_D4 SDFM-1 Channel 4 Data Input I 128, 22, 39, 54, 69 B18, J4, P18, W17, W9 134, 22, 86, 98
SD2_C1 SDFM-2 Channel 1 Clock Input I 131, 25, 57, 80 D15, K2, N18, V10 102, 148, 25
SD2_C2 SDFM-2 Channel 2 Clock Input I 133, 27, 58, 59, 74 C17, G18, L1, M16, N17 103, 104, 118, 141, 28
SD2_C3 SDFM-2 Channel 3 Clock Input I 135, 29, 59, 61, 76 C16, L16, M16, U18, W11 104, 107, 143, 65
SD2_C4 SDFM-2 Channel 4 Clock Input I 137, 31, 60, 63, 78 B15, J16, M17, T18, U11 105, 109, 145, 66
SD2_D1 SDFM-2 Channel 1 Data Input I 130, 24, 49, 56, 79 C15, K3, N16, R17, U10 101, 146, 24, 93
SD2_D2 SDFM-2 Channel 2 Data Input I 132, 26, 50, 58, 73 A16, K1, N17, R18, W18 103, 140, 27, 94
SD2_D3 SDFM-2 Channel 3 Data Input I 134, 28, 51, 60, 75 D16, M17, R19, V11, V18 105, 142, 64, 95
SD2_D4 SDFM-2 Channel 4 Data Input I 136, 30, 52, 62, 77 A15, J17, P16, T11, T17 108, 144, 63, 96
SPIA_CLK SPI-A Clock I/O 18, 34, 56, 60 E3, M17, N16, U14 10, 101, 105, 70
SPIA_SIMO SPI-A Slave In, Master Out (SIMO) I/O 16, 32, 54, 58 E1, N17, P18, U13 103, 67, 8, 98
SPIA_SOMI SPI-A Slave Out, Master In (SOMI) I/O 17, 33, 55, 59 E2, M16, P19, T13 100, 104, 69, 9
SPIA_STEn SPI-A Slave Transmit Enable (STE) I/O 19, 35, 57, 61 E4, L16, N18, T14 102, 107, 12, 71
SPIB_CLK SPI-B Clock I/O 22, 26, 58, 65 J4, K1, K16, N17 103, 111, 22, 27
SPIB_SIMO SPI-B Slave In, Master Out (SIMO) I/O 24, 60, 63 J16, K3, M17 105, 109, 24
SPIB_SOMI SPI-B Slave Out, Master In (SOMI) I/O 25, 61, 64 K2, L16, L17 107, 110, 25
SPIB_STEn SPI-B Slave Transmit Enable (STE) I/O 23, 27, 59, 66 K17, K4, L1, M16 104, 112, 23, 28
SPIC_CLK SPI-C Clock I/O 102, 124, 22, 52, 71 B17, H3, J4, P16, V8 136, 22, 96
SPIC_SIMO SPI-C Slave In, Master Out (SIMO) I/O 100, 122, 20, 50, 69 B18, F2, H1, R18, T8 13, 134, 94
SPIC_SOMI SPI-C Slave Out, Master In (SOMI) I/O 101, 123, 21, 51, 70 A17, F3, H2, R19, U8 135, 14, 95
SPIC_STEn SPI-C Slave Transmit Enable (STE) I/O 103, 125, 23, 53, 72 B16, J1, K4, P17, T9 139, 23, 97
SPID_CLK SPI-D Clock I/O 32, 93 B4, U13 175, 67
SPID_SIMO SPI-D Slave In, Master Out (SIMO) I/O 30, 91 B5, T11 173, 63
SPID_SOMI SPI-D Slave Out, Master In (SOMI) I/O 31, 92 A4, U11 174, 66
SPID_STEn SPI-D Slave Transmit Enable (STE) I/O 33, 94 A3, T13 176, 69
SSIA_CLK SSI-A Clock I/O 18, 56, 65, 93 B4, E3, K16, N16 10, 101, 111, 175
SSIA_FSS SSI-A Frame Sync I/O 19, 57, 66, 94 A3, E4, K17, N18 102, 112, 12, 176
SSIA_RX SSI-A Serial Data Receive I/O 17, 55, 64, 92 A4, E2, L17, P19 100, 110, 174, 9
SSIA_TX SSI-A Serial Data Transmit I/O 16, 54, 63, 91 B5, E1, J16, P18 109, 173, 8, 98
TRACE_CLK Trace Clock O 24 K3 24
TRACE_DATA0 Trace Data 0 O 20 F2 13
TRACE_DATA1 Trace Data 1 O 21 F3 14
TRACE_DATA2 Trace Data 2 O 22 J4 22
TRACE_DATA3 Trace Data 3 O 23 K4 23
TRACE_SWO Trace Single Wire Out O 25 K2 25
UARTA_RX UART-A Serial Data Receive I/O 43, 85 B11, C19 131, 155
UARTA_TX UART-A Serial Data Transmit I/O 42, 84 A11, D19 130, 154
USB0DM USB-0 PHY differential data O 42 D19 130
USB0DP USB-0 PHY differential data O 43 C19 131
XCLKOUT External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device. O 73 A16 140