SPRSP14E may 2019 – june 2023 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The user should analyze the ADC input setting assuming worst-case initial conditions on Ch. This will require assuming that Ch could start the S+H window completely charged to VREFHI or completely discharged to VREFLO. When the ADC transitions from an odd-numbered channel to an even-numbered channel, or vice-versa, the actual initial voltage on Ch will be close to being completely discharged to VREFLO. For even-to-even or odd-to-odd channel transitions, the initial voltage on Ch will be close to the voltage of the previously converted channel.
For differential operation, the ADC input characteristics are given by Section 7.11.2.3.8.4 and Figure 7-38.