SPRSP85 Data sheet

SPRSP85A April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

PRODMIX

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

PNA|80
PM|64
RSH|56
PZ|100
PDT|128

Thermal pad, mechanical data (Package|Pins)

6.15.4.2.6 ADC Timing Diagrams

The following diagrams show the ADC conversion timings for two SOCs given the following assumptions:

SOC0 and SOC1 are configured to use the same trigger.
No other SOCs are converting or pending when the trigger occurs.
The round-robin pointer is in a state that causes SOC0 to convert first.
ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).

Table 6-21 lists the descriptions of the ADC timing parameters. Table 6-22 and Table 6-23 list the ADC timings.

TMS320F28P550SJ TMS320F28P559SJ-Q1 ADC Timings for 12-bit Mode in
Early Interrupt Mode

Figure 6-44 ADC Timings for 12-bit Mode in Early Interrupt Mode

TMS320F28P550SJ TMS320F28P559SJ-Q1 ADC Timings for 12-bit Mode in
Late Interrupt Mode

Figure 6-45 ADC Timings for 12-bit Mode in Late Interrupt Mode

Table 6-21 ADC Timing Parameter Descriptions

PARAMETER	DESCRIPTION
t_SH	The duration of the S+H window.
	At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each SOC, so t_SH is not necessarily the same for different SOCs.
	Note: The value on the S+H capacitor is captured approximately 5 ns before the end of the S+H window regardless of device clock settings.
t_LAT	The time from the end of the S+H window until the ADC results latch in the ADCRESULTx register.
t_LAT	If the ADCRESULTx register is read before this time, the previous conversion results are returned.
t_EOC	The time from the end of the S+H window until the S+H window for the next ADC conversion can begin. The subsequent sample can start before the conversion results are latched.
t_INT	The time from the end of the S+H window until an ADCINT flag is set (if configured).
	If the INTPULSEPOS bit in the ADCCTL1 register is set, t_INT coincides with the end of conversion (EOC) signal.
	If the INTPULSEPOS bit is 0, t_INT coincides with the end of the S+H window. If t_INT triggers a read of the ADC result register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be taken to make sure the read occurs after the results latch (otherwise, the previous results are read).
	If the INTPULSEPOS bit is 0, and the OFFSET field in the ADCINTCYCLE register is not 0, then there is a delay of OFFSET SYSCLK cycles before the ADCINT flag is set. This delay can be used to enter the ISR or trigger the DMA exactly when the sample is ready.
t_DMA	The time from the end of the S+H window until a DMA read of the ADC conversion result is triggered, when ADCCTL1.TDMAEN = 1.
t_DMA	If TDMAEN is set to 0, then the DMA trigger occurs at T_INT. In certain conditions, the ADCINT flag can be set before the ADCRESULT value is latched. To make sure that the DMA read occurs after the ADCRESULT value has been latched, write 1 to ADCCTL1.TDMAEN to enable DMA timings.

Table 6-22 ADC Timings in 12-bit Mode with SAMPCAPRESETSEL = 0

ADCCLK Prescale		SYSCLK Cycles
ADCCTL2. PRESCALE	Prescale Ratio	t_EOC	t_LAT	t_INT (Early)⁽¹⁾	t_INT (Late)	t_DMA
0	1	15	20	1	15	20
2	2	30	35	1	30	35
3	2.5	38	46	1	38	46
4	3	45	50	1	45	50
5	3.5	53	58	1	53	58
6	4	60	65	1	60	65
7	4.5	68	73	1	68	73
8	5	75	80	1	75	80
9	5.5	83	88	1	83	88
10	6	90	95	1	90	95
11	6.5	98	103	1	98	103
12	7	105	110	1	105	110
13	7.5	113	118	1	113	118
14	8	120	125	1	120	125
15	8.5	128	133	1	128	133

(1) By default, t_INT occurs one SYSCLK cycle after the S+H window if INTPULSEPOS is 0. This can be changed by writing to the OFFSET field in the ADCINTCYCLE register.

Table 6-23 ADC Timings in 12-bit Mode with SAMPCAPRESETSEL = 1

ADCCLK Prescale		SYSCLK Cycles
ADCCTL2. PRESCALE	Prescale Ratio	t_EOC	t_LAT	t_INT (Early)⁽¹⁾	t_INT (Late)	t_DMA
0	1	14	19	1	14	19
2	2	28	33	1	28	33
3	2.5	35	40	1	35	40
4	3	42	47	1	42	47
5	3.5	49	54	1	49	54
6	4	56	61	1	56	61
7	4.5	63	68	1	63	68
8	5	70	75	1	70	75
9	5.5	77	82	1	77	82
10	6	84	89	1	84	89
11	6.5	91	96	1	91	96
12	7	98	103	1	98	103
13	7.5	105	110	1	105	110
14	8	112	117	1	112	117
15	8.5	119	124	1	119	124

(1) By default, t_INT occurs one SYSCLK cycle after the S+H window if INTPULSEPOS is 0. This can be changed by writing to the OFFSET field in the ADCINTCYCLE register.