SPRSP85A April   2024  – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption - VREG Enable - Internal Supply
      2. 6.5.2 System Current Consumption - VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Reducing Current Consumption
        1. 6.5.4.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Special Considerations for 5V Fail-Safe Pins
    8. 6.8  Thermal Resistance Characteristics for PDT Package
    9. 6.9  Thermal Resistance Characteristics for PZ Package
    10. 6.10 Thermal Resistance Characteristics for PNA Package
    11. 6.11 Thermal Resistance Characteristics for PM Package
    12. 6.12 Thermal Resistance Characteristics for RSH Package
    13. 6.13 Thermal Design Considerations
    14. 6.14 System
      1. 6.14.1  Power Management Module (PMM)
        1. 6.14.1.1 Introduction
        2. 6.14.1.2 Overview
          1. 6.14.1.2.1 Power Rail Monitors
            1. 6.14.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.14.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.14.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.14.1.2.2 External Supervisor Usage
          3. 6.14.1.2.3 Delay Blocks
          4. 6.14.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.14.1.2.5 VREGENZ
        3. 6.14.1.3 External Components
          1. 6.14.1.3.1 Decoupling Capacitors
            1. 6.14.1.3.1.1 VDDIO Decoupling
            2. 6.14.1.3.1.2 VDD Decoupling
        4. 6.14.1.4 Power Sequencing
          1. 6.14.1.4.1 Supply Pins Ganging
          2. 6.14.1.4.2 Signal Pins Power Sequence
          3. 6.14.1.4.3 Supply Pins Power Sequence
            1. 6.14.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.14.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.14.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.14.1.4.3.4 Supply Slew Rate
        5. 6.14.1.5 Power Management Module Electrical Data and Timing
          1. 6.14.1.5.1 Power Management Module Operating Conditions
          2. 6.14.1.5.2 Power Management Module Characteristics
      2. 6.14.2  Reset Timing
        1. 6.14.2.1 Reset Sources
        2. 6.14.2.2 Reset Electrical Data and Timing
          1. 6.14.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.14.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.14.2.2.3 Reset Timing Diagrams
      3. 6.14.3  Clock Specifications
        1. 6.14.3.1 Clock Sources
        2. 6.14.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.14.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.14.3.2.1.1 Input Clock Frequency
            2. 6.14.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.14.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.14.3.2.1.4 X1 Timing Requirements
            5. 6.14.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.14.3.2.1.6 APLL Characteristics
            7. 6.14.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.14.3.2.1.8 Internal Clock Frequencies
        3. 6.14.3.3 Input Clocks and PLLs
        4. 6.14.3.4 XTAL Oscillator
          1. 6.14.3.4.1 Introduction
          2. 6.14.3.4.2 Overview
            1. 6.14.3.4.2.1 Electrical Oscillator
              1. 6.14.3.4.2.1.1 Modes of Operation
                1. 6.14.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.14.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.14.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.14.3.4.2.2 Quartz Crystal
            3. 6.14.3.4.2.3 GPIO Modes of Operation
          3. 6.14.3.4.3 Functional Operation
            1. 6.14.3.4.3.1 ESR – Effective Series Resistance
            2. 6.14.3.4.3.2 Rneg – Negative Resistance
            3. 6.14.3.4.3.3 Start-up Time
              1. 6.14.3.4.3.3.1 X1/X2 Precondition
            4. 6.14.3.4.3.4 DL – Drive Level
          4. 6.14.3.4.4 How to Choose a Crystal
          5. 6.14.3.4.5 Testing
          6. 6.14.3.4.6 Common Problems and Debug Tips
          7. 6.14.3.4.7 Crystal Oscillator Specifications
            1. 6.14.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.14.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.14.3.4.7.3 Crystal Oscillator Parameters
        5. 6.14.3.5 Internal Oscillators
          1. 6.14.3.5.1 INTOSC Characteristics
      4. 6.14.4  Flash Parameters
        1. 6.14.4.1 Flash Parameters 
      5. 6.14.5  RAM Specifications
      6. 6.14.6  ROM Specifications
      7. 6.14.7  Emulation/JTAG
        1. 6.14.7.1 JTAG Electrical Data and Timing
          1. 6.14.7.1.1 JTAG Timing Requirements
          2. 6.14.7.1.2 JTAG Switching Characteristics
          3. 6.14.7.1.3 JTAG Timing Diagram
        2. 6.14.7.2 cJTAG Electrical Data and Timing
          1. 6.14.7.2.1 cJTAG Timing Requirements
          2. 6.14.7.2.2 cJTAG Switching Characteristics
          3. 6.14.7.2.3 cJTAG Timing Diagram
      8. 6.14.8  GPIO Electrical Data and Timing
        1. 6.14.8.1 GPIO – Output Timing
          1. 6.14.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.14.8.1.2 General-Purpose Output Timing Diagram
        2. 6.14.8.2 GPIO – Input Timing
          1. 6.14.8.2.1 General-Purpose Input Timing Requirements
          2. 6.14.8.2.2 Sampling Mode
        3. 6.14.8.3 Sampling Window Width for Input Signals
      9. 6.14.9  Interrupts
        1. 6.14.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.14.9.1.1 External Interrupt Timing Requirements
          2. 6.14.9.1.2 External Interrupt Switching Characteristics
          3. 6.14.9.1.3 External Interrupt Timing
      10. 6.14.10 Low-Power Modes
        1. 6.14.10.1 Clock-Gating Low-Power Modes
        2. 6.14.10.2 Low-Power Mode Wake-up Timing
          1. 6.14.10.2.1 IDLE Mode Timing Requirements
          2. 6.14.10.2.2 IDLE Mode Switching Characteristics
          3. 6.14.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.14.10.2.4 STANDBY Mode Timing Requirements
          5. 6.14.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.14.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.14.10.2.7 HALT Mode Timing Requirements
          8. 6.14.10.2.8 HALT Mode Switching Characteristics
          9. 6.14.10.2.9 HALT Entry and Exit Timing Diagram
    15. 6.15 Analog Peripherals
      1. 6.15.1 Block Diagram
      2. 6.15.2 Analog Pins and Internal Connections
      3. 6.15.3 Analog Signal Descriptions
      4. 6.15.4 Analog-to-Digital Converter (ADC)
        1. 6.15.4.1 ADC Configurability
          1. 6.15.4.1.1 Signal Mode
        2. 6.15.4.2 ADC Electrical Data and Timing
          1. 6.15.4.2.1 ADC Operating Conditions
          2. 6.15.4.2.2 ADC Characteristics
          3. 6.15.4.2.3 ADC INL and DNL
          4. 6.15.4.2.4 ADC Performance Per Pin
          5. 6.15.4.2.5 ADC Input Model
          6. 6.15.4.2.6 ADC Timing Diagrams
      5. 6.15.5 Temperature Sensor
        1. 6.15.5.1 Temperature Sensor Electrical Data and Timing
          1. 6.15.5.1.1 Temperature Sensor Characteristics
      6. 6.15.6 Comparator Subsystem (CMPSS)
        1. 6.15.6.1 CMPx_DACL
        2. 6.15.6.2 CMPSS Connectivity Diagram
        3. 6.15.6.3 Block Diagram
        4. 6.15.6.4 CMPSS Electrical Data and Timing
          1. 6.15.6.4.1 CMPSS Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.15.6.4.2 CMPSS DAC Static Electrical Characteristics
          4. 6.15.6.4.3 CMPSS Illustrative Graphs
          5. 6.15.6.4.4 Buffered Output from CMPx_DACL Operating Conditions
          6. 6.15.6.4.5 Buffered Output from CMPx_DACL Electrical Characteristics
      7. 6.15.7 Buffered Digital-to-Analog Converter (DAC)
        1. 6.15.7.1 Buffered DAC Electrical Data and Timing
          1. 6.15.7.1.1 Buffered DAC Operating Conditions
          2. 6.15.7.1.2 Buffered DAC Electrical Characteristics
      8. 6.15.8 Programmable Gain Amplifier (PGA)
        1. 6.15.8.1 PGA Electrical Data and Timing
          1. 6.15.8.1.1 PGA Operating Conditions
          2. 6.15.8.1.2 PGA Characteristics
    16. 6.16 Control Peripherals
      1. 6.16.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.16.1.1 Control Peripherals Synchronization
        2. 6.16.1.2 ePWM Electrical Data and Timing
          1. 6.16.1.2.1 ePWM Timing Requirements
          2. 6.16.1.2.2 ePWM Switching Characteristics
          3. 6.16.1.2.3 Trip-Zone Input Timing
            1. 6.16.1.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.16.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.16.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.16.2.1 HRPWM Electrical Data and Timing
          1. 6.16.2.1.1 High-Resolution PWM Characteristics
      3. 6.16.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.16.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.16.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.16.4 Enhanced Capture (eCAP)
        1. 6.16.4.1 eCAP Block Diagram
        2. 6.16.4.2 eCAP Synchronization
        3. 6.16.4.3 eCAP Electrical Data and Timing
          1. 6.16.4.3.1 eCAP Timing Requirements
          2. 6.16.4.3.2 eCAP Switching Characteristics
      5. 6.16.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.16.5.1 eQEP Electrical Data and Timing
          1. 6.16.5.1.1 eQEP Timing Requirements
          2. 6.16.5.1.2 eQEP Switching Characteristics
    17. 6.17 Communications Peripherals
      1. 6.17.1 Modular Controller Area Network (MCAN)
      2. 6.17.2 Inter-Integrated Circuit (I2C)
        1. 6.17.2.1 I2C Electrical Data and Timing
          1. 6.17.2.1.1 I2C Timing Requirements
          2. 6.17.2.1.2 I2C Switching Characteristics
          3. 6.17.2.1.3 I2C Timing Diagram
      3. 6.17.3 Power Management Bus (PMBus) Interface
        1. 6.17.3.1 PMBus Electrical Data and Timing
          1. 6.17.3.1.1 PMBus Electrical Characteristics
          2. 6.17.3.1.2 PMBus Fast Plus Mode Switching Characteristics
          3. 6.17.3.1.3 PMBus Fast Mode Switching Characteristics
          4. 6.17.3.1.4 PMBus Standard Mode Switching Characteristics
      4. 6.17.4 Serial Communications Interface (SCI)
      5. 6.17.5 Serial Peripheral Interface (SPI)
        1. 6.17.5.1 SPI Controller Mode Timings
          1. 6.17.5.1.1 SPI Controller Mode Timing Requirements
          2. 6.17.5.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0
          3. 6.17.5.1.3 SPI Controller Mode Switching Characteristics - Clock Phase 1
          4. 6.17.5.1.4 SPI Controller Mode Timing Diagrams
        2. 6.17.5.2 SPI Peripheral Mode Timings
          1. 6.17.5.2.1 SPI Peripheral Mode Timing Requirements
          2. 6.17.5.2.2 SPI Peripheral Mode Switching Characteristics
          3. 6.17.5.2.3 SPI Peripheral Mode Timing Diagrams
      6. 6.17.6 Local Interconnect Network (LIN)
      7. 6.17.7 Fast Serial Interface (FSI)
        1. 6.17.7.1 FSI Transmitter
          1. 6.17.7.1.1 FSITX Electrical Data and Timing
            1. 6.17.7.1.1.1 FSITX Switching Characteristics
            2. 6.17.7.1.1.2 FSITX Timings
        2. 6.17.7.2 FSI Receiver
          1. 6.17.7.2.1 FSIRX Electrical Data and Timing
            1. 6.17.7.2.1.1 FSIRX Timing Requirements
            2. 6.17.7.2.1.2 FSIRX Switching Characteristics
            3. 6.17.7.2.1.3 FSIRX Timings
        3. 6.17.7.3 FSI SPI Compatibility Mode
          1. 6.17.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.17.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.17.7.3.1.2 FSITX SPI Signaling Mode Timings
      8. 6.17.8 Universal Serial Bus (USB)
        1. 6.17.8.1 USB Electrical Data and Timing
          1. 6.17.8.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.17.8.1.2 USB Output Ports DP and DM Switching Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
        3. 7.3.1.3 Global Shared RAM (GSx RAM)
        4. 7.3.1.4 Message RAM
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit (FPU)
      2. 7.6.2 Trigonometric Math Unit (TMU)
      3. 7.6.3 VCRC Unit
    7. 7.7  Control Law Accelerator (CLA)
    8. 7.8  Embedded Real-Time Analysis and Diagnostic (ERAD)
    9. 7.9  Direct Memory Access (DMA)
    10. 7.10 Device Boot Modes
      1. 7.10.1 Device Boot Configurations
        1. 7.10.1.1 Configuring Boot Mode Pins
        2. 7.10.1.2 Configuring Boot Mode Table Options
      2. 7.10.2 GPIO Assignments
    11. 7.11 Security
      1. 7.11.1 Securing the Boundary of the Chip
        1. 7.11.1.1 JTAGLOCK
        2. 7.11.1.2 Zero-pin Boot
      2. 7.11.2 Dual-Zone Security
      3. 7.11.3 Disclaimer
    12. 7.12 Watchdog
    13. 7.13 C28x Timers
    14. 7.14 Dual-Clock Comparator (DCC)
      1. 7.14.1 Features
      2. 7.14.2 Mapping of DCCx Clock Source Inputs
    15. 7.15 Configurable Logic Block (CLB)
  9. 8 Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2.     TAPE AND REEL INFORMATION
    3.     TRAY

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PNA|80
  • PM|64
  • RSH|56
  • PZ|100
  • PDT|128
Thermal pad, mechanical data (Package|Pins)

5.2 Pin Attributes

Table 5-1 Pin Attributes
SIGNAL NAME MUX POSITION 128 PDT 100 PZ 80 PNA 64 PM 56 RSH PIN TYPE DESCRIPTION
ANALOG
A0 30 23 19 15 13 I ADC-A Input 0
B15 I ADC-B Input 15
C15 I ADC-C Input 15
CMP3_HP2 I CMPSS-3 High Comparator Positive Input 2
CMP3_LP2 I CMPSS-3 Low Comparator Positive Input 2
DACA_OUT O Buffered DAC-A Output.
AIO231 0, 4, 8, 12 I Analog Pin Used For Digital Input 231
A1 29 22 18 14 12 I ADC-A Input 1
B7 I ADC-B Input 7
CMP1_DACL I CMPSS-1 Low DAC Output
CMP1_HP4 I CMPSS-1 High Comparator Positive Input 4
CMP1_LP4 I CMPSS-1 Low Comparator Positive Input 4
D11 I ADC-D Input 11
AIO232 0, 4, 8, 12 I Analog Pin Used For Digital Input 232
A2 21 17 13 9 7 I ADC-A Input 2
B6 I ADC-B Input 6
C9 I ADC-C Input 9
CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0
CMP1_LP0 I CMPSS-1 Low Comparator Positive Input 0
GPIO224 I/O General-Purpose Input Output 224 This pin also has digital mux functions which are described in the GPIO section of this table.
PGA1_INP I PGA-1 Plus
A3 18 I ADC-A Input 3
CMP3_HP5 I CMPSS-3 High Comparator Positive Input 5
CMP3_LP5 I CMPSS-3 Low Comparator Positive Input 5
AIO229 0, 4, 8, 12 I Analog Pin Used For Digital Input 229
A3 20 12 8 6 I ADC-A Input 3
CMP3_HP5 I CMPSS-3 High Comparator Positive Input 5
CMP3_LP5 I CMPSS-3 Low Comparator Positive Input 5
A4 42 36 27 23 21 I ADC-A Input 4
B8 I ADC-B Input 8
CMP2_HP0 I CMPSS-2 High Comparator Positive Input 0
CMP2_LP0 I CMPSS-2 Low Comparator Positive Input 0
AIO225 0, 4, 8, 12 I Analog Pin Used For Digital Input 225
A5 35 I ADC-A Input 5
CMP2_HP5 I CMPSS-2 High Comparator Positive Input 5
CMP2_LP5 I CMPSS-2 Low Comparator Positive Input 5
AIO249 0, 4, 8, 12 I Analog Pin Used For Digital Input 249
A5 28 17 13 11 I ADC-A Input 5
CMP2_HP5 I CMPSS-2 High Comparator Positive Input 5
CMP2_LP5 I CMPSS-2 Low Comparator Positive Input 5
A6 18 14 10 6 I ADC-A Input 6
CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2
CMP1_LP2 I CMPSS-1 Low Comparator Positive Input 2
D14 I ADC-D Input 14
E14 I ADC-E Input 14
GPIO228 I/O General-Purpose Input Output 228 This pin also has digital mux functions which are described in the GPIO section of this table.
A7 37 31 23 19 17 I ADC-A Input 7
B30 I ADC-B Input 30
C3 I ADC-C Input 3
CMP4_HN1 I CMPSS-4 High Comparator Negative Input 1
CMP4_HP1 I CMPSS-4 High Comparator Positive Input 1
CMP4_LN1 I CMPSS-4 Low Comparator Negative Input 1
CMP4_LP1 I CMPSS-4 Low Comparator Positive Input 1
D12 I ADC-D Input 12
E30 I ADC-E Input 30
AIO245 0, 4, 8, 12 I Analog Pin Used For Digital Input 245
A8 37 I ADC-A Input 8
CMP4_HP4 I CMPSS-4 High Comparator Positive Input 4
CMP4_LP4 I CMPSS-4 Low Comparator Positive Input 4
AIO240 0, 4, 8, 12 I Analog Pin Used For Digital Input 240
A8 39 24 20 18 I ADC-A Input 8
B0 I ADC-B Input 0
C11 I ADC-C Input 11
CMP4_HP4 I CMPSS-4 High Comparator Positive Input 4
CMP4_LP4 I CMPSS-4 Low Comparator Positive Input 4
AIO241 0, 4, 8, 12 I Analog Pin Used For Digital Input 241
A9 48 38 28 24 22 I ADC-A Input 9
CMP2_HP2 I CMPSS-2 High Comparator Positive Input 2
CMP2_LP2 I CMPSS-2 Low Comparator Positive Input 2
GPIO227 I/O General-Purpose Input Output 227 This pin also has digital mux functions which are described in the GPIO section of this table.
A10 50 40 29 25 23 I ADC-A Input 10
B1 I ADC-B Input 1
C10 I ADC-C Input 10
CMP2_HN0 I CMPSS-2 High Comparator Negative Input 0
CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3
CMP2_LN0 I CMPSS-2 Low Comparator Negative Input 0
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3
GPIO230 I/O General-Purpose Input Output 230 This pin also has digital mux functions which are described in the GPIO section of this table.
A11 27 20 16 12 10 I ADC-A Input 11
B10 I ADC-B Input 10
C0 I ADC-C Input 0
CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1
CMP1_HP1 I CMPSS-1 High Comparator Positive Input 1
CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1
CMP1_LP1 I CMPSS-1 Low Comparator Positive Input 1
PGA2_OUT O PGA-2 Output
AIO237 0, 4, 8, 12 I Analog Pin Used For Digital Input 237
A12 35 28 22 18 16 I ADC-A Input 12
CMP2_HN1 I CMPSS-2 High Comparator Negative Input 1
CMP2_HP1 I CMPSS-2 High Comparator Positive Input 1
CMP2_LN1 I CMPSS-2 Low Comparator Negative Input 1
CMP2_LP1 I CMPSS-2 Low Comparator Positive Input 1
AIO238 0, 4, 8, 12 I Analog Pin Used For Digital Input 238
A13 34 26 21 17 15 I ADC-A Input 13
B13 I ADC-B Input 13
C13 I ADC-C Input 13
D13 I ADC-D Input 13
E13 I ADC-E Input 13
VREFLO(1) I ADC Low Reference
AIO235 0, 4, 8, 12 I Analog Pin Used For Digital Input 235
A13 33, 34 26, 27 21 17 15 I ADC-A Input 13
B13 I ADC-B Input 13
C13 I ADC-C Input 13
D13 I ADC-D Input 13
E13 I ADC-E Input 13
VREFLO(1) I ADC Low Reference
AIO235 ALT I Analog Pin Used For Digital Input 235
A14 26 19 15 11 9 I ADC-A Input 14
B14 I ADC-B Input 14
C4 I ADC-C Input 4
CMP3_HP4 I CMPSS-3 High Comparator Positive Input 4
CMP3_LP4 I CMPSS-3 Low Comparator Positive Input 4
PGA1_OUT O PGA-1 Output
AIO239 0, 4, 8, 12 I Analog Pin Used For Digital Input 239
A15 22 14 10 8 I ADC-A Input 15
CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0
CMP1_HP3 I CMPSS-1 High Comparator Positive Input 3
CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0
CMP1_LP3 I CMPSS-1 Low Comparator Positive Input 3
AIO233 0, 4, 8, 12 I Analog Pin Used For Digital Input 233
A16 2 1 4 2 3 I ADC-A Input 16
B16 I ADC-B Input 16
C16 I ADC-C Input 16
GPIO28 I/O General-Purpose Input Output 28 This pin also has digital mux functions which are described in the GPIO section of this table.
A17 60 48 33 27 24 I ADC-A Input 17
B17 I ADC-B Input 17
C17 I ADC-C Input 17
GPIO20 I/O General-Purpose Input Output 20 This pin also has digital mux functions which are described in the GPIO section of this table.
A18 61 49 34 28 25 I ADC-A Input 18
B18 I ADC-B Input 18
C18 I ADC-C Input 18
GPIO21 I/O General-Purpose Input Output 21 This pin also has digital mux functions which are described in the GPIO section of this table.
A19 62 50 35 29 26 I ADC-A Input 19
B19 I ADC-B Input 19
C19 I ADC-C Input 19
GPIO13 I/O General-Purpose Input Output 13 This pin also has digital mux functions which are described in the GPIO section of this table.
A20 63 51 36 30 27 I ADC-A Input 20
B20 I ADC-B Input 20
C20 I ADC-C Input 20
GPIO12 I/O General-Purpose Input Output 12 This pin also has digital mux functions which are described in the GPIO section of this table.
A24 64 52 37 31 28 I ADC-A Input 24
D0 I ADC-D Input 0
E0 I ADC-E Input 0
GPIO11 I/O General-Purpose Input Output 11 This pin also has digital mux functions which are described in the GPIO section of this table.
A25 67 55 40 34 31 I ADC-A Input 25
D3 I ADC-D Input 3
E3 I ADC-E Input 3
GPIO17 I/O General-Purpose Input Output 17 This pin also has digital mux functions which are described in the GPIO section of this table.
A26 24 I ADC-A Input 26
D6 I ADC-D Input 6
E6 I ADC-E Input 6
AIO209 0, 4, 8, 12 I Analog Pin Used For Digital Input 209
A27 44 I ADC-A Input 27
AIO227 I Analog Pin Used For Digital Input 227
D9 I ADC-D Input 9
E9 I ADC-E Input 9
A28 47 I ADC-A Input 28
AIO243 I Analog Pin Used For Digital Input 243
D19 I ADC-D Input 19
E19 I ADC-E Input 19
B0 41 I ADC-B Input 0
C11 I ADC-C Input 11
CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3
GPIO231 I/O General-Purpose Input Output 231 This pin also has digital mux functions which are described in the GPIO section of this table.
B2 19 15 11 7 I ADC-B Input 2
C6 I ADC-C Input 6
CMP3_HP0 I CMPSS-3 High Comparator Positive Input 0
CMP3_LP0 I CMPSS-3 Low Comparator Positive Input 0
E12 I ADC-E Input 12
GPIO226 I/O General-Purpose Input Output 226 This pin also has digital mux functions which are described in the GPIO section of this table.
B3 20 16 12 8 6 I ADC-B Input 3
CMP3_HN0 I CMPSS-3 High Comparator Negative Input 0
CMP3_HP3 I CMPSS-3 High Comparator Positive Input 3
CMP3_LN0 I CMPSS-3 Low Comparator Negative Input 0
CMP3_LP3 I CMPSS-3 Low Comparator Positive Input 3
GPIO242 I/O General-Purpose Input Output 242 This pin also has digital mux functions which are described in the GPIO section of this table.
PGA2_INP I PGA-2 Plus
B4 49 39 28 24 22 I ADC-B Input 4
C8 I ADC-C Input 8
CMP4_HP0 I CMPSS-4 High Comparator Positive Input 0
CMP4_LP0 I CMPSS-4 Low Comparator Positive Input 0
GPIO236 0, 4, 8, 12 I/O General-Purpose Input Output 236 This pin also has digital mux functions which are described in the GPIO section of this table.
B5 38 32 I ADC-B Input 5
CMP1_HP5 I CMPSS-1 High Comparator Positive Input 5
CMP1_LP5 I CMPSS-1 Low Comparator Positive Input 5
D15 I ADC-D Input 15
E15 I ADC-E Input 15
AIO252 0, 4, 8, 12 I Analog Pin Used For Digital Input 252
B9 22 18 14 10 8 I ADC-B Input 9
C7 I ADC-C Input 7
PGA1_INM I PGA-1 Minus
B11 36 30 I ADC-B Input 11
CMP4_HP5 I CMPSS-4 High Comparator Positive Input 5
CMP4_LP5 I CMPSS-4 Low Comparator Positive Input 5
D16 I ADC-D Input 16
E16 I ADC-E Input 16
AIO251 0, 4, 8, 12 I Analog Pin Used For Digital Input 251
B12 28 21 17 13 11 I ADC-B Input 12
C2 I ADC-C Input 2
CMP3_HN1 I CMPSS-3 High Comparator Negative Input 1
CMP3_HP1 I CMPSS-3 High Comparator Positive Input 1
CMP3_LN1 I CMPSS-3 Low Comparator Negative Input 1
CMP3_LP1 I CMPSS-3 Low Comparator Positive Input 1
PGA2_INM I PGA-2 Minus
AIO244 0, 4, 8, 12 I Analog Pin Used For Digital Input 244
B24 65 53 38 32 29 I ADC-B Input 24
D1 I ADC-D Input 1
E1 I ADC-E Input 1
GPIO33 I/O General-Purpose Input Output 33 This pin also has digital mux functions which are described in the GPIO section of this table.
B25 68 56 41 35 32 I ADC-B Input 25
D4 I ADC-D Input 4
E4 I ADC-E Input 4
GPIO24 I/O General-Purpose Input Output 24 This pin also has digital mux functions which are described in the GPIO section of this table.
B26 25 I ADC-B Input 26
D7 I ADC-D Input 7
E7 I ADC-E Input 7
AIO210 0, 4, 8, 12 I Analog Pin Used For Digital Input 210
AIO228 45 I Analog Pin Used For Digital Input 228
B27 I ADC-B Input 27
D10 I ADC-D Input 10
E10 I ADC-E Input 10
C1 35 29 22 18 16 I ADC-C Input 1
CMP4_HP2 I CMPSS-4 High Comparator Positive Input 2
CMP4_LP2 I CMPSS-4 Low Comparator Positive Input 2
E11 I ADC-E Input 11
PGA3_INP I PGA-3 Plus
AIO248 0, 4, 8, 12 I Analog Pin Used For Digital Input 248
C5 20 28 12 8 6 I ADC-C Input 5
C14 42 I ADC-C Input 14
CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0
CMP4_HP3 I CMPSS-4 High Comparator Positive Input 3
CMP4_LN0 I CMPSS-4 Low Comparator Negative Input 0
CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3
GPIO247 I/O General-Purpose Input Output 247 This pin also has digital mux functions which are described in the GPIO section of this table.
C14 42 27 23 21 I ADC-C Input 14
CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0
CMP4_HP3 I CMPSS-4 High Comparator Positive Input 3
CMP4_LN0 I CMPSS-4 Low Comparator Negative Input 0
CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3
C24 66 54 39 33 30 I ADC-C Input 24
D2 I ADC-D Input 2
E2 I ADC-E Input 2
GPIO16 I/O General-Purpose Input Output 16 This pin also has digital mux functions which are described in the GPIO section of this table.
AIO253 23 I Analog Pin Used For Digital Input 253
C25 I ADC-C Input 25
D5 I ADC-D Input 5
E5 I ADC-E Input 5
AIO208 0, 4, 8, 12 I Analog Pin Used For Digital Input 208
AIO226 43 I Analog Pin Used For Digital Input 226
C26 I ADC-C Input 26
D8 I ADC-D Input 8
E8 I ADC-E Input 8
AIO242 46 I Analog Pin Used For Digital Input 242
C27 I ADC-C Input 27
D18 I ADC-D Input 18
E18 I ADC-E Input 18
D20 31 24 20 16 14 I ADC-D Input 20
E20 I ADC-E Input 20
VREFHI(2) I ADC High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHI and VREFLO pins.
AIO234 0, 4, 8, 12 I Analog Pin Used For Digital Input 234
D20 32 25 20 16 14 I ADC-D Input 20
E20 I ADC-E Input 20
VREFHI(2) I ADC High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHI and VREFLO pins.
AIO234 ALT I Analog Pin Used For Digital Input 234
PGA3_INM 36 30 23 19 17 I PGA-3 Minus
PGA3_OUT 38 32 24 20 18 O PGA-3 Output
GPIO
GPIO236 0, 4, 8, 12 49 39 28 24 22 I/O General-Purpose Input Output 236 This pin also has analog functions which are described in the ANALOG section of this table.
EPWM7_A 1 O ePWM-7 Output A
EQEP1_INDEX 5 I/O eQEP-1 Index
EPWM12_A 9 O ePWM-12 Output A
GPIO0 0, 4, 8, 12 100 79 63 52 47 I/O General-Purpose Input Output 0
EPWM1_A 1 O ePWM-1 Output A
OUTPUTXBAR7 3 O Output X-BAR Output 7
SCIA_RX 5 I SCI-A Receive Data
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
SPIA_PTE 7 I/O SPI-A Peripheral Transmit Enable (PTE)
FSIRXA_CLK 9 I FSIRX-A Input Clock
MCANA_RX 10 I CAN/CAN FD Receive
CLB_OUTPUTXBAR8 11 O CLB Output X-BAR Output 8
EQEP1_INDEX 13 I/O eQEP-1 Index
EPWM3_A 15 O ePWM-3 Output A
GPIO1 0, 4, 8, 12 99 78 62 51 46 I/O General-Purpose Input Output 1
EPWM1_B 1 O ePWM-1 Output B
SCIA_TX 5 O SCI-A Transmit Data
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
SPIA_POCI 7 I/O SPI-A Peripheral Out, Controller In (POCI)
EQEP1_STROBE 9 I/O eQEP-1 Strobe
MCANA_TX 10 O CAN/CAN FD Transmit
CLB_OUTPUTXBAR7 11 O CLB Output X-BAR Output 7
EPWM10_B 13 O ePWM-10 Output B
EPWM3_B 15 O ePWM-3 Output B
GPIO2 0, 4, 8, 12 98 77 61 50 45 I/O General-Purpose Input Output 2
EPWM2_A 1 O ePWM-2 Output A
OUTPUTXBAR1 5 O Output X-BAR Output 1
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
SPIA_PICO 7 I/O SPI-A Peripheral In, Controller Out (PICO)
SCIA_TX 9 O SCI-A Transmit Data
FSIRXA_D1 10 I FSIRX-A Optional Additional Data Input
I2CB_SDA 11 I/OD I2C-B Open-Drain Bidirectional Data
EPWM10_A 13 O ePWM-10 Output A
MCANB_TX 14 O CAN/CAN FD Transmit
EPWM4_A 15 O ePWM-4 Output A
GPIO3 0, 4, 8, 12 97 76 60 49 44 I/O General-Purpose Input Output 3
EPWM2_B 1 O ePWM-2 Output B
OUTPUTXBAR2 2, 5 O Output X-BAR Output 2
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
SPIA_CLK 7 I/O SPI-A Clock
SCIA_RX 9 I SCI-A Receive Data
FSIRXA_D0 10 I FSIRX-A Primary Data Input
I2CB_SCL 11 I/OD I2C-B Open-Drain Bidirectional Clock
MCANB_RX 14 I CAN/CAN FD Receive
EPWM4_B 15 O ePWM-4 Output B
GPIO4 0, 4, 8, 12 96 75 59 48 43 I/O General-Purpose Input Output 4
EPWM3_A 1 O ePWM-3 Output A
I2CA_SCL 2 I/OD I2C-A Open-Drain Bidirectional Clock
MCANA_TX 3 O CAN/CAN FD Transmit
OUTPUTXBAR3 5 O Output X-BAR Output 3
SPIB_CLK 7 I/O SPI-B Clock
EQEP2_STROBE 9 I/O eQEP-2 Strobe
FSIRXA_CLK 10 I FSIRX-A Input Clock
CLB_OUTPUTXBAR6 11 O CLB Output X-BAR Output 6
EPWM11_B 13 O ePWM-11 Output B
SPIA_POCI 14 I/O SPI-A Peripheral Out, Controller In (POCI)
EPWM1_A 15 O ePWM-1 Output A
GPIO5 0, 4, 8, 12 118 89 74 61 55 I/O General-Purpose Input Output 5
EPWM3_B 1 O ePWM-3 Output B
I2CA_SDA 2 I/OD I2C-A Open-Drain Bidirectional Data
OUTPUTXBAR3 3 O Output X-BAR Output 3
MCANA_RX 5 I CAN/CAN FD Receive
SPIA_PTE 7 I/O SPI-A Peripheral Transmit Enable (PTE)
FSITXA_D1 9 O FSITX-A Optional Additional Data Output
CLB_OUTPUTXBAR5 10 O CLB Output X-BAR Output 5
SCIA_RX 11 I SCI-A Receive Data
EPWM1_B 15 O ePWM-1 Output B
GPIO6 0, 4, 8, 12 126 97 80 64 1 I/O General-Purpose Input Output 6
EPWM4_A 1 O ePWM-4 Output A
OUTPUTXBAR4 2 O Output X-BAR Output 4
SYNCOUT 3 O External ePWM Synchronization Pulse
EQEP1_A 5 I eQEP-1 Input A
SPIB_POCI 7 I/O SPI-B Peripheral Out, Controller In (POCI)
FSITXA_D0 9 O FSITX-A Primary Data Output
FSITXA_D1 11 O FSITX-A Optional Additional Data Output
CLB_OUTPUTXBAR8 14 O CLB Output X-BAR Output 8
EPWM2_A 15 O ePWM-2 Output A
GPIO7 0, 4, 8, 12 105 84 68 57 52 I/O General-Purpose Input Output 7
EPWM4_B 1 O ePWM-4 Output B
EPWM2_A 2 O ePWM-2 Output A
OUTPUTXBAR5 3 O Output X-BAR Output 5
EQEP1_B 5 I eQEP-1 Input B
SPIB_PICO 7 I/O SPI-B Peripheral In, Controller Out (PICO)
FSITXA_CLK 9 O FSITX-A Output Clock
CLB_OUTPUTXBAR2 10 O CLB Output X-BAR Output 2
SCIA_TX 11 O SCI-A Transmit Data
MCANA_TX 14 O CAN/CAN FD Transmit
EPWM2_B 15 O ePWM-2 Output B
GPIO8 0, 4, 8, 12 95 74 58 47 I/O General-Purpose Input Output 8
EPWM5_A 1 O ePWM-5 Output A
ADCSOCAO 3 O ADC Start of Conversion A for External ADC
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SCIA_TX 6 O SCI-A Transmit Data
SPIA_PICO 7 I/O SPI-A Peripheral In, Controller Out (PICO)
I2CA_SCL 9 I/OD I2C-A Open-Drain Bidirectional Clock
FSITXA_D1 10 O FSITX-A Optional Additional Data Output
CLB_OUTPUTXBAR5 11 O CLB Output X-BAR Output 5
EPWM11_A 13 O ePWM-11 Output A
GPIO9 0, 4, 8, 12 119 90 75 62 56 I/O General-Purpose Input Output 9
EPWM5_B 1 O ePWM-5 Output B
SCIB_TX 2 O SCI-B Transmit Data
OUTPUTXBAR6 3 O Output X-BAR Output 6
EQEP1_INDEX 5 I/O eQEP-1 Index
SCIA_RX 6 I SCI-A Receive Data
SPIA_CLK 7 I/O SPI-A Clock
I2CA_SCL 9 I/OD I2C-A Open-Drain Bidirectional Clock
FSITXA_D0 10 O FSITX-A Primary Data Output
LINA_RX 11 I LIN-A Receive
PMBUSA_SCL 13 I/OD PMBus-A Open-Drain Bidirectional Clock
I2CB_SCL 14 I/OD I2C-B Open-Drain Bidirectional Clock
EQEP3_B 15 I eQEP-3 Input B
GPIO10 0, 4, 8, 12 122 93 76 63 I/O General-Purpose Input Output 10
EPWM6_A 1 O ePWM-6 Output A
ADCSOCBO 3 O ADC Start of Conversion B for External ADC
EQEP1_A 5 I eQEP-1 Input A
SCIB_TX 6 O SCI-B Transmit Data
SPIA_POCI 7 I/O SPI-A Peripheral Out, Controller In (POCI)
I2CA_SDA 9 I/OD I2C-A Open-Drain Bidirectional Data
FSITXA_CLK 10 O FSITX-A Output Clock
LINA_TX 11 O LIN-A Transmit
EQEP3_STROBE 13 I/O eQEP-3 Strobe
CLB_OUTPUTXBAR4 15 O CLB Output X-BAR Output 4
GPIO11 0, 4, 8, 12 64 52 37 31 28 I/O General-Purpose Input Output 11 This pin also has analog functions which are described in the ANALOG section of this table.
EPWM6_B 1 O ePWM-6 Output B
MCANA_RX 2 I CAN/CAN FD Receive
OUTPUTXBAR7 3 O Output X-BAR Output 7
EQEP1_B 5 I eQEP-1 Input B
SCIB_RX 6 I SCI-B Receive Data
SPIA_PTE 7 I/O SPI-A Peripheral Transmit Enable (PTE)
FSIRXA_D1 9 I FSIRX-A Optional Additional Data Input
LINA_RX 10 I LIN-A Receive
EQEP2_A 11 I eQEP-2 Input A
SPIA_PICO 13 I/O SPI-A Peripheral In, Controller Out (PICO)
EQEP3_INDEX 15 I/O eQEP-3 Index
GPIO12 0, 4, 8, 12 63 51 36 30 27 I/O General-Purpose Input Output 12 This pin also has analog functions which are described in the ANALOG section of this table.
EPWM7_A 1 O ePWM-7 Output A
MCANA_RX 3 I CAN/CAN FD Receive
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SCIB_TX 6 O SCI-B Transmit Data
PMBUSA_CTL 7 I/O PMBus-A Control Signal - Target Input/Controller Output
FSIRXA_D0 9 I FSIRX-A Primary Data Input
LINA_TX 10 O LIN-A Transmit
SPIA_CLK 11 I/O SPI-A Clock
GPIO13 0, 4, 8, 12 62 50 35 29 26 I/O General-Purpose Input Output 13 This pin also has analog functions which are described in the ANALOG section of this table.
EPWM7_B 1 O ePWM-7 Output B
MCANA_TX 3 O CAN/CAN FD Transmit
EQEP1_INDEX 5 I/O eQEP-1 Index
SCIB_RX 6 I SCI-B Receive Data
PMBUSA_ALERT 7 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
FSIRXA_CLK 9 I FSIRX-A Input Clock
LINA_RX 10 I LIN-A Receive
SPIA_POCI 11 I/O SPI-A Peripheral Out, Controller In (POCI)
GPIO14 0, 4, 8, 12 125 96 79 I/O General-Purpose Input Output 14
EPWM8_A 1 O ePWM-8 Output A
SCIB_TX 2 O SCI-B Transmit Data
I2CB_SDA 5 I/OD I2C-B Open-Drain Bidirectional Data
OUTPUTXBAR3 6 O Output X-BAR Output 3
PMBUSA_SDA 7 I/OD PMBus-A Open-Drain Bidirectional Data
SPIB_CLK 9 I/O SPI-B Clock
EQEP2_A 10 I eQEP-2 Input A
LINA_TX 11 O LIN-A Transmit
EPWM3_A 13 O ePWM-3 Output A
CLB_OUTPUTXBAR7 14 O CLB Output X-BAR Output 7
GPIO15 0, 4, 8, 12 124 95 78 I/O General-Purpose Input Output 15
EPWM8_B 1 O ePWM-8 Output B
SCIB_RX 2 I SCI-B Receive Data
I2CB_SCL 5 I/OD I2C-B Open-Drain Bidirectional Clock
OUTPUTXBAR4 6 O Output X-BAR Output 4
PMBUSA_SCL 7 I/OD PMBus-A Open-Drain Bidirectional Clock
SPIB_PTE 9 I/O SPI-B Peripheral Transmit Enable (PTE)
EQEP2_B 10 I eQEP-2 Input B
LINA_RX 11 I LIN-A Receive
EPWM3_B 13 O ePWM-3 Output B
CLB_OUTPUTXBAR6 14 O CLB Output X-BAR Output 6
GPIO16 0, 4, 8, 12 66 54 39 33 30 I/O General-Purpose Input Output 16 This pin also has analog functions which are described in the ANALOG section of this table.
SPIA_PICO 1 I/O SPI-A Peripheral In, Controller Out (PICO)
OUTPUTXBAR7 3 O Output X-BAR Output 7
EPWM9_A 5 O ePWM-9 Output A
SCIA_TX 6 O SCI-A Transmit Data
EQEP1_STROBE 9 I/O eQEP-1 Strobe
PMBUSA_SCL 10 I/OD PMBus-A Open-Drain Bidirectional Clock
XCLKOUT 11 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
EQEP2_B 13 I eQEP-2 Input B
SPIB_POCI 14 I/O SPI-B Peripheral Out, Controller In (POCI)
EQEP3_STROBE 15 I/O eQEP-3 Strobe
GPIO17 0, 4, 8, 12 67 55 40 34 31 I/O General-Purpose Input Output 17 This pin also has analog functions which are described in the ANALOG section of this table.
SPIA_POCI 1 I/O SPI-A Peripheral Out, Controller In (POCI)
OUTPUTXBAR8 3 O Output X-BAR Output 8
EPWM9_B 5 O ePWM-9 Output B
SCIA_RX 6 I SCI-A Receive Data
EQEP1_INDEX 9 I/O eQEP-1 Index
PMBUSA_SDA 10 I/OD PMBus-A Open-Drain Bidirectional Data
MCANA_TX 11 O CAN/CAN FD Transmit
EPWM6_A 14 O ePWM-6 Output A
GPIO18 0, 4, 8, 12 87 68 50 41 38 I/O General-Purpose Input Output 18
SPIA_CLK 1 I/O SPI-A Clock
SCIB_TX 2 O SCI-B Transmit Data
MCANB_RX 3 I CAN/CAN FD Receive
EPWM6_A 5 O ePWM-6 Output A
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
EQEP2_A 9 I eQEP-2 Input A
PMBUSA_CTL 10 I/O PMBus-A Control Signal - Target Input/Controller Output
XCLKOUT 11 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
LINA_TX 13 O LIN-A Transmit
EQEP3_INDEX 15 I/O eQEP-3 Index
X2 ALT I/O Crystal oscillator output.
GPIO19 0, 4, 8, 12 88 69 51 42 39 I/O General-Purpose Input Output 19
SPIA_PTE 1 I/O SPI-A Peripheral Transmit Enable (PTE)
SCIB_RX 2 I SCI-B Receive Data
MCANB_TX 3 O CAN/CAN FD Transmit
EPWM6_B 5 O ePWM-6 Output B
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
EQEP2_B 9 I eQEP-2 Input B
PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
CLB_OUTPUTXBAR1 11 O CLB Output X-BAR Output 1
LINA_RX 13 I LIN-A Receive
X1 ALT I/O Crystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock.
GPIO20 0, 4, 8, 12 60 48 33 27 24 I/O General-Purpose Input Output 20 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP1_A 1 I eQEP-1 Input A
EPWM12_A 5 O ePWM-12 Output A
SPIB_PICO 6 I/O SPI-B Peripheral In, Controller Out (PICO)
MCANA_TX 9 O CAN/CAN FD Transmit
ADCE_EXTMUXSEL0 10 O ADCE external mux selection pin for position 0
I2CA_SCL 11 I/OD I2C-A Open-Drain Bidirectional Clock
SCIC_TX 15 O SCI-C Transmit Data
GPIO21 0, 4, 8, 12 61 49 34 28 25 I/O General-Purpose Input Output 21 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP1_B 1 I eQEP-1 Input B
EPWM12_B 5 O ePWM-12 Output B
SPIB_POCI 6 I/O SPI-B Peripheral Out, Controller In (POCI)
MCANA_RX 9 I CAN/CAN FD Receive
ADCE_EXTMUXSEL1 10 O ADCE external mux selection pin for position 1
I2CA_SDA 11 I/OD I2C-A Open-Drain Bidirectional Data
SCIC_RX 15 I SCI-C Receive Data
GPIO22 0, 4, 8, 12 104 83 67 56 51 I/O General-Purpose Input Output 22
EQEP1_STROBE 1 I/O eQEP-1 Strobe
SCIB_TX 3 O SCI-B Transmit Data
SPIB_CLK 6 I/O SPI-B Clock
LINA_TX 9, 11 O LIN-A Transmit
CLB_OUTPUTXBAR1 10 O CLB Output X-BAR Output 1
EPWM4_A 14 O ePWM-4 Output A
EQEP3_A 15 I eQEP-3 Input A
GPIO23 0, 4, 8, 12 102 81 65 54 49 I/O General-Purpose Input Output 23
EQEP1_INDEX 1 I/O eQEP-1 Index
SCIB_RX 3 I SCI-B Receive Data
SPIB_PTE 6 I/O SPI-B Peripheral Transmit Enable (PTE)
LINA_RX 9, 11 I LIN-A Receive
CLB_OUTPUTXBAR3 10 O CLB Output X-BAR Output 3
EPWM12_A 13 O ePWM-12 Output A
EPWM4_B 14 O ePWM-4 Output B
USB0DM ALT O USB-0 PHY differential data
GPIO24 0, 4, 8, 12 68 56 41 35 32 I/O General-Purpose Input Output 24 This pin also has analog functions which are described in the ANALOG section of this table.
OUTPUTXBAR1 1 O Output X-BAR Output 1
EQEP2_A 2 I eQEP-2 Input A
SPIA_PTE 3 I/O SPI-A Peripheral Transmit Enable (PTE)
EPWM8_A 5 O ePWM-8 Output A
SPIB_PICO 6 I/O SPI-B Peripheral In, Controller Out (PICO)
LINA_TX 9 O LIN-A Transmit
PMBUSA_SCL 10 I/OD PMBus-A Open-Drain Bidirectional Clock
SCIA_TX 11 O SCI-A Transmit Data
ERRORSTS 13 O Error Status Output. This signal requires an external pulldown.
EPWM9_A 14 O ePWM-9 Output A
GPIO25 0, 4, 8, 12 69 57 42 I/O General-Purpose Input Output 25
OUTPUTXBAR2 1 O Output X-BAR Output 2
EQEP2_B 2 I eQEP-2 Input B
EQEP1_A 5 I eQEP-1 Input A
SPIB_POCI 6 I/O SPI-B Peripheral Out, Controller In (POCI)
FSITXA_D1 9 O FSITX-A Optional Additional Data Output
PMBUSA_SDA 10 I/OD PMBus-A Open-Drain Bidirectional Data
SCIA_RX 11 I SCI-A Receive Data
EQEP3_A 13 I eQEP-3 Input A
GPIO26 0, 4, 8, 12 70 58 43 I/O General-Purpose Input Output 26
OUTPUTXBAR3 1, 5 O Output X-BAR Output 3
EQEP2_INDEX 2 I/O eQEP-2 Index
SPIB_CLK 6 I/O SPI-B Clock
FSITXA_D0 9 O FSITX-A Primary Data Output
PMBUSA_CTL 10 I/O PMBus-A Control Signal - Target Input/Controller Output
I2CA_SDA 11 I/OD I2C-A Open-Drain Bidirectional Data
EQEP3_B 13 I eQEP-3 Input B
GPIO27 0, 4, 8, 12 71 59 44 I/O General-Purpose Input Output 27
OUTPUTXBAR4 1, 5 O Output X-BAR Output 4
EQEP2_STROBE 2 I/O eQEP-2 Strobe
SPIB_PTE 6 I/O SPI-B Peripheral Transmit Enable (PTE)
FSITXA_CLK 9 O FSITX-A Output Clock
PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
I2CA_SCL 11 I/OD I2C-A Open-Drain Bidirectional Clock
EQEP3_STROBE 13 I/O eQEP-3 Strobe
GPIO28 0, 4, 8, 12 2 1 4 2 3 I/O General-Purpose Input Output 28 This pin also has analog functions which are described in the ANALOG section of this table.
SCIA_RX 1 I SCI-A Receive Data
EPWM7_A 3 O ePWM-7 Output A
OUTPUTXBAR5 5 O Output X-BAR Output 5
EQEP1_A 6 I eQEP-1 Input A
EQEP2_STROBE 9 I/O eQEP-2 Strobe
LINA_TX 10 O LIN-A Transmit
SPIB_CLK 11 I/O SPI-B Clock
ERRORSTS 13 O Error Status Output. This signal requires an external pulldown.
I2CB_SDA 14 I/OD I2C-B Open-Drain Bidirectional Data
GPIO29 0, 4, 8, 12 1 100 3 1 2 I/O General-Purpose Input Output 29
SCIA_TX 1 O SCI-A Transmit Data
EPWM7_B 3 O ePWM-7 Output B
OUTPUTXBAR6 5 O Output X-BAR Output 6
EQEP1_B 6 I eQEP-1 Input B
EQEP2_INDEX 9 I/O eQEP-2 Index
LINA_RX 10 I LIN-A Receive
SPIB_PTE 11 I/O SPI-B Peripheral Transmit Enable (PTE)
ERRORSTS 13 O Error Status Output. This signal requires an external pulldown.
I2CB_SCL 14 I/OD I2C-B Open-Drain Bidirectional Clock
AUXCLKIN ALT I Auxiliary Clock Input
GPIO30 0, 4, 8, 12 127 98 1 I/O General-Purpose Input Output 30
SPIB_PICO 3 I/O SPI-B Peripheral In, Controller Out (PICO)
OUTPUTXBAR7 5 O Output X-BAR Output 7
EQEP1_STROBE 6 I/O eQEP-1 Strobe
FSIRXA_CLK 9 I FSIRX-A Input Clock
MCANA_RX 10 I CAN/CAN FD Receive
EPWM1_A 11 O ePWM-1 Output A
EQEP3_INDEX 13 I/O eQEP-3 Index
GPIO31 0, 4, 8, 12 128 99 2 I/O General-Purpose Input Output 31
SPIB_POCI 3 I/O SPI-B Peripheral Out, Controller In (POCI)
OUTPUTXBAR8 5 O Output X-BAR Output 8
EQEP1_INDEX 6 I/O eQEP-1 Index
FSIRXA_D1 9 I FSIRX-A Optional Additional Data Input
MCANA_TX 10 O CAN/CAN FD Transmit
EPWM1_B 11 O ePWM-1 Output B
GPIO32 0, 4, 8, 12 79 64 49 40 37 I/O General-Purpose Input Output 32
I2CA_SDA 1 I/OD I2C-A Open-Drain Bidirectional Data
EQEP1_INDEX 2 I/O eQEP-1 Index
SPIB_CLK 3 I/O SPI-B Clock
EPWM8_B 5 O ePWM-8 Output B
LINA_TX 6 O LIN-A Transmit
FSIRXA_D0 9 I FSIRX-A Primary Data Input
MCANB_TX 10 O CAN/CAN FD Transmit
PMBUSA_SDA 11 I/OD PMBus-A Open-Drain Bidirectional Data
ADCSOCBO 13 O ADC Start of Conversion B for External ADC
GPIO33 0, 4, 8, 12 65 53 38 32 29 I/O General-Purpose Input Output 33 This pin also has analog functions which are described in the ANALOG section of this table.
I2CA_SCL 1 I/OD I2C-A Open-Drain Bidirectional Clock
SPIB_PTE 3 I/O SPI-B Peripheral Transmit Enable (PTE)
OUTPUTXBAR4 5 O Output X-BAR Output 4
LINA_RX 6 I LIN-A Receive
FSIRXA_CLK 9 I FSIRX-A Input Clock
MCANB_RX 10 I CAN/CAN FD Receive
EQEP2_B 11 I eQEP-2 Input B
ADCSOCAO 13 O ADC Start of Conversion A for External ADC
SCIC_RX 15 I SCI-C Receive Data
GPIO34 0, 4, 8, 12 123 94 77 I/O General-Purpose Input Output 34
OUTPUTXBAR1 1 O Output X-BAR Output 1
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
I2CB_SDA 14 I/OD I2C-B Open-Drain Bidirectional Data
GPIO35 0, 4, 8, 12 78 63 48 39 36 I/O General-Purpose Input Output 35
SCIA_RX 1 I SCI-A Receive Data
SPIA_POCI 2 I/O SPI-A Peripheral Out, Controller In (POCI)
I2CA_SDA 3 I/OD I2C-A Open-Drain Bidirectional Data
MCANB_RX 5 I CAN/CAN FD Receive
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
LINA_RX 7 I LIN-A Receive
EQEP1_A 9 I eQEP-1 Input A
PMBUSA_CTL 10 I/O PMBus-A Control Signal - Target Input/Controller Output
EPWM5_B 11 O ePWM-5 Output B
TDI 15 I JTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input.
GPIO37 0, 4, 8, 12 76 61 46 37 34 I/O General-Purpose Input Output 37
OUTPUTXBAR2 1 O Output X-BAR Output 2
SPIA_PTE 2 I/O SPI-A Peripheral Transmit Enable (PTE)
I2CA_SCL 3 I/OD I2C-A Open-Drain Bidirectional Clock
SCIA_TX 5 O SCI-A Transmit Data
MCANB_TX 6 O CAN/CAN FD Transmit
LINA_TX 7 O LIN-A Transmit
EQEP1_B 9 I eQEP-1 Input B
PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
EPWM5_A 11 O ePWM-5 Output A
TDO 15 O JTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input.
GPIO40 0, 4, 8, 12 101 80 64 53 48 I/O General-Purpose Input Output 40
SPIB_PICO 1 I/O SPI-B Peripheral In, Controller Out (PICO)
EPWM2_B 5 O ePWM-2 Output B
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
FSIRXA_D0 7 I FSIRX-A Primary Data Input
SCIB_TX 9 O SCI-B Transmit Data
EQEP1_A 10 I eQEP-1 Input A
LINA_TX 11 O LIN-A Transmit
CLB_OUTPUTXBAR4 14 O CLB Output X-BAR Output 4
EQEP3_STROBE 15 I/O eQEP-3 Strobe
GPIO41 0, 4, 8, 12 103 82 66 55 50 I/O General-Purpose Input Output 41
EPWM7_A 1 O ePWM-7 Output A
EPWM2_A 5 O ePWM-2 Output A
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
FSIRXA_D1 7 I FSIRX-A Optional Additional Data Input
SCIB_RX 9 I SCI-B Receive Data
EQEP1_B 10 I eQEP-1 Input B
LINA_RX 11 I LIN-A Receive
EPWM12_B 13 O ePWM-12 Output B
SPIB_POCI 14 I/O SPI-B Peripheral Out, Controller In (POCI)
USB0DP ALT O USB-0 PHY differential data
GPIO42 0, 4, 8, 12 94 57 I/O General-Purpose Input Output 42
LINA_RX 2 I LIN-A Receive
OUTPUTXBAR5 3 O Output X-BAR Output 5
PMBUSA_CTL 5 I/O PMBus-A Control Signal - Target Input/Controller Output
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
SCIC_RX 7 I SCI-C Receive Data
EQEP1_STROBE 10 I/O eQEP-1 Strobe
CLB_OUTPUTXBAR3 11 O CLB Output X-BAR Output 3
GPIO43 0, 4, 8, 12 91 54 I/O General-Purpose Input Output 43
OUTPUTXBAR6 3 O Output X-BAR Output 6
PMBUSA_ALERT 5, 9 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
SCIC_TX 7 O SCI-C Transmit Data
EQEP1_INDEX 10 I/O eQEP-1 Index
CLB_OUTPUTXBAR4 11 O CLB Output X-BAR Output 4
GPIO44 0, 4, 8, 12 106 85 69 I/O General-Purpose Input Output 44
OUTPUTXBAR7 3 O Output X-BAR Output 7
EQEP1_A 5 I eQEP-1 Input A
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
FSITXA_CLK 7 O FSITX-A Output Clock
PMBUSA_CTL 9 I/O PMBus-A Control Signal - Target Input/Controller Output
CLB_OUTPUTXBAR3 10 O CLB Output X-BAR Output 3
FSIRXA_D0 11 I FSIRX-A Primary Data Input
LINA_TX 14 O LIN-A Transmit
GPIO45 0, 4, 8, 12 110 73 I/O General-Purpose Input Output 45
OUTPUTXBAR8 3 O Output X-BAR Output 8
FSITXA_D0 7 O FSITX-A Primary Data Output
PMBUSA_ALERT 9 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
CLB_OUTPUTXBAR4 10 O CLB Output X-BAR Output 4
GPIO46 0, 4, 8, 12 4 6 I/O General-Purpose Input Output 46
LINA_TX 3 O LIN-A Transmit
MCANA_TX 5 O CAN/CAN FD Transmit
FSITXA_D1 7 O FSITX-A Optional Additional Data Output
PMBUSA_SDA 9 I/OD PMBus-A Open-Drain Bidirectional Data
GPIO47 0, 4, 8, 12 8 6 I/O General-Purpose Input Output 47
LINA_RX 3 I LIN-A Receive
MCANA_RX 5 I CAN/CAN FD Receive
CLB_OUTPUTXBAR2 7 O CLB Output X-BAR Output 2
PMBUSA_SCL 9 I/OD PMBus-A Open-Drain Bidirectional Clock
GPIO48 0, 4, 8, 12 11 7 I/O General-Purpose Input Output 48
OUTPUTXBAR3 1 O Output X-BAR Output 3
MCANA_TX 5 O CAN/CAN FD Transmit
SCIA_TX 6 O SCI-A Transmit Data
PMBUSA_SDA 9 I/OD PMBus-A Open-Drain Bidirectional Data
GPIO49 0, 4, 8, 12 12 8 I/O General-Purpose Input Output 49
OUTPUTXBAR4 1 O Output X-BAR Output 4
MCANA_RX 5 I CAN/CAN FD Receive
SCIA_RX 6 I SCI-A Receive Data
LINA_RX 9 I LIN-A Receive
FSITXA_D0 14 O FSITX-A Primary Data Output
GPIO50 0, 4, 8, 12 13 9 I/O General-Purpose Input Output 50
EQEP1_A 1 I eQEP-1 Input A
MCANA_TX 5 O CAN/CAN FD Transmit
SPIB_PICO 6 I/O SPI-B Peripheral In, Controller Out (PICO)
I2CB_SDA 9 I/OD I2C-B Open-Drain Bidirectional Data
FSITXA_D1 14 O FSITX-A Optional Additional Data Output
GPIO51 0, 4, 8, 12 14 10 I/O General-Purpose Input Output 51
EQEP1_B 1 I eQEP-1 Input B
MCANA_RX 5 I CAN/CAN FD Receive
SPIB_POCI 6 I/O SPI-B Peripheral Out, Controller In (POCI)
I2CB_SCL 9 I/OD I2C-B Open-Drain Bidirectional Clock
FSITXA_CLK 14 O FSITX-A Output Clock
GPIO52 0, 4, 8, 12 15 11 I/O General-Purpose Input Output 52
EQEP1_STROBE 1 I/O eQEP-1 Strobe
CLB_OUTPUTXBAR5 5 O CLB Output X-BAR Output 5
SPIB_CLK 6 I/O SPI-B Clock
SYNCOUT 9 O External ePWM Synchronization Pulse
FSIRXA_D0 14 I FSIRX-A Primary Data Input
GPIO53 0, 4, 8, 12 16 12 I/O General-Purpose Input Output 53
EQEP1_INDEX 1 I/O eQEP-1 Index
CLB_OUTPUTXBAR6 5 O CLB Output X-BAR Output 6
SPIB_PTE 6 I/O SPI-B Peripheral Transmit Enable (PTE)
ADCSOCAO 9 O ADC Start of Conversion A for External ADC
MCANB_RX 10 I CAN/CAN FD Receive
FSIRXA_D1 14 I FSIRX-A Optional Additional Data Input
GPIO54 0, 4, 8, 12 17 13 I/O General-Purpose Input Output 54
SPIA_PICO 1 I/O SPI-A Peripheral In, Controller Out (PICO)
EQEP2_A 5 I eQEP-2 Input A
OUTPUTXBAR2 6 O Output X-BAR Output 2
ADCSOCBO 9 O ADC Start of Conversion B for External ADC
LINA_TX 10 O LIN-A Transmit
FSIRXA_CLK 14 I FSIRX-A Input Clock
GPIO55 0, 4, 8, 12 51 43 I/O General-Purpose Input Output 55
SPIA_POCI 1 I/O SPI-A Peripheral Out, Controller In (POCI)
EQEP2_B 5 I eQEP-2 Input B
OUTPUTXBAR3 6 O Output X-BAR Output 3
ERRORSTS 9 O Error Status Output. This signal requires an external pulldown.
LINA_RX 10 I LIN-A Receive
GPIO56 0, 4, 8, 12 80 65 I/O General-Purpose Input Output 56
SPIA_CLK 1 I/O SPI-A Clock
CLB_OUTPUTXBAR7 2 O CLB Output X-BAR Output 7
MCANA_TX 3 O CAN/CAN FD Transmit
EQEP2_STROBE 5 I/O eQEP-2 Strobe
SCIB_TX 6 O SCI-B Transmit Data
SPIB_PICO 9 I/O SPI-B Peripheral In, Controller Out (PICO)
I2CA_SDA 10 I/OD I2C-A Open-Drain Bidirectional Data
EQEP1_A 11 I eQEP-1 Input A
FSIRXA_D1 14 I FSIRX-A Optional Additional Data Input
GPIO57 0, 4, 8, 12 81 66 I/O General-Purpose Input Output 57
SPIA_PTE 1 I/O SPI-A Peripheral Transmit Enable (PTE)
CLB_OUTPUTXBAR8 2 O CLB Output X-BAR Output 8
MCANA_RX 3 I CAN/CAN FD Receive
EQEP2_INDEX 5 I/O eQEP-2 Index
SCIB_RX 6 I SCI-B Receive Data
SPIB_POCI 9 I/O SPI-B Peripheral Out, Controller In (POCI)
I2CA_SCL 10 I/OD I2C-A Open-Drain Bidirectional Clock
EQEP1_B 11 I eQEP-1 Input B
FSIRXA_CLK 14 I FSIRX-A Input Clock
GPIO58 0, 4, 8, 12 82 67 I/O General-Purpose Input Output 58
OUTPUTXBAR1 5 O Output X-BAR Output 1
SPIB_CLK 6 I/O SPI-B Clock
LINA_TX 9 O LIN-A Transmit
MCANB_TX 10 O CAN/CAN FD Transmit
EQEP1_STROBE 11 I/O eQEP-1 Strobe
FSIRXA_D0 14 I FSIRX-A Primary Data Input
GPIO59 0, 4, 8, 12 121 92 I/O General-Purpose Input Output 59
OUTPUTXBAR2 5 O Output X-BAR Output 2
SPIB_PTE 6 I/O SPI-B Peripheral Transmit Enable (PTE)
LINA_RX 9 I LIN-A Receive
MCANB_RX 10 I CAN/CAN FD Receive
EQEP1_INDEX 11 I/O eQEP-1 Index
GPIO60 0, 4, 8, 12 52 44 I/O General-Purpose Input Output 60
EPWM12_B 1 O ePWM-12 Output B
MCANA_TX 3 O CAN/CAN FD Transmit
OUTPUTXBAR3 5 O Output X-BAR Output 3
SPIB_PICO 6 I/O SPI-B Peripheral In, Controller Out (PICO)
GPIO61 0, 4, 8, 12 120 91 I/O General-Purpose Input Output 61
MCANA_RX 3 I CAN/CAN FD Receive
OUTPUTXBAR4 5 O Output X-BAR Output 4
SPIB_POCI 6 I/O SPI-B Peripheral Out, Controller In (POCI)
MCANB_RX 14 I CAN/CAN FD Receive
GPIO62 0, 4, 8, 12 58 46 31 I/O General-Purpose Input Output 62
EPWM10_A 1 O ePWM-10 Output A
OUTPUTXBAR3 2 O Output X-BAR Output 3
MCANA_TX 5 O CAN/CAN FD Transmit
SCIA_TX 6 O SCI-A Transmit Data
PMBUSA_SDA 9 I/OD PMBus-A Open-Drain Bidirectional Data
GPIO63 0, 4, 8, 12 59 47 32 I/O General-Purpose Input Output 63
EPWM10_B 1 O ePWM-10 Output B
OUTPUTXBAR4 2 O Output X-BAR Output 4
MCANA_RX 5 I CAN/CAN FD Receive
SCIA_RX 6 I SCI-A Receive Data
LINA_RX 9 I LIN-A Receive
GPIO64 0, 4, 8, 12 56 I/O General-Purpose Input Output 64
SCIA_RX 1 I SCI-A Receive Data
EPWM11_A 2 O ePWM-11 Output A
EPWM7_A 3 O ePWM-7 Output A
OUTPUTXBAR5 5 O Output X-BAR Output 5
EQEP1_A 6 I eQEP-1 Input A
EQEP2_STROBE 9 I/O eQEP-2 Strobe
LINA_TX 10 O LIN-A Transmit
SPIB_CLK 11 I/O SPI-B Clock
ERRORSTS 13 O Error Status Output. This signal requires an external pulldown.
I2CB_SDA 14 I/OD I2C-B Open-Drain Bidirectional Data
GPIO65 0, 4, 8, 12 57 I/O General-Purpose Input Output 65
EQEP1_A 1 I eQEP-1 Input A
EPWM11_B 2 O ePWM-11 Output B
SPIB_PICO 6 I/O SPI-B Peripheral In, Controller Out (PICO)
MCANA_TX 9 O CAN/CAN FD Transmit
I2CA_SCL 11 I/OD I2C-A Open-Drain Bidirectional Clock
GPIO66 0, 4, 8, 12 9 I/O General-Purpose Input Output 66
EQEP1_B 1 I eQEP-1 Input B
EPWM12_A 2 O ePWM-12 Output A
SPIB_POCI 6 I/O SPI-B Peripheral Out, Controller In (POCI)
MCANA_RX 9 I CAN/CAN FD Receive
I2CA_SDA 11 I/OD I2C-A Open-Drain Bidirectional Data
GPIO67 0, 4, 8, 12 10 I/O General-Purpose Input Output 67
EPWM7_B 1 O ePWM-7 Output B
EPWM12_B 2 O ePWM-12 Output B
MCANA_TX 3 O CAN/CAN FD Transmit
EQEP1_INDEX 5 I/O eQEP-1 Index
SCIB_RX 6 I SCI-B Receive Data
PMBUSA_ALERT 7 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
FSIRXA_CLK 9 I FSIRX-A Input Clock
LINA_RX 10 I LIN-A Receive
SPIA_POCI 11 I/O SPI-A Peripheral Out, Controller In (POCI)
SCIC_RX 15 I SCI-C Receive Data
GPIO68 0, 4, 8, 12 72 I/O General-Purpose Input Output 68
EPWM7_A 1 O ePWM-7 Output A
EPWM3_A 2 O ePWM-3 Output A
MCANA_RX 3 I CAN/CAN FD Receive
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SCIB_TX 6 O SCI-B Transmit Data
PMBUSA_CTL 7 I/O PMBus-A Control Signal - Target Input/Controller Output
FSIRXA_D0 9 I FSIRX-A Primary Data Input
LINA_TX 10 O LIN-A Transmit
SPIA_CLK 11 I/O SPI-A Clock
SCIC_TX 15 O SCI-C Transmit Data
GPIO69 0, 4, 8, 12 73 I/O General-Purpose Input Output 69
EPWM6_B 1 O ePWM-6 Output B
EPWM3_B 2 O ePWM-3 Output B
OUTPUTXBAR7 3 O Output X-BAR Output 7
EQEP1_B 5 I eQEP-1 Input B
SCIB_RX 6 I SCI-B Receive Data
SPIA_PTE 7 I/O SPI-A Peripheral Transmit Enable (PTE)
FSIRXA_D1 9 I FSIRX-A Optional Additional Data Input
LINA_RX 10 I LIN-A Receive
EQEP2_A 11 I eQEP-2 Input A
SPIA_PICO 13 I/O SPI-A Peripheral In, Controller Out (PICO)
EQEP3_INDEX 15 I/O eQEP-3 Index
GPIO70 0, 4, 8, 12 74 I/O General-Purpose Input Output 70
I2CA_SCL 1 I/OD I2C-A Open-Drain Bidirectional Clock
SPIB_PTE 3 I/O SPI-B Peripheral Transmit Enable (PTE)
OUTPUTXBAR4 5 O Output X-BAR Output 4
LINA_RX 6 I LIN-A Receive
FSIRXA_CLK 9 I FSIRX-A Input Clock
MCANA_RX 10 I CAN/CAN FD Receive
EQEP2_B 11 I eQEP-2 Input B
ADCSOCAO 13 O ADC Start of Conversion A for External ADC
EQEP3_A 15 I eQEP-3 Input A
GPIO71 0, 4, 8, 12 83 I/O General-Purpose Input Output 71
SPIA_PICO 1 I/O SPI-A Peripheral In, Controller Out (PICO)
EPWM4_B 2 O ePWM-4 Output B
OUTPUTXBAR7 3 O Output X-BAR Output 7
EPWM9_A 5 O ePWM-9 Output A
SCIA_TX 6 O SCI-A Transmit Data
EQEP1_STROBE 9 I/O eQEP-1 Strobe
PMBUSA_SCL 10 I/OD PMBus-A Open-Drain Bidirectional Clock
XCLKOUT 11 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
EQEP2_INDEX 13 I/O eQEP-2 Index
SPIB_POCI 14 I/O SPI-B Peripheral Out, Controller In (POCI)
EQEP3_STROBE 15 I/O eQEP-3 Strobe
GPIO72 0, 4, 8, 12 84 I/O General-Purpose Input Output 72
SPIA_POCI 1 I/O SPI-A Peripheral Out, Controller In (POCI)
EPWM5_A 2 O ePWM-5 Output A
OUTPUTXBAR8 3 O Output X-BAR Output 8
EPWM9_B 5 O ePWM-9 Output B
SCIA_RX 6 I SCI-A Receive Data
EQEP1_INDEX 9 I/O eQEP-1 Index
PMBUSA_SDA 10 I/OD PMBus-A Open-Drain Bidirectional Data
MCANA_TX 11 O CAN/CAN FD Transmit
EPWM6_A 14 O ePWM-6 Output A
EQEP3_B 15 I eQEP-3 Input B
GPIO73 0, 4, 8, 12 85 I/O General-Purpose Input Output 73
OUTPUTXBAR1 1 O Output X-BAR Output 1
EPWM5_B 2 O ePWM-5 Output B
SPIA_PTE 3 I/O SPI-A Peripheral Transmit Enable (PTE)
EPWM8_A 5 O ePWM-8 Output A
SPIB_PICO 6 I/O SPI-B Peripheral In, Controller Out (PICO)
LINA_TX 9 O LIN-A Transmit
PMBUSA_SCL 10 I/OD PMBus-A Open-Drain Bidirectional Clock
SCIA_TX 11 O SCI-A Transmit Data
ERRORSTS 13 O Error Status Output. This signal requires an external pulldown.
EPWM9_A 14 O ePWM-9 Output A
GPIO74 0, 4, 8, 12 86 I/O General-Purpose Input Output 74
EPWM2_B 1 O ePWM-2 Output B
ADCSOCAO 3 O ADC Start of Conversion A for External ADC
MCANA_TX 5 O CAN/CAN FD Transmit
SPIA_POCI 6 I/O SPI-A Peripheral Out, Controller In (POCI)
EQEP1_B 11 I eQEP-1 Input B
GPIO75 0, 4, 8, 12 111 I/O General-Purpose Input Output 75
EPWM1_B 1 O ePWM-1 Output B
LINA_RX 3 I LIN-A Receive
EPWM6_A 5 O ePWM-6 Output A
SPIA_CLK 6 I/O SPI-A Clock
EQEP1_STROBE 11 I/O eQEP-1 Strobe
SCIC_RX 14 I SCI-C Receive Data
GPIO76 0, 4, 8, 12 112 I/O General-Purpose Input Output 76
EPWM4_A 1 O ePWM-4 Output A
OUTPUTXBAR2 5 O Output X-BAR Output 2
SPIA_PTE 6 I/O SPI-A Peripheral Transmit Enable (PTE)
MCANA_RX 10 I CAN/CAN FD Receive
EQEP1_INDEX 11 I/O eQEP-1 Index
GPIO77 0, 4, 8, 12 113 I/O General-Purpose Input Output 77
EPWM1_A 1 O ePWM-1 Output A
OUTPUTXBAR3 5 O Output X-BAR Output 3
SPIA_PICO 6 I/O SPI-A Peripheral In, Controller Out (PICO)
MCANA_TX 10 O CAN/CAN FD Transmit
EQEP1_A 11 I eQEP-1 Input A
SCIC_TX 14 O SCI-C Transmit Data
GPIO78 0, 4, 8, 12 114 I/O General-Purpose Input Output 78
EPWM8_A 2 O ePWM-8 Output A
EPWM3_A 3 O ePWM-3 Output A
OUTPUTXBAR1 5 O Output X-BAR Output 1
EPWM2_B 6 O ePWM-2 Output B
FSITXA_CLK 9 O FSITX-A Output Clock
GPIO79 0, 4, 8, 12 115 I/O General-Purpose Input Output 79
EPWM8_B 2 O ePWM-8 Output B
EPWM3_B 3 O ePWM-3 Output B
MCANA_RX 5 I CAN/CAN FD Receive
EPWM2_A 6 O ePWM-2 Output A
I2CA_SDA 7 I/OD I2C-A Open-Drain Bidirectional Data
PMBUSA_SCL 9 I/OD PMBus-A Open-Drain Bidirectional Clock
GPIO80 0, 4, 8, 12 116 I/O General-Purpose Input Output 80
EPWM1_A 1 O ePWM-1 Output A
OUTPUTXBAR7 3 O Output X-BAR Output 7
SCIA_RX 5 I SCI-A Receive Data
I2CB_SDA 6 I/OD I2C-B Open-Drain Bidirectional Data
SPIA_PTE 7 I/O SPI-A Peripheral Transmit Enable (PTE)
FSITXA_D0 9 O FSITX-A Primary Data Output
MCANA_RX 10 I CAN/CAN FD Receive
CLB_OUTPUTXBAR8 11 O CLB Output X-BAR Output 8
EQEP1_INDEX 13 I/O eQEP-1 Index
EPWM3_A 15 O ePWM-3 Output A
GPIO81 0, 4, 8, 12 117 I/O General-Purpose Input Output 81
EPWM1_B 1 O ePWM-1 Output B
OUTPUTXBAR6 2 O Output X-BAR Output 6
SCIC_RX 3 I SCI-C Receive Data
SPIB_CLK 5 I/O SPI-B Clock
I2CB_SCL 6 I/OD I2C-B Open-Drain Bidirectional Clock
FSITXA_D1 9 O FSITX-A Optional Additional Data Output
MCANA_TX 10 O CAN/CAN FD Transmit
EQEP3_INDEX 11 I/O eQEP-3 Index
GPIO211 0, 4, 8, 12 43 I/O General-Purpose Input Output 211
EPWM10_A 1 O ePWM-10 Output A
EQEP3_A 5 I eQEP-3 Input A
GPIO212 0, 4, 8, 12 44 I/O General-Purpose Input Output 212
EPWM10_B 1 O ePWM-10 Output B
EQEP3_B 5 I eQEP-3 Input B
GPIO213 0, 4, 8, 12 45 I/O General-Purpose Input Output 213
EPWM11_A 1 O ePWM-11 Output A
EQEP3_STROBE 5 I/O eQEP-3 Strobe
GPIO214 0, 4, 8, 12 46 I/O General-Purpose Input Output 214
EPWM11_B 1 O ePWM-11 Output B
EQEP3_INDEX 5 I/O eQEP-3 Index
GPIO215 0, 4, 8, 12 47 I/O General-Purpose Input Output 215
EPWM7_B 1 O ePWM-7 Output B
EQEP2_A 5 I eQEP-2 Input A
GPIO224 0, 4, 8, 12 21 17 13 9 7 I/O General-Purpose Input Output 224 This pin also has analog functions which are described in the ANALOG section of this table.
EPWM11_B 1 O ePWM-11 Output B
OUTPUTXBAR3 5 O Output X-BAR Output 3
SPIA_PICO 6 I/O SPI-A Peripheral In, Controller Out (PICO)
EPWM1_A 9 O ePWM-1 Output A
MCANA_TX 10 O CAN/CAN FD Transmit
EQEP1_A 11 I eQEP-1 Input A
ADCE_EXTMUXSEL3 13 O ADCE external mux selection pin for position 3
SCIC_TX 14 O SCI-C Transmit Data
GPIO226 0, 4, 8, 12 19 15 11 7 I/O General-Purpose Input Output 226 This pin also has analog functions which are described in the ANALOG section of this table.
EPWM10_B 1 O ePWM-10 Output B
LINA_RX 3 I LIN-A Receive
EPWM6_A 5 O ePWM-6 Output A
SPIA_CLK 6 I/O SPI-A Clock
EPWM1_B 9 O ePWM-1 Output B
EQEP1_STROBE 11 I/O eQEP-1 Strobe
ADCE_EXTMUXSEL1 13 O ADCE external mux selection pin for position 1
SCIC_RX 14 I SCI-C Receive Data
GPIO227 0, 4, 8, 12 48 38 28 24 22 I/O General-Purpose Input Output 227 This pin also has analog functions which are described in the ANALOG section of this table.
I2CB_SCL 1 I/OD I2C-B Open-Drain Bidirectional Clock
EPWM3_A 3 O ePWM-3 Output A
OUTPUTXBAR1 5 O Output X-BAR Output 1
EPWM2_B 6 O ePWM-2 Output B
GPIO228 0, 4, 8, 12 18 14 10 6 I/O General-Purpose Input Output 228 This pin also has analog functions which are described in the ANALOG section of this table.
EPWM10_A 1 O ePWM-10 Output A
ADCSOCAO 3 O ADC Start of Conversion A for External ADC
MCANA_TX 5 O CAN/CAN FD Transmit
SPIA_POCI 6 I/O SPI-A Peripheral Out, Controller In (POCI)
EPWM2_B 9 O ePWM-2 Output B
EQEP1_B 11 I eQEP-1 Input B
ADCE_EXTMUXSEL0 13 O ADCE external mux selection pin for position 0
GPIO230 0, 4, 8, 12 50 40 29 25 23 I/O General-Purpose Input Output 230 This pin also has analog functions which are described in the ANALOG section of this table.
I2CB_SDA 1 I/OD I2C-B Open-Drain Bidirectional Data
EPWM3_B 3 O ePWM-3 Output B
MCANA_RX 5 I CAN/CAN FD Receive
EPWM2_A 6 O ePWM-2 Output A
I2CA_SDA 7 I/OD I2C-A Open-Drain Bidirectional Data
PMBUSA_SCL 9 I/OD PMBus-A Open-Drain Bidirectional Clock
GPIO242 0, 4, 8, 12 20 16 12 8 6 I/O General-Purpose Input Output 242 This pin also has analog functions which are described in the ANALOG section of this table.
EPWM11_A 1 O ePWM-11 Output A
OUTPUTXBAR2 5 O Output X-BAR Output 2
SPIA_PTE 6 I/O SPI-A Peripheral Transmit Enable (PTE)
EPWM4_A 9 O ePWM-4 Output A
MCANA_RX 10 I CAN/CAN FD Receive
EQEP1_INDEX 11 I/O eQEP-1 Index
ADCE_EXTMUXSEL2 13 O ADCE external mux selection pin for position 2
GPIO247 0, 4, 8, 12 42 I/O General-Purpose Input Output 247 This pin also has analog functions which are described in the ANALOG section of this table.
EPWM12_B 1 O ePWM-12 Output B
GPIO253 0, 4, 8, 12 41 I/O General-Purpose Input Output 253
EPWM12_A 1 O ePWM-12 Output A
TEST, JTAG, AND RESET
TCK 75 60 45 36 33 I JTAG test clock with internal pullup.
TMS 77 62 47 38 35 I/O JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. This device does not have a TRSTn pin. An external pullup resistor (recommended 2.2 kΩ) on the TMS pin to VDDIO should be placed on the board to keep JTAG in reset during normal operation.
XRSn 3 2 5 3 4 I/OD Device Reset (in) and Watchdog Reset (out). During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRSn pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor between 2.2 kΩ and 10 kΩ should be placed between XRSn and VDDIO. If a capacitor is placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. This pin is an open-drain output with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device.
POWER AND GROUND
VDD 6, 54, 90, 108 4, 71, 87 8, 53, 71 4, 44, 59 5, 41, 53 1.2-V Digital Logic Power Pins. TI recommends placing a decoupling capacitor near each VDD pin with a minimum total capacitance of approximately 10 µF. It is also recommended that all VDD pins be externally connected to each other when internal VREG is used.
VDDA 41 34 26 22 20 3.3-V Analog Power Pins. Place a minimum 2.2-µF decoupling capacitor on each pin.
VDDIO 5, 55, 89, 109 3, 70, 88 7, 52, 72 43, 60 40, 54 3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF decoupling capacitor on each pin.
VREGENZ 93 73 56 46 42 I Internal voltage regulator enable with internal pulldown. Tie low to VSS to enable internal VREG. Tie high to VDDIO to use an external supply.
VSS 7, 53, 92, 107 5, 45, 72, 86 9, 30, 55, 70 5, 26, 45, 58 PAD Digital Ground
VSSA 40 33 25 21 19 Analog Ground
(1) On the 128-PDT package, VREFLO is assigned to pins 33 and 34; these pins should be tied together at the PCB level. On the 100-PZ package, VREFLO is assigned to pins 26 and 27; these pins should be tied together at the PCB level.
(2) On the 128-PDT package, VREFHI is assigned to pins 31 and 32; these pins should be tied together at the PCB level. On the 100-PZ package, VREFHI is assigned to pins 24 and 25; these pins should be tied together at the PCB level.