SPRSP85A April   2024  – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption - VREG Enable - Internal Supply
      2. 6.5.2 System Current Consumption - VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Reducing Current Consumption
        1. 6.5.4.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Special Considerations for 5V Fail-Safe Pins
    8. 6.8  Thermal Resistance Characteristics for PDT Package
    9. 6.9  Thermal Resistance Characteristics for PZ Package
    10. 6.10 Thermal Resistance Characteristics for PNA Package
    11. 6.11 Thermal Resistance Characteristics for PM Package
    12. 6.12 Thermal Resistance Characteristics for RSH Package
    13. 6.13 Thermal Design Considerations
    14. 6.14 System
      1. 6.14.1  Power Management Module (PMM)
        1. 6.14.1.1 Introduction
        2. 6.14.1.2 Overview
          1. 6.14.1.2.1 Power Rail Monitors
            1. 6.14.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.14.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.14.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.14.1.2.2 External Supervisor Usage
          3. 6.14.1.2.3 Delay Blocks
          4. 6.14.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.14.1.2.5 VREGENZ
        3. 6.14.1.3 External Components
          1. 6.14.1.3.1 Decoupling Capacitors
            1. 6.14.1.3.1.1 VDDIO Decoupling
            2. 6.14.1.3.1.2 VDD Decoupling
        4. 6.14.1.4 Power Sequencing
          1. 6.14.1.4.1 Supply Pins Ganging
          2. 6.14.1.4.2 Signal Pins Power Sequence
          3. 6.14.1.4.3 Supply Pins Power Sequence
            1. 6.14.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.14.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.14.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.14.1.4.3.4 Supply Slew Rate
        5. 6.14.1.5 Power Management Module Electrical Data and Timing
          1. 6.14.1.5.1 Power Management Module Operating Conditions
          2. 6.14.1.5.2 Power Management Module Characteristics
      2. 6.14.2  Reset Timing
        1. 6.14.2.1 Reset Sources
        2. 6.14.2.2 Reset Electrical Data and Timing
          1. 6.14.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.14.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.14.2.2.3 Reset Timing Diagrams
      3. 6.14.3  Clock Specifications
        1. 6.14.3.1 Clock Sources
        2. 6.14.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.14.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.14.3.2.1.1 Input Clock Frequency
            2. 6.14.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.14.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.14.3.2.1.4 X1 Timing Requirements
            5. 6.14.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.14.3.2.1.6 APLL Characteristics
            7. 6.14.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.14.3.2.1.8 Internal Clock Frequencies
        3. 6.14.3.3 Input Clocks and PLLs
        4. 6.14.3.4 XTAL Oscillator
          1. 6.14.3.4.1 Introduction
          2. 6.14.3.4.2 Overview
            1. 6.14.3.4.2.1 Electrical Oscillator
              1. 6.14.3.4.2.1.1 Modes of Operation
                1. 6.14.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.14.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.14.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.14.3.4.2.2 Quartz Crystal
            3. 6.14.3.4.2.3 GPIO Modes of Operation
          3. 6.14.3.4.3 Functional Operation
            1. 6.14.3.4.3.1 ESR – Effective Series Resistance
            2. 6.14.3.4.3.2 Rneg – Negative Resistance
            3. 6.14.3.4.3.3 Start-up Time
              1. 6.14.3.4.3.3.1 X1/X2 Precondition
            4. 6.14.3.4.3.4 DL – Drive Level
          4. 6.14.3.4.4 How to Choose a Crystal
          5. 6.14.3.4.5 Testing
          6. 6.14.3.4.6 Common Problems and Debug Tips
          7. 6.14.3.4.7 Crystal Oscillator Specifications
            1. 6.14.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.14.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.14.3.4.7.3 Crystal Oscillator Parameters
        5. 6.14.3.5 Internal Oscillators
          1. 6.14.3.5.1 INTOSC Characteristics
      4. 6.14.4  Flash Parameters
        1. 6.14.4.1 Flash Parameters 
      5. 6.14.5  RAM Specifications
      6. 6.14.6  ROM Specifications
      7. 6.14.7  Emulation/JTAG
        1. 6.14.7.1 JTAG Electrical Data and Timing
          1. 6.14.7.1.1 JTAG Timing Requirements
          2. 6.14.7.1.2 JTAG Switching Characteristics
          3. 6.14.7.1.3 JTAG Timing Diagram
        2. 6.14.7.2 cJTAG Electrical Data and Timing
          1. 6.14.7.2.1 cJTAG Timing Requirements
          2. 6.14.7.2.2 cJTAG Switching Characteristics
          3. 6.14.7.2.3 cJTAG Timing Diagram
      8. 6.14.8  GPIO Electrical Data and Timing
        1. 6.14.8.1 GPIO – Output Timing
          1. 6.14.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.14.8.1.2 General-Purpose Output Timing Diagram
        2. 6.14.8.2 GPIO – Input Timing
          1. 6.14.8.2.1 General-Purpose Input Timing Requirements
          2. 6.14.8.2.2 Sampling Mode
        3. 6.14.8.3 Sampling Window Width for Input Signals
      9. 6.14.9  Interrupts
        1. 6.14.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.14.9.1.1 External Interrupt Timing Requirements
          2. 6.14.9.1.2 External Interrupt Switching Characteristics
          3. 6.14.9.1.3 External Interrupt Timing
      10. 6.14.10 Low-Power Modes
        1. 6.14.10.1 Clock-Gating Low-Power Modes
        2. 6.14.10.2 Low-Power Mode Wake-up Timing
          1. 6.14.10.2.1 IDLE Mode Timing Requirements
          2. 6.14.10.2.2 IDLE Mode Switching Characteristics
          3. 6.14.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.14.10.2.4 STANDBY Mode Timing Requirements
          5. 6.14.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.14.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.14.10.2.7 HALT Mode Timing Requirements
          8. 6.14.10.2.8 HALT Mode Switching Characteristics
          9. 6.14.10.2.9 HALT Entry and Exit Timing Diagram
    15. 6.15 Analog Peripherals
      1. 6.15.1 Block Diagram
      2. 6.15.2 Analog Pins and Internal Connections
      3. 6.15.3 Analog Signal Descriptions
      4. 6.15.4 Analog-to-Digital Converter (ADC)
        1. 6.15.4.1 ADC Configurability
          1. 6.15.4.1.1 Signal Mode
        2. 6.15.4.2 ADC Electrical Data and Timing
          1. 6.15.4.2.1 ADC Operating Conditions
          2. 6.15.4.2.2 ADC Characteristics
          3. 6.15.4.2.3 ADC INL and DNL
          4. 6.15.4.2.4 ADC Performance Per Pin
          5. 6.15.4.2.5 ADC Input Model
          6. 6.15.4.2.6 ADC Timing Diagrams
      5. 6.15.5 Temperature Sensor
        1. 6.15.5.1 Temperature Sensor Electrical Data and Timing
          1. 6.15.5.1.1 Temperature Sensor Characteristics
      6. 6.15.6 Comparator Subsystem (CMPSS)
        1. 6.15.6.1 CMPx_DACL
        2. 6.15.6.2 CMPSS Connectivity Diagram
        3. 6.15.6.3 Block Diagram
        4. 6.15.6.4 CMPSS Electrical Data and Timing
          1. 6.15.6.4.1 CMPSS Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.15.6.4.2 CMPSS DAC Static Electrical Characteristics
          4. 6.15.6.4.3 CMPSS Illustrative Graphs
          5. 6.15.6.4.4 Buffered Output from CMPx_DACL Operating Conditions
          6. 6.15.6.4.5 Buffered Output from CMPx_DACL Electrical Characteristics
      7. 6.15.7 Buffered Digital-to-Analog Converter (DAC)
        1. 6.15.7.1 Buffered DAC Electrical Data and Timing
          1. 6.15.7.1.1 Buffered DAC Operating Conditions
          2. 6.15.7.1.2 Buffered DAC Electrical Characteristics
      8. 6.15.8 Programmable Gain Amplifier (PGA)
        1. 6.15.8.1 PGA Electrical Data and Timing
          1. 6.15.8.1.1 PGA Operating Conditions
          2. 6.15.8.1.2 PGA Characteristics
    16. 6.16 Control Peripherals
      1. 6.16.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.16.1.1 Control Peripherals Synchronization
        2. 6.16.1.2 ePWM Electrical Data and Timing
          1. 6.16.1.2.1 ePWM Timing Requirements
          2. 6.16.1.2.2 ePWM Switching Characteristics
          3. 6.16.1.2.3 Trip-Zone Input Timing
            1. 6.16.1.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.16.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.16.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.16.2.1 HRPWM Electrical Data and Timing
          1. 6.16.2.1.1 High-Resolution PWM Characteristics
      3. 6.16.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.16.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.16.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.16.4 Enhanced Capture (eCAP)
        1. 6.16.4.1 eCAP Block Diagram
        2. 6.16.4.2 eCAP Synchronization
        3. 6.16.4.3 eCAP Electrical Data and Timing
          1. 6.16.4.3.1 eCAP Timing Requirements
          2. 6.16.4.3.2 eCAP Switching Characteristics
      5. 6.16.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.16.5.1 eQEP Electrical Data and Timing
          1. 6.16.5.1.1 eQEP Timing Requirements
          2. 6.16.5.1.2 eQEP Switching Characteristics
    17. 6.17 Communications Peripherals
      1. 6.17.1 Modular Controller Area Network (MCAN)
      2. 6.17.2 Inter-Integrated Circuit (I2C)
        1. 6.17.2.1 I2C Electrical Data and Timing
          1. 6.17.2.1.1 I2C Timing Requirements
          2. 6.17.2.1.2 I2C Switching Characteristics
          3. 6.17.2.1.3 I2C Timing Diagram
      3. 6.17.3 Power Management Bus (PMBus) Interface
        1. 6.17.3.1 PMBus Electrical Data and Timing
          1. 6.17.3.1.1 PMBus Electrical Characteristics
          2. 6.17.3.1.2 PMBus Fast Plus Mode Switching Characteristics
          3. 6.17.3.1.3 PMBus Fast Mode Switching Characteristics
          4. 6.17.3.1.4 PMBus Standard Mode Switching Characteristics
      4. 6.17.4 Serial Communications Interface (SCI)
      5. 6.17.5 Serial Peripheral Interface (SPI)
        1. 6.17.5.1 SPI Controller Mode Timings
          1. 6.17.5.1.1 SPI Controller Mode Timing Requirements
          2. 6.17.5.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0
          3. 6.17.5.1.3 SPI Controller Mode Switching Characteristics - Clock Phase 1
          4. 6.17.5.1.4 SPI Controller Mode Timing Diagrams
        2. 6.17.5.2 SPI Peripheral Mode Timings
          1. 6.17.5.2.1 SPI Peripheral Mode Timing Requirements
          2. 6.17.5.2.2 SPI Peripheral Mode Switching Characteristics
          3. 6.17.5.2.3 SPI Peripheral Mode Timing Diagrams
      6. 6.17.6 Local Interconnect Network (LIN)
      7. 6.17.7 Fast Serial Interface (FSI)
        1. 6.17.7.1 FSI Transmitter
          1. 6.17.7.1.1 FSITX Electrical Data and Timing
            1. 6.17.7.1.1.1 FSITX Switching Characteristics
            2. 6.17.7.1.1.2 FSITX Timings
        2. 6.17.7.2 FSI Receiver
          1. 6.17.7.2.1 FSIRX Electrical Data and Timing
            1. 6.17.7.2.1.1 FSIRX Timing Requirements
            2. 6.17.7.2.1.2 FSIRX Switching Characteristics
            3. 6.17.7.2.1.3 FSIRX Timings
        3. 6.17.7.3 FSI SPI Compatibility Mode
          1. 6.17.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.17.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.17.7.3.1.2 FSITX SPI Signaling Mode Timings
      8. 6.17.8 Universal Serial Bus (USB)
        1. 6.17.8.1 USB Electrical Data and Timing
          1. 6.17.8.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.17.8.1.2 USB Output Ports DP and DM Switching Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
        3. 7.3.1.3 Global Shared RAM (GSx RAM)
        4. 7.3.1.4 Message RAM
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit (FPU)
      2. 7.6.2 Trigonometric Math Unit (TMU)
      3. 7.6.3 VCRC Unit
    7. 7.7  Control Law Accelerator (CLA)
    8. 7.8  Embedded Real-Time Analysis and Diagnostic (ERAD)
    9. 7.9  Direct Memory Access (DMA)
    10. 7.10 Device Boot Modes
      1. 7.10.1 Device Boot Configurations
        1. 7.10.1.1 Configuring Boot Mode Pins
        2. 7.10.1.2 Configuring Boot Mode Table Options
      2. 7.10.2 GPIO Assignments
    11. 7.11 Security
      1. 7.11.1 Securing the Boundary of the Chip
        1. 7.11.1.1 JTAGLOCK
        2. 7.11.1.2 Zero-pin Boot
      2. 7.11.2 Dual-Zone Security
      3. 7.11.3 Disclaimer
    12. 7.12 Watchdog
    13. 7.13 C28x Timers
    14. 7.14 Dual-Clock Comparator (DCC)
      1. 7.14.1 Features
      2. 7.14.2 Mapping of DCCx Clock Source Inputs
    15. 7.15 Configurable Logic Block (CLB)
  9. 8 Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2.     TAPE AND REEL INFORMATION
    3.     TRAY

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PNA|80
  • PM|64
  • RSH|56
  • PZ|100
  • PDT|128
Thermal pad, mechanical data (Package|Pins)

5.3.1 Analog Signals

Table 5-2 Analog Signals
SIGNAL NAMEPIN TYPEDESCRIPTION128 PDT100 PZ80 PNA64 PM56 RSH
A0IADC-A Input 03023191513
A1IADC-A Input 12922181412
A2IADC-A Input 221171397
A3IADC-A Input 320181286
A4IADC-A Input 44236272321
A5IADC-A Input 52835171311
A6IADC-A Input 61814106
A7IADC-A Input 73731231917
A8IADC-A Input 83937242018
A9IADC-A Input 94838282422
A10IADC-A Input 105040292523
A11IADC-A Input 112720161210
A12IADC-A Input 123528221816
A13IADC-A Input 1333, 3426, 27211715
A14IADC-A Input 14261915119
A15IADC-A Input 152214108
A16IADC-A Input 1621423
A17IADC-A Input 176048332724
A18IADC-A Input 186149342825
A19IADC-A Input 196250352926
A20IADC-A Input 206351363027
A24IADC-A Input 246452373128
A25IADC-A Input 256755403431
A26IADC-A Input 2624
A27IADC-A Input 2744
A28IADC-A Input 2847
AIO208IAnalog Pin Used For Digital Input 20823
AIO209IAnalog Pin Used For Digital Input 20924
AIO210IAnalog Pin Used For Digital Input 21025
AIO225IAnalog Pin Used For Digital Input 2254236272321
AIO226IAnalog Pin Used For Digital Input 22643
AIO227IAnalog Pin Used For Digital Input 22744
AIO228IAnalog Pin Used For Digital Input 22845
AIO229IAnalog Pin Used For Digital Input 22918
AIO231IAnalog Pin Used For Digital Input 2313023191513
AIO232IAnalog Pin Used For Digital Input 2322922181412
AIO233IAnalog Pin Used For Digital Input 2332214108
AIO234IAnalog Pin Used For Digital Input 23431, 3224, 25201614
AIO235IAnalog Pin Used For Digital Input 23533, 3426, 27211715
AIO237IAnalog Pin Used For Digital Input 2372720161210
AIO238IAnalog Pin Used For Digital Input 2383528221816
AIO239IAnalog Pin Used For Digital Input 239261915119
AIO240IAnalog Pin Used For Digital Input 24037
AIO241IAnalog Pin Used For Digital Input 24139242018
AIO242IAnalog Pin Used For Digital Input 24246
AIO243IAnalog Pin Used For Digital Input 24347
AIO244IAnalog Pin Used For Digital Input 2442821171311
AIO245IAnalog Pin Used For Digital Input 2453731231917
AIO248IAnalog Pin Used For Digital Input 2483529221816
AIO249IAnalog Pin Used For Digital Input 24935
AIO251IAnalog Pin Used For Digital Input 2513630
AIO252IAnalog Pin Used For Digital Input 2523832
AIO253IAnalog Pin Used For Digital Input 25323
B0IADC-B Input 03941242018
B1IADC-B Input 15040292523
B2IADC-B Input 21915117
B3IADC-B Input 320161286
B4IADC-B Input 44939282422
B5IADC-B Input 53832
B6IADC-B Input 621171397
B7IADC-B Input 72922181412
B8IADC-B Input 84236272321
B9IADC-B Input 9221814108
B10IADC-B Input 102720161210
B11IADC-B Input 113630
B12IADC-B Input 122821171311
B13IADC-B Input 1333, 3426, 27211715
B14IADC-B Input 14261915119
B15IADC-B Input 153023191513
B16IADC-B Input 1621423
B17IADC-B Input 176048332724
B18IADC-B Input 186149342825
B19IADC-B Input 196250352926
B20IADC-B Input 206351363027
B24IADC-B Input 246553383229
B25IADC-B Input 256856413532
B26IADC-B Input 2625
B27IADC-B Input 2745
B30IADC-B Input 303731231917
C0IADC-C Input 02720161210
C1IADC-C Input 13529221816
C2IADC-C Input 22821171311
C3IADC-C Input 33731231917
C4IADC-C Input 4261915119
C5IADC-C Input 520281286
C6IADC-C Input 61915117
C7IADC-C Input 7221814108
C8IADC-C Input 84939282422
C9IADC-C Input 921171397
C10IADC-C Input 105040292523
C11IADC-C Input 113941242018
C13IADC-C Input 1333, 3426, 27211715
C14IADC-C Input 144242272321
C15IADC-C Input 153023191513
C16IADC-C Input 1621423
C17IADC-C Input 176048332724
C18IADC-C Input 186149342825
C19IADC-C Input 196250352926
C20IADC-C Input 206351363027
C24IADC-C Input 246654393330
C25IADC-C Input 2523
C26IADC-C Input 2643
C27IADC-C Input 2746
CMP1_DACLICMPSS-1 Low DAC Output2922181412
CMP1_HN0ICMPSS-1 High Comparator Negative Input 02214108
CMP1_HN1ICMPSS-1 High Comparator Negative Input 12720161210
CMP1_HP0ICMPSS-1 High Comparator Positive Input 021171397
CMP1_HP1ICMPSS-1 High Comparator Positive Input 12720161210
CMP1_HP2ICMPSS-1 High Comparator Positive Input 21814106
CMP1_HP3ICMPSS-1 High Comparator Positive Input 32214108
CMP1_HP4ICMPSS-1 High Comparator Positive Input 42922181412
CMP1_HP5ICMPSS-1 High Comparator Positive Input 53832
CMP1_LN0ICMPSS-1 Low Comparator Negative Input 02214108
CMP1_LN1ICMPSS-1 Low Comparator Negative Input 12720161210
CMP1_LP0ICMPSS-1 Low Comparator Positive Input 021171397
CMP1_LP1ICMPSS-1 Low Comparator Positive Input 12720161210
CMP1_LP2ICMPSS-1 Low Comparator Positive Input 21814106
CMP1_LP3ICMPSS-1 Low Comparator Positive Input 32214108
CMP1_LP4ICMPSS-1 Low Comparator Positive Input 42922181412
CMP1_LP5ICMPSS-1 Low Comparator Positive Input 53832
CMP2_HN0ICMPSS-2 High Comparator Negative Input 05040292523
CMP2_HN1ICMPSS-2 High Comparator Negative Input 13528221816
CMP2_HP0ICMPSS-2 High Comparator Positive Input 04236272321
CMP2_HP1ICMPSS-2 High Comparator Positive Input 13528221816
CMP2_HP2ICMPSS-2 High Comparator Positive Input 24838282422
CMP2_HP3ICMPSS-2 High Comparator Positive Input 35040, 41292523
CMP2_HP5ICMPSS-2 High Comparator Positive Input 52835171311
CMP2_LN0ICMPSS-2 Low Comparator Negative Input 05040292523
CMP2_LN1ICMPSS-2 Low Comparator Negative Input 13528221816
CMP2_LP0ICMPSS-2 Low Comparator Positive Input 04236272321
CMP2_LP1ICMPSS-2 Low Comparator Positive Input 13528221816
CMP2_LP2ICMPSS-2 Low Comparator Positive Input 24838282422
CMP2_LP3ICMPSS-2 Low Comparator Positive Input 35040, 41292523
CMP2_LP5ICMPSS-2 Low Comparator Positive Input 52835171311
CMP3_HN0ICMPSS-3 High Comparator Negative Input 020161286
CMP3_HN1ICMPSS-3 High Comparator Negative Input 12821171311
CMP3_HP0ICMPSS-3 High Comparator Positive Input 01915117
CMP3_HP1ICMPSS-3 High Comparator Positive Input 12821171311
CMP3_HP2ICMPSS-3 High Comparator Positive Input 23023191513
CMP3_HP3ICMPSS-3 High Comparator Positive Input 320161286
CMP3_HP4ICMPSS-3 High Comparator Positive Input 4261915119
CMP3_HP5ICMPSS-3 High Comparator Positive Input 520181286
CMP3_LN0ICMPSS-3 Low Comparator Negative Input 020161286
CMP3_LN1ICMPSS-3 Low Comparator Negative Input 12821171311
CMP3_LP0ICMPSS-3 Low Comparator Positive Input 01915117
CMP3_LP1ICMPSS-3 Low Comparator Positive Input 12821171311
CMP3_LP2ICMPSS-3 Low Comparator Positive Input 23023191513
CMP3_LP3ICMPSS-3 Low Comparator Positive Input 320161286
CMP3_LP4ICMPSS-3 Low Comparator Positive Input 4261915119
CMP3_LP5ICMPSS-3 Low Comparator Positive Input 520181286
CMP4_HN0ICMPSS-4 High Comparator Negative Input 04242272321
CMP4_HN1ICMPSS-4 High Comparator Negative Input 13731231917
CMP4_HP0ICMPSS-4 High Comparator Positive Input 04939282422
CMP4_HP1ICMPSS-4 High Comparator Positive Input 13731231917
CMP4_HP2ICMPSS-4 High Comparator Positive Input 23529221816
CMP4_HP3ICMPSS-4 High Comparator Positive Input 34242272321
CMP4_HP4ICMPSS-4 High Comparator Positive Input 43937242018
CMP4_HP5ICMPSS-4 High Comparator Positive Input 53630
CMP4_LN0ICMPSS-4 Low Comparator Negative Input 04242272321
CMP4_LN1ICMPSS-4 Low Comparator Negative Input 13731231917
CMP4_LP0ICMPSS-4 Low Comparator Positive Input 04939282422
CMP4_LP1ICMPSS-4 Low Comparator Positive Input 13731231917
CMP4_LP2ICMPSS-4 Low Comparator Positive Input 23529221816
CMP4_LP3ICMPSS-4 Low Comparator Positive Input 34242272321
CMP4_LP4ICMPSS-4 Low Comparator Positive Input 43937242018
CMP4_LP5ICMPSS-4 Low Comparator Positive Input 53630
D0IADC-D Input 06452373128
D1IADC-D Input 16553383229
D2IADC-D Input 26654393330
D3IADC-D Input 36755403431
D4IADC-D Input 46856413532
D5IADC-D Input 523
D6IADC-D Input 624
D7IADC-D Input 725
D8IADC-D Input 843
D9IADC-D Input 944
D10IADC-D Input 1045
D11IADC-D Input 112922181412
D12IADC-D Input 123731231917
D13IADC-D Input 1333, 3426, 27211715
D14IADC-D Input 141814106
D15IADC-D Input 153832
D16IADC-D Input 163630
D18IADC-D Input 1846
D19IADC-D Input 1947
D20IADC-D Input 2031, 3224, 25201614
DACA_OUTOBuffered DAC-A Output.3023191513
E0IADC-E Input 06452373128
E1IADC-E Input 16553383229
E2IADC-E Input 26654393330
E3IADC-E Input 36755403431
E4IADC-E Input 46856413532
E5IADC-E Input 523
E6IADC-E Input 624
E7IADC-E Input 725
E8IADC-E Input 843
E9IADC-E Input 944
E10IADC-E Input 1045
E11IADC-E Input 113529221816
E12IADC-E Input 121915117
E13IADC-E Input 1333, 3426, 27211715
E14IADC-E Input 141814106
E15IADC-E Input 153832
E16IADC-E Input 163630
E18IADC-E Input 1846
E19IADC-E Input 1947
E20IADC-E Input 2031, 3224, 25201614
E30IADC-E Input 303731231917
PGA1_INMIPGA-1 Minus221814108
PGA1_INPIPGA-1 Plus21171397
PGA1_OUTOPGA-1 Output261915119
PGA2_INMIPGA-2 Minus2821171311
PGA2_INPIPGA-2 Plus20161286
PGA2_OUTOPGA-2 Output2720161210
PGA3_INMIPGA-3 Minus3630231917
PGA3_INPIPGA-3 Plus3529221816
PGA3_OUTOPGA-3 Output3832242018
VREFHI(1)IADC High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHI and VREFLO pins.31, 3224, 25201614
VREFLO(2)IADC Low Reference33, 3426, 27211715
(1) On the 128-PDT package, VREFHI is assigned to pins 31 and 32; these pins should be tied together at the PCB level. On the 100-PZ package, VREFHI is assigned to pins 24 and 25; these pins should be tied together at the PCB level.
(2) On the 128-PDT package, VREFLO is assigned to pins 33 and 34; these pins should be tied together at the PCB level. On the 100-PZ package, VREFLO is assigned to pins 26 and 27; these pins should be tied together at the PCB level.