SPRSP69B July   2023  – November 2023 TMS320F28P650DK , TMS320F28P659DK-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pins With Internal Pullup and Pulldown
    5. 5.5 Pin Multiplexing
      1. 5.5.1 GPIO Muxed Pins
      2. 5.5.2 USB Pin Muxing
      3. 5.5.3 High-Speed SPI Pin Muxing
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption VREG Enabled
      2. 6.5.2 System Current Consumption VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Current Consumption Graphs
      5. 6.5.5 Reducing Current Consumption
        1. 6.5.5.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics for ZEJ Package
    8. 6.8  Thermal Resistance Characteristics for PTP Package
    9. 6.9  Thermal Resistance Characteristics for NMR Package
    10. 6.10 Thermal Resistance Characteristics for PZP Package
    11. 6.11 Thermal Design Considerations
    12. 6.12 System
      1. 6.12.1  Power Management Module (PMM)
        1. 6.12.1.1 Introduction
        2. 6.12.1.2 Overview
          1. 6.12.1.2.1 Power Rail Monitors
            1. 6.12.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.12.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.12.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.12.1.2.2 External Supervisor Usage
          3. 6.12.1.2.3 Delay Blocks
          4. 6.12.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.12.1.2.5 VREGENZ
        3. 6.12.1.3 External Components
          1. 6.12.1.3.1 Decoupling Capacitors
            1. 6.12.1.3.1.1 VDDIO Decoupling
            2. 6.12.1.3.1.2 VDD Decoupling
        4. 6.12.1.4 Power Sequencing
          1. 6.12.1.4.1 Supply Pins Ganging
          2. 6.12.1.4.2 Signal Pins Power Sequence
          3. 6.12.1.4.3 Supply Pins Power Sequence
            1. 6.12.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.12.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.12.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.12.1.4.3.4 Supply Slew Rate
        5. 6.12.1.5 Power Management Module Electrical Data and Timing
          1. 6.12.1.5.1 Power Management Module Operating Conditions
          2. 6.12.1.5.2 Power Management Module Characteristics
      2. 6.12.2  Reset Timing
        1. 6.12.2.1 Reset Sources
        2. 6.12.2.2 Reset Electrical Data and Timing
          1. 6.12.2.2.1 Reset XRSn Timing Requirements
          2. 6.12.2.2.2 Reset XRSn Switching Characteristics
          3. 6.12.2.2.3 Reset Timing Diagrams
      3. 6.12.3  Clock Specifications
        1. 6.12.3.1 Clock Sources
        2. 6.12.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.12.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.12.3.2.1.1 Input Clock Frequency
            2. 6.12.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.12.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source Not a Crystal
            4. 6.12.3.2.1.4 X1 Timing Requirements
            5. 6.12.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.12.3.2.1.6 APLL Characteristics
            7. 6.12.3.2.1.7 XCLKOUT Switching Characteristics PLL Bypassed or Enabled
            8. 6.12.3.2.1.8 Internal Clock Frequencies
        3. 6.12.3.3 Input Clocks
        4. 6.12.3.4 XTAL Oscillator
          1. 6.12.3.4.1 Introduction
          2. 6.12.3.4.2 Overview
            1. 6.12.3.4.2.1 Electrical Oscillator
              1. 6.12.3.4.2.1.1 Modes of Operation
                1. 6.12.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.12.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.12.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.12.3.4.2.2 Quartz Crystal
            3. 6.12.3.4.2.3 GPIO Modes of Operation
          3. 6.12.3.4.3 Functional Operation
            1. 6.12.3.4.3.1 ESR – Effective Series Resistance
            2. 6.12.3.4.3.2 Rneg – Negative Resistance
            3. 6.12.3.4.3.3 Start-up Time
            4. 6.12.3.4.3.4 DL – Drive Level
          4. 6.12.3.4.4 How to Choose a Crystal
          5. 6.12.3.4.5 Testing
          6. 6.12.3.4.6 Common Problems and Debug Tips
          7. 6.12.3.4.7 Crystal Oscillator Specifications
            1. 6.12.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.12.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.12.3.4.7.3 Crystal Oscillator Parameters
            4. 6.12.3.4.7.4 Crystal Oscillator Electrical Characteristics
        5. 6.12.3.5 Internal Oscillators
          1. 6.12.3.5.1 INTOSC Characteristics
      4. 6.12.4  Flash Parameters
        1. 6.12.4.1 Flash Parameters 
      5. 6.12.5  RAM Specifications
      6. 6.12.6  ROM Specifications
      7. 6.12.7  Emulation/JTAG
        1. 6.12.7.1 JTAG Electrical Data and Timing
          1. 6.12.7.1.1 JTAG Timing Requirements
          2. 6.12.7.1.2 JTAG Switching Characteristics
          3. 6.12.7.1.3 JTAG Timing Diagram
        2. 6.12.7.2 cJTAG Electrical Data and Timing
          1. 6.12.7.2.1 cJTAG Timing Requirements
          2. 6.12.7.2.2 cJTAG Switching Characteristics
          3. 6.12.7.2.3 cJTAG Timing Diagram
      8. 6.12.8  GPIO Electrical Data and Timing
        1. 6.12.8.1 GPIO – Output Timing
          1. 6.12.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.12.8.1.2 General-Purpose Output Timing Diagram
        2. 6.12.8.2 GPIO – Input Timing
          1. 6.12.8.2.1 General-Purpose Input Timing Requirements
          2. 6.12.8.2.2 Sampling Mode
        3. 6.12.8.3 Sampling Window Width for Input Signals
      9. 6.12.9  Interrupts
        1. 6.12.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.12.9.1.1 External Interrupt Timing Requirements
          2. 6.12.9.1.2 External Interrupt Switching Characteristics
          3. 6.12.9.1.3 External Interrupt Timing
      10. 6.12.10 Low-Power Modes
        1. 6.12.10.1 Clock-Gating Low-Power Modes
        2. 6.12.10.2 Low-Power Mode Wake-up Timing
          1. 6.12.10.2.1 IDLE Mode Timing Requirements
          2. 6.12.10.2.2 IDLE Mode Switching Characteristics
          3. 6.12.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.12.10.2.4 STANDBY Mode Timing Requirements
          5. 6.12.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.12.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.12.10.2.7 HALT Mode Timing Requirements
          8. 6.12.10.2.8 HALT Mode Switching Characteristics
          9. 6.12.10.2.9 HALT Entry and Exit Timing Diagram
      11. 6.12.11 External Memory Interface (EMIF)
        1. 6.12.11.1 Asynchronous Memory Support
        2. 6.12.11.2 Synchronous DRAM Support
        3. 6.12.11.3 EMIF Electrical Data and Timing
          1. 6.12.11.3.1 EMIF Synchronous Memory Timing Requirements
          2. 6.12.11.3.2 EMIF Synchronous Memory Switching Characteristics
          3. 6.12.11.3.3 EMIF Synchronous Memory Timing Diagrams
          4. 6.12.11.3.4 EMIF Asynchronous Memory Timing Requirements
          5. 6.12.11.3.5 EMIF Asynchronous Memory Switching Characteristics
          6. 6.12.11.3.6 EMIF Asynchronous Memory Timing Diagrams
    13. 6.13 C28x Analog Peripherals
      1. 6.13.1 Analog Subsystem
        1. 6.13.1.1 Features
        2. 6.13.1.2 Block Diagram
      2. 6.13.2 Analog-to-Digital Converter (ADC)
        1. 6.13.2.1 ADC Configurability
          1. 6.13.2.1.1 Signal Mode
        2. 6.13.2.2 ADC Electrical Data and Timing
          1. 6.13.2.2.1  ADC Operating Conditions 12-bit Single-Ended
          2. 6.13.2.2.2  ADC Operating Conditions 12-bit Differential
          3. 6.13.2.2.3  ADC Operating Conditions 16-bit Single-Ended
          4. 6.13.2.2.4  ADC Operating Conditions 16-bit Differential
          5. 6.13.2.2.5  ADC Characteristics 12-bit Single-Ended
          6. 6.13.2.2.6  ADC Characteristics 12-bit Differential
          7. 6.13.2.2.7  ADC Characteristics 16-bit Single-Ended
          8. 6.13.2.2.8  ADC Characteristics 16-bit Differential
          9. 6.13.2.2.9  ADC Performance Per Pin
          10. 6.13.2.2.10 ADC Input Models
          11. 6.13.2.2.11 ADC Timing Diagrams
      3. 6.13.3 Temperature Sensor
        1. 6.13.3.1 Temperature Sensor Electrical Data and Timing
          1. 6.13.3.1.1 Temperature Sensor Characteristics
      4. 6.13.4 Comparator Subsystem (CMPSS)
        1. 6.13.4.1 CMPSS Connectivity Diagram
        2. 6.13.4.2 Block Diagram
        3. 6.13.4.3 CMPSS Electrical Data and Timing
          1. 6.13.4.3.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.13.4.3.2 CMPSS DAC Static Electrical Characteristics
          4. 6.13.4.3.3 CMPSS Illustrative Graphs
          5. 6.13.4.3.4 CMPSS DAC Dynamic Error
      5. 6.13.5 Buffered Digital-to-Analog Converter (DAC)
        1. 6.13.5.1 Buffered DAC Electrical Data and Timing
          1. 6.13.5.1.1 Buffered DAC Operating Conditions
          2. 6.13.5.1.2 Buffered DAC Electrical Characteristics
    14. 6.14 C28x Control Peripherals
      1. 6.14.1 Enhanced Capture (eCAP)
        1. 6.14.1.1 eCAP Block Diagram
        2. 6.14.1.2 eCAP Synchronization
        3. 6.14.1.3 eCAP Electrical Data and Timing
          1. 6.14.1.3.1 eCAP Timing Requirements
          2. 6.14.1.3.2 eCAP Switching Characteristics
      2. 6.14.2 High-Resolution Capture (HRCAP)
        1. 6.14.2.1 eCAP and HRCAP Block Diagram
        2. 6.14.2.2 HRCAP Electrical Data and Timing
          1. 6.14.2.2.1 HRCAP Switching Characteristics
          2. 6.14.2.2.2 HRCAP Figure and Graph
      3. 6.14.3 Enhanced Pulse Width Modulator (ePWM)
        1. 6.14.3.1 Control Peripherals Synchronization
        2. 6.14.3.2 ePWM Electrical Data and Timing
          1. 6.14.3.2.1 ePWM Timing Requirements
          2. 6.14.3.2.2 ePWM Switching Characteristics
          3. 6.14.3.2.3 Trip-Zone Input Timing
            1. 6.14.3.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.14.3.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      4. 6.14.4 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.14.4.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.14.4.2 ADCSOCAO or ADCSOCBO Timing Diagram
      5. 6.14.5 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.14.5.1 HRPWM Electrical Data and Timing
          1. 6.14.5.1.1 High-Resolution PWM Characteristics
      6. 6.14.6 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.14.6.1 eQEP Electrical Data and Timing
          1. 6.14.6.1.1 eQEP Timing Requirements
          2. 6.14.6.1.2 eQEP Switching Characteristics
      7. 6.14.7 Sigma-Delta Filter Module (SDFM)
        1. 6.14.7.1 SDFM Electrical Data and Timing
          1. 6.14.7.1.1 SDFM Timing Requirements When Using Asynchronous GPIO ASYNC Option
    15. 6.15 C28x Communications Peripherals
      1. 6.15.1  Controller Area Network (CAN)
      2. 6.15.2  Modular Controller Area Network (MCAN)
      3. 6.15.3  Fast Serial Interface (FSI)
        1. 6.15.3.1 FSI Transmitter
          1. 6.15.3.1.1 FSITX Electrical Data and Timing
            1. 6.15.3.1.1.1 FSITX Switching Characteristics
            2. 6.15.3.1.1.2 FSITX Timings
        2. 6.15.3.2 FSI Receiver
          1. 6.15.3.2.1 FSIRX Electrical Data and Timing
            1. 6.15.3.2.1.1 FSIRX Timing Requirements
            2. 6.15.3.2.1.2 FSIRX Switching Characteristics
            3. 6.15.3.2.1.3 FSIRX Timings
        3. 6.15.3.3 FSI SPI Compatibility Mode
          1. 6.15.3.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.15.3.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.15.3.3.1.2 FSITX SPI Signaling Mode Timings
      4. 6.15.4  Inter-Integrated Circuit (I2C)
        1. 6.15.4.1 I2C Electrical Data and Timing
          1. 6.15.4.1.1 I2C Timing Requirements
          2. 6.15.4.1.2 I2C Switching Characteristics
          3. 6.15.4.1.3 I2C Timing Diagram
      5. 6.15.5  Power Management Bus (PMBus) Interface
        1. 6.15.5.1 PMBus Electrical Data and Timing
          1. 6.15.5.1.1 PMBus Electrical Characteristics
          2. 6.15.5.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.15.5.1.3 PMBus Standard Mode Switching Characteristics
      6. 6.15.6  Serial Communications Interface (SCI)
      7. 6.15.7  Serial Peripheral Interface (SPI)
        1. 6.15.7.1 SPI Controller Mode Timings
          1. 6.15.7.1.1 SPI Controller Mode Switching Characteristics Clock Phase 0
          2. 6.15.7.1.2 SPI Controller Mode Switching Characteristics Clock Phase 1
          3. 6.15.7.1.3 SPI Controller Mode Timing Requirements
          4. 6.15.7.1.4 SPI Controller Mode Timing Diagrams
        2. 6.15.7.2 SPI Peripheral Mode Timings
          1. 6.15.7.2.1 SPI Peripheral Mode Switching Characteristics
          2. 6.15.7.2.2 SPI Peripheral Mode Timing Requirements
          3. 6.15.7.2.3 SPI Peripheral Mode Timing Diagrams
      8. 6.15.8  Local Interconnect Network (LIN)
      9. 6.15.9  EtherCAT SubordinateDevice Controller (ESC)
        1. 6.15.9.1 ESC Features
        2. 6.15.9.2 ESC Subsystem Integrated Features
        3. 6.15.9.3 EtherCAT IP Block Diagram
        4. 6.15.9.4 EtherCAT Electrical Data and Timing
          1. 6.15.9.4.1 EtherCAT Timing Requirements
          2. 6.15.9.4.2 EtherCAT Switching Characteristics
          3. 6.15.9.4.3 EtherCAT Timing Diagrams
      10. 6.15.10 Universal Serial Bus (USB)
        1. 6.15.10.1 USB Electrical Data and Timing
          1. 6.15.10.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.15.10.1.2 USB Output Ports DP and DM Switching Characteristics
      11. 6.15.11 Universal Asynchronous Receiver-Transmitter (UART)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Memory
      1. 7.3.1 C28x Memory Map
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 EMIF Chip Select Memory Map
      5. 7.3.5 Peripheral Registers Memory Map
      6. 7.3.6 Memory Types
        1. 7.3.6.1 Dedicated RAM (Mx and Dx RAM)
        2. 7.3.6.2 Local Shared RAM (LSx RAM)
        3. 7.3.6.3 Global Shared RAM (GSx RAM)
        4. 7.3.6.4 CPU Message RAM (CPU MSGRAM)
        5. 7.3.6.5 CLA Message RAM (CLA MSGRAM)
        6. 7.3.6.6 CLA - DMA Message RAM (CLA-DMA MSGRAM)
    4. 7.4 Identification
    5. 7.5 Bus Architecture – Peripheral Connectivity
    6. 7.6 Boot ROM
      1. 7.6.1 Device Boot
      2. 7.6.2 Device Boot Modes
      3. 7.6.3 Device Boot Configurations
      4. 7.6.4 GPIO Assignments
    7. 7.7 Security
      1. 7.7.1 Securing the Boundary of the Chip
        1. 7.7.1.1 JTAGLOCK
        2. 7.7.1.2 Zero-pin Boot
      2. 7.7.2 Dual-Zone Security
      3. 7.7.3 Disclaimer
    8. 7.8 Advanced Encryption Standard (AES) Accelerator
    9. 7.9 C28x (CPU1/CPU2) Subsystem
      1. 7.9.1  C28x Processor
        1. 7.9.1.1 Floating-Point Unit (FPU)
        2. 7.9.1.2 Fast Integer Division Unit
        3. 7.9.1.3 Trigonometric Math Unit (TMU)
        4. 7.9.1.4 VCRC Unit
        5. 7.9.1.5 Lockstep Compare Module (LCM)
      2. 7.9.2  Control Law Accelerator (CLA)
      3. 7.9.3  Embedded Real-Time Analysis and Diagnostic (ERAD)
      4. 7.9.4  Background CRC-32 (BGCRC)
      5. 7.9.5  Direct Memory Access (DMA)
      6. 7.9.6  Interprocessor Communication (IPC) Module
      7. 7.9.7  C28x Timers
      8. 7.9.8  Dual-Clock Comparator (DCC)
        1. 7.9.8.1 Features
        2. 7.9.8.2 Mapping of DCCx Clock Source Inputs
      9. 7.9.9  Nonmaskable Interrupt With Watchdog Timer (NMIWD)
      10. 7.9.10 Watchdog
      11. 7.9.11 Configurable Logic Block (CLB)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 Servo Drive Control Module
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Servo Drive Control Module Resources
        2. 8.3.1.2 Solar Micro Inverter
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 Solar Micro Inverter Resources
        3. 8.3.1.3 EV Charging Station Power Module
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 EV Charging Station Power Module Resources
        4. 8.3.1.4 On-Board Charger (OBC)
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 OBC Resources
        5. 8.3.1.5 High-Voltage Traction Inverter
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 High-Voltage Traction Inverter Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZP|100
  • ZEJ|256
  • PTP|176
  • NMR|169
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.13.1.2 Block Diagram

The following analog subsystem block diagrams show the connections between the different integrated analog modules to the device pins. These pins fall into two categories: analog module inputs/outputs and reference pins.

The reference pins, VREFHIA to VREFHIC and VREFLOA to VREFLOC, can be used to supply an external voltage reference to the associated ADCs. VREFHIA can also be used to supply the voltage reference to DAC A, and VREFHIB can be used to supply the voltage reference to DAC C. An internal voltage reference is available and connects to VREFHIA. To use the internal voltage reference on ADC B, ADC C or DAC C, connect VREFHIA to VREFHIB and/or VREFHIC externally.

The VDAC reference pin can be used to set an alternate range for DAC A and DAC C, and for the DACs inside the CMPSS modules (the CMPSS DACs are referenced to VDDA and VSSA by default). Using this pin as a reference prevents the channel from being used as an ADC input (but the ADC can be used to sample the VDAC voltage, if desired). The choice of reference is configurable per module for each CMPSS or buffered DAC; the selection is made using the module's configuration registers.

Some analog pins support digital functionality through muxed AIOs and AGPIOs. AIOs only support digital input functionality, while AGPIOs support full digital input and output functionality.

The following notes apply to all packages:

  • Not all analog pins are available on all devices. See Section 5 to determine which pins are available.
  • See Section 6.13.2.2 to determine the allowable voltage range for VREFHI and VREFLO.
  • An external capacitor is required on the VREFHI pins. See Section 6.13.2.2 for the specific value required.
  • For buffered DAC modules, VSSA is the low reference whether VREFHIx or VDAC is selected as the high reference.
  • For CMPSS modules, VSSA is the low reference whether VDAC or VDDA is selected as the high reference.

Note: If all ADCs are operating in internal VREF mode, then VREFHIA, VREFHIB, and VREFHIC must be manually connected externally.
GUID-20231004-SS0I-5CMT-XN33-7SW6NHGXHJLC-low.svg Figure 6-47 Analog System Block Diagram (ADC A, ADC B and ADC C)

Input connections to the CMPSS modules are selectable through a programmable input mux. Figure 6-48 shows the CMPSS input connections. Table 6-12 shows the mapping of ADC input signals to CMPSS mux inputs.

  • To configure the CMPH_POSIN input mux for CMPSSx, write to the CMPxHPMXSEL field in the CMPHPMXSEL or CMPHPMXSEL1 analog subsystem register.
  • To configure the CMPH_NEGIN input mux for CMPSSx, write to the CMPxHNMXSEL field in the CMPHNMXSEL analog subsystem register.
  • To configure the CMPL_POSIN input mux for CMPSSx, write to the CMPxLPMXSEL field in the CMPLPMXSEL or CMPLPMXSEL1 analog subsystem register.
  • To configure the CMPL_NEGIN input mux for CMPSSx, write to the CMPxLNMXSEL field in the CMPLNMXSEL analog subsystem register.

GUID-20221026-SS0I-TG5F-R6RN-M08RH4PX7NBG-low.svg Figure 6-48 CMPSS Input Connections
Table 6-12 CMPSS Input Mux Options
CMP1 CMP2 CMP3 CMP4 CMP5 CMP6 CMP7 CMP8 CMP9 CMP10 CMP11
HP0 A2 A4 B2 A14 C4 C2 A6 A8 B13 C10 C11
HP1 A0 B8 B0 B10 B4 C0 B6 A10 C13 C6 C7
HP2 A1 B9 B1 B11 B5 C1 B7 A11 A7 C8 C9
HP3 A3 A5 TS A15 TS 0.9*VREFHIA 0.9*VREFHIB 0.9*VREFHIC
HN0 A3 A5 B3 A15 C5 C3 A7 A9 A0 B8 B0
HN1 A1 A2 B7 B10 B4 C0 B6 A10 B9 C4 C13
LP0 A2 A4 B2 A14 C4 C2 A6 A8 B13 C10 C11
LP1 A0 B8 B0 B10 B4 C0 B6 A10 C13 C6 C7
LP2 A1 B9 B1 B11 B5 C1 B7 A11 A5 C8 C9
LP3 B3 C5 C3 A7 A9 0.9*VREFHIA 0.9*VREFHIB 0.9*VREFHIC
LN0 A3 A5 B3 A15 C5 C3 A7 A9 A0 B8 B0
LN1 A1 A2 B7 B10 B4 C0 B6 A10 B9 C4 C13
Table 6-13 Analog Signal Descriptions
Signal Name Description
ADCINAx, Ax ADC A Input
ADCINBx, Bx ADC B Input
ADCINCx, Cx ADC C Input
CMPH_POSIN Comparator subsystem high comparator positive input
CMPH_NEGIN Comparator subsystem high comparator negative input
CMPL_POSIN Comparator subsystem low comparator positive input
CMPL_NEGIN Comparator subsystem low comparator negative input
DACOUTx Buffered DAC Output
TEMP SENSOR, TS Internal temperature sensor
VDAC Optional external reference voltage for on-chip DACs. There is a 100-pF capacitor to VSSA on this pin whether used for ADC input or DAC reference that cannot be disabled. If this pin is being used as a reference for the on-chip DACs, place at least a 1-µF capacitor on this pin.
Table 6-14 Reference Summary
Module Reference Option Configured Where? Register Driverlib Function Notes
ADC External or Internal Analog Subsystem AnalogSubsysRegs.ANAREFCTL.bit.ANAREFxSEL ASysCtl_setAnalogReferenceInternal, ASysCtl_setAnalogReferenceExternal Internal reference only connected to ADCA. For ADCB/ADC, VREFHI pins must be externally connected to VREFHIA.
Internal Reference 2.5V or 3.3V Analog Subsystem AnalogSubsysRegs.ANAREFCTL.bit.ANAREFx2P5SEL ASysCtl_setAnalogReference2P5, ASysCtl_setAnalogReference1P65
Buffered DAC VREFHI or VDAC DAC Module DacxRegs. DACCTL.bit.DACREFSEL DAC_setReferenceVoltage
External or Internal Analog Subsystem AnalogSubsysRegs.ANAREFCTL.bit.ANAREFxSEL ASysCtl_setAnalogReferenceInternal, ASysCtl_setAnalogReferenceExternal Internal reference only connected to ADCA. For ADCB/ADC, VREFHI pins must be externally connected to VREFHIA.
CMPSS DACs VDDA or VDAC CMPSS Module CmpssxRegs. COMPDACHCTL.bit.SELREF CMPSS_COMPDACHCTL_SELREF
Table 6-15 Analog Internal Connections
Pin Name Pins/Package ADC DAC Comparator Subsystem (Mux) AIO Input/GPIO
256 ZEJ 176 PTP 169 NMR 100 PZP A B C High Positive High Negative Low Positive Low Negative
VREFHIA M2 37 K2 19
VREFHIB R4 53 M4 34
VREFHIC L2 35 J2 19
VREFLOA M1 33 K1 16 A18 C18
VREFLOB T4 50 N4 32 A19 C19
VREFLOC L1 32 J1 16 A20 C20
Analog Group 1 CMP1
A1 P2 42 K3 24 A1 B19 CMP1 (HPMXSEL=2) CMP1 (HNMXSEL=1) CMP1 (LPMXSEL=2) CMP1 (LNMXSEL=1) AIO228
A3 N4 40 H3 22 A3 B21 CMP1 (HPMXSEL=3) CMP1 (HNMXSEL=0) CMP1 (LNMXSEL=0) AIO230
Analog Group 2 CMP1/CMP2/CMP9
A2 N3 41 J3 23 A2 B20 CMP1 (HPMXSEL=0) CMP2 (HNMXSEL=1) CMP1 (LPMXSEL=0) CMP2 (LNMXSEL=1) AIO229
A0 P1 43 L3 25 A0,A12 B12 C12 DACA_OUT CMP1 (HPMXSEL=1) CMP9 (HNMXSEL=0) CMP1 (LPMXSEL=1) CMP9 (LNMXSEL=0) AIO227
Analog Group 3 CMP2
A4 M4 39 H2 21 A4 B22 CMP2 (HPMXSEL=0) CMP2 (LPMXSEL=0) AIO231
Analog Group 4 CMP2/CMP9/CMP10
A5 M5 38 H1 20 A5 B23 CMP2 (HPMXSEL=3) CMP2 (HNMXSEL=0) CMP9 (LPMXSEL=2) CMP2 (LNMXSEL=0) AIO232
B9 N8 67 N7 B9 C29 CMP2 (HPMXSEL=2) CMP9 (HNMXSEL=1) CMP2 (LPMXSEL=2) CMP9 (LNMXSEL=1) GPIO218
B8 P8 66 M7 B8 C28 CMP2 (HPMXSEL=1) CMP10 (HNMXSEL=0) CMP2 (LPMXSEL=1) CMP10 (LNMXSEL=0) GPIO217
Analog Group 5 CMP3
TempSensor A13 B18 CMP3 (HPMXSEL=3)
B2 R3 48 M3 30 A26 B2 CMP3 (HPMXSEL=0) CMP3 (LPMXSEL=0) AIO235
B1 T3 47 N3 29 A25 B1 DACC_OUT CMP3 (HPMXSEL=2) CMP3 (LPMXSEL=2) AIO234
Analog Group 6 CMP3/CMP1/CMP11
B3 P3 49 L4 31 A27 B3 CMP3 (HNMXSEL=0) CMP1 (LPMXSEL=3) CMP3 (LNMXSEL=0) AIO236
B0 T2 46 N2 28 B0 A24 VDAC CMP3 (HPMXSEL=1) CMP11 (HNMXSEL=0) CMP3 (LPMXSEL=1) CMP11 (LNMXSEL=0) AIO233
Analog Group 7 CMP4
A14/B14/C14 R1 44 M1 26 A14 B14 C14 CMP4 (HPMXSEL=0) CMP4 (LPMXSEL=0) AIO225
A15/B15/C15 R2 45 M2 27 A15 B15 C15 CMP4 (HPMXSEL=3) CMP4 (HNMXSEL=0) CMP4 (LNMXSEL=0) AIO226
B11 P4 51 B11 C31 CMP4 (HPMXSEL=2) CMP4 (LPMXSEL=2) AIO240
B10 R7 61 B10 C30 CMP4 (HPMXSEL=1) CMP4 (HNMXSEL=1) CMP4 (LPMXSEL=1) CMP4 (LNMXSEL=1) GPIO219
Analog Group 8 CMP5
TempSensor A13 B18 CPM5 (HPMXSEL=3)
B5 N7 65 N6 A29 B5 CMP5 (HPMXSEL=2) CMP5 (LPMXSEL=2) GPIO216
B4 P7 64 M6 A28 B4 CMP5 (HPMXSEL=1) CMP5 (HNMXSEL=1) CMP5 (LPMXSEL=1) CMP5 (LNMXSEL=1) GPIO215
Analog Group 9 CMP5/CMP2/CMP10
C5 L6 28 G6 12 B29 C5 CMP5 (HNMXSEL=0) CMP2 (LPMXSEL=3) CMP5 (LNMXSEL=0) GPIO204
C4 M6 29 H6 13 B28 C4 CMP5 (HPMXSEL=0) CMP10 (HNMXSEL=1) CMP5 (LPMXSEL=0) CMP10 (LNMXSEL=1) GPIO205
Analog Group 10 CMP6
0.9*VREFHIA B16 C16 CMP6 (HPMXSEL=3) CMP6 (LPMXSEL=3)
C0 H1 22 F1 9 B24 C0 CMP6 (HPMXSEL=1) CMP6 (HNMXSEL=1) CMP6 (LPMXSEL=1) CMP6 (LNMXSEL=1) GPIO199
C1 J1 23 G1 10 B25 C1 CMP6 (HPMXSEL=2) CMP6 (LPMXSEL=2) GPIO200
C2 L4 31 H4 15 B26 C2 CMP6 (HPMXSEL=0) CMP6 (LPMXSEL=0) AIO237
Analog Group 11 CMP6/CMP3
C3 L5 30 H5 14 B27 C3 CMP6 (HNMXSEL=0) CMP3 (LPMXSEL=3) CMP6 (LNMXSEL=0) GPIO206
Analog Group 12 CMP7
0.9*VREFHIB A16 C17 CMP7 (HPMXSEL=3) CMP7 (LPMXSEL=3)
B6 N5 55 J4 36 A30 B6 CMP7 (HPMXSEL=1) CMP7 (HNMXSEL=1) CMP7 (LPMXSEL=1) CMP7 (LNMXSEL=1) GPIO207
A6 N6 57 J5 38 A6 CMP7 (HPMXSEL=0) CMP7 (LPMXSEL=0) GPIO209
Analog Group 13 CMP7/CMP3
B7 P5 56 K4 37 A31 B7 CMP7 (HPMXSEL=2) CMP3 (HNMXSEL=1) CMP7 (LPMXSEL=2) CMP3 (LNMXSEL=1) GPIO208
Analog Group 14 CMP8
0.9*VREFHIC A17 CMP8 (HPMXSEL=3) CMP8 (LPMXSEL=3)
A8 R6 59 J6 A8 C24 CMP8 (HPMXSEL=0) CMP8 (LPMXSEL=0) GPIO211
A11 R8 63 L6 40 A11 C27 CMP8 (HPMXSEL=2) CMP8 (LPMXSEL=2) GPIO214
A10 T8 62 L5 39 A10 C26 CMP8 (HPMXSEL=1) CMP8 (HNMXSEL=1) CMP8 (LPMXSEL=1) CMP8 (LNMXSEL=1) GPIO213
Analog Group 15 CMP8/CMP5
A9 T7 60 K6 A9 C25 CMP8 (HNMXSEL=0) CMP5 (LPMXSEL=3) CMP8 (LNMXSEL=0) GPIO212
Analog Group 16 CMP9
B13 R5 B13 CMP9 (HPMXSEL=0) CMP9 (LPMXSEL=0) AIO238
Analog Group 17 CMP9/CMP4/CMP7/CMP11
A7 P6 58 K5 A7 CMP9 (HPMXSEL=2) CMP7 (HNMXSEL=0) CMP4 (LPMXSEL=3) CMP7 (LNMXSEL=0) GPIO210
C13 K1 C13 CMP9 (HPMXSEL=1) CMP11 (HNMXSEL=1) CMP9 (LPMXSEL=1) CMP11 (LNMXSEL=1) AIO239
Analog Group 18 CMP10
C8 K3 25 G3 C8 CMP10 (HPMXSEL=2) CMP10 (LPMXSEL=2) GPIO202
C6 K5 27 G5 11 B30 C6 CMP10 (HPMXSEL=1) CMP10 (LPMXSEL=1) GPIO203
C10 L3 C10 CMP10 (HPMXSEL=0) CMP10 (LPMXSEL=0) AIO241
Analog Group 19 CMP11
C9 J2 24 G2 C9 CMP11 (HPMXSEL=2) CMP11 (LPMXSEL=2) GPIO201
C11 K2 C11 CMP11 (HPMXSEL=0) CMP11 (LPMXSEL=0) AIO242
C7 K4 26 G4 B31 C7 CMP11 (HPMXSEL=1) CMP11 (LPMXSEL=1) GPIO198