SPRSP69B July   2023  – November 2023 TMS320F28P650DK , TMS320F28P659DK-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pins With Internal Pullup and Pulldown
    5. 5.5 Pin Multiplexing
      1. 5.5.1 GPIO Muxed Pins
      2. 5.5.2 USB Pin Muxing
      3. 5.5.3 High-Speed SPI Pin Muxing
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption VREG Enabled
      2. 6.5.2 System Current Consumption VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Current Consumption Graphs
      5. 6.5.5 Reducing Current Consumption
        1. 6.5.5.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics for ZEJ Package
    8. 6.8  Thermal Resistance Characteristics for PTP Package
    9. 6.9  Thermal Resistance Characteristics for NMR Package
    10. 6.10 Thermal Resistance Characteristics for PZP Package
    11. 6.11 Thermal Design Considerations
    12. 6.12 System
      1. 6.12.1  Power Management Module (PMM)
        1. 6.12.1.1 Introduction
        2. 6.12.1.2 Overview
          1. 6.12.1.2.1 Power Rail Monitors
            1. 6.12.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.12.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.12.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.12.1.2.2 External Supervisor Usage
          3. 6.12.1.2.3 Delay Blocks
          4. 6.12.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.12.1.2.5 VREGENZ
        3. 6.12.1.3 External Components
          1. 6.12.1.3.1 Decoupling Capacitors
            1. 6.12.1.3.1.1 VDDIO Decoupling
            2. 6.12.1.3.1.2 VDD Decoupling
        4. 6.12.1.4 Power Sequencing
          1. 6.12.1.4.1 Supply Pins Ganging
          2. 6.12.1.4.2 Signal Pins Power Sequence
          3. 6.12.1.4.3 Supply Pins Power Sequence
            1. 6.12.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.12.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.12.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.12.1.4.3.4 Supply Slew Rate
        5. 6.12.1.5 Power Management Module Electrical Data and Timing
          1. 6.12.1.5.1 Power Management Module Operating Conditions
          2. 6.12.1.5.2 Power Management Module Characteristics
      2. 6.12.2  Reset Timing
        1. 6.12.2.1 Reset Sources
        2. 6.12.2.2 Reset Electrical Data and Timing
          1. 6.12.2.2.1 Reset XRSn Timing Requirements
          2. 6.12.2.2.2 Reset XRSn Switching Characteristics
          3. 6.12.2.2.3 Reset Timing Diagrams
      3. 6.12.3  Clock Specifications
        1. 6.12.3.1 Clock Sources
        2. 6.12.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.12.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.12.3.2.1.1 Input Clock Frequency
            2. 6.12.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.12.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source Not a Crystal
            4. 6.12.3.2.1.4 X1 Timing Requirements
            5. 6.12.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.12.3.2.1.6 APLL Characteristics
            7. 6.12.3.2.1.7 XCLKOUT Switching Characteristics PLL Bypassed or Enabled
            8. 6.12.3.2.1.8 Internal Clock Frequencies
        3. 6.12.3.3 Input Clocks
        4. 6.12.3.4 XTAL Oscillator
          1. 6.12.3.4.1 Introduction
          2. 6.12.3.4.2 Overview
            1. 6.12.3.4.2.1 Electrical Oscillator
              1. 6.12.3.4.2.1.1 Modes of Operation
                1. 6.12.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.12.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.12.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.12.3.4.2.2 Quartz Crystal
            3. 6.12.3.4.2.3 GPIO Modes of Operation
          3. 6.12.3.4.3 Functional Operation
            1. 6.12.3.4.3.1 ESR – Effective Series Resistance
            2. 6.12.3.4.3.2 Rneg – Negative Resistance
            3. 6.12.3.4.3.3 Start-up Time
            4. 6.12.3.4.3.4 DL – Drive Level
          4. 6.12.3.4.4 How to Choose a Crystal
          5. 6.12.3.4.5 Testing
          6. 6.12.3.4.6 Common Problems and Debug Tips
          7. 6.12.3.4.7 Crystal Oscillator Specifications
            1. 6.12.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.12.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.12.3.4.7.3 Crystal Oscillator Parameters
            4. 6.12.3.4.7.4 Crystal Oscillator Electrical Characteristics
        5. 6.12.3.5 Internal Oscillators
          1. 6.12.3.5.1 INTOSC Characteristics
      4. 6.12.4  Flash Parameters
        1. 6.12.4.1 Flash Parameters 
      5. 6.12.5  RAM Specifications
      6. 6.12.6  ROM Specifications
      7. 6.12.7  Emulation/JTAG
        1. 6.12.7.1 JTAG Electrical Data and Timing
          1. 6.12.7.1.1 JTAG Timing Requirements
          2. 6.12.7.1.2 JTAG Switching Characteristics
          3. 6.12.7.1.3 JTAG Timing Diagram
        2. 6.12.7.2 cJTAG Electrical Data and Timing
          1. 6.12.7.2.1 cJTAG Timing Requirements
          2. 6.12.7.2.2 cJTAG Switching Characteristics
          3. 6.12.7.2.3 cJTAG Timing Diagram
      8. 6.12.8  GPIO Electrical Data and Timing
        1. 6.12.8.1 GPIO – Output Timing
          1. 6.12.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.12.8.1.2 General-Purpose Output Timing Diagram
        2. 6.12.8.2 GPIO – Input Timing
          1. 6.12.8.2.1 General-Purpose Input Timing Requirements
          2. 6.12.8.2.2 Sampling Mode
        3. 6.12.8.3 Sampling Window Width for Input Signals
      9. 6.12.9  Interrupts
        1. 6.12.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.12.9.1.1 External Interrupt Timing Requirements
          2. 6.12.9.1.2 External Interrupt Switching Characteristics
          3. 6.12.9.1.3 External Interrupt Timing
      10. 6.12.10 Low-Power Modes
        1. 6.12.10.1 Clock-Gating Low-Power Modes
        2. 6.12.10.2 Low-Power Mode Wake-up Timing
          1. 6.12.10.2.1 IDLE Mode Timing Requirements
          2. 6.12.10.2.2 IDLE Mode Switching Characteristics
          3. 6.12.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.12.10.2.4 STANDBY Mode Timing Requirements
          5. 6.12.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.12.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.12.10.2.7 HALT Mode Timing Requirements
          8. 6.12.10.2.8 HALT Mode Switching Characteristics
          9. 6.12.10.2.9 HALT Entry and Exit Timing Diagram
      11. 6.12.11 External Memory Interface (EMIF)
        1. 6.12.11.1 Asynchronous Memory Support
        2. 6.12.11.2 Synchronous DRAM Support
        3. 6.12.11.3 EMIF Electrical Data and Timing
          1. 6.12.11.3.1 EMIF Synchronous Memory Timing Requirements
          2. 6.12.11.3.2 EMIF Synchronous Memory Switching Characteristics
          3. 6.12.11.3.3 EMIF Synchronous Memory Timing Diagrams
          4. 6.12.11.3.4 EMIF Asynchronous Memory Timing Requirements
          5. 6.12.11.3.5 EMIF Asynchronous Memory Switching Characteristics
          6. 6.12.11.3.6 EMIF Asynchronous Memory Timing Diagrams
    13. 6.13 C28x Analog Peripherals
      1. 6.13.1 Analog Subsystem
        1. 6.13.1.1 Features
        2. 6.13.1.2 Block Diagram
      2. 6.13.2 Analog-to-Digital Converter (ADC)
        1. 6.13.2.1 ADC Configurability
          1. 6.13.2.1.1 Signal Mode
        2. 6.13.2.2 ADC Electrical Data and Timing
          1. 6.13.2.2.1  ADC Operating Conditions 12-bit Single-Ended
          2. 6.13.2.2.2  ADC Operating Conditions 12-bit Differential
          3. 6.13.2.2.3  ADC Operating Conditions 16-bit Single-Ended
          4. 6.13.2.2.4  ADC Operating Conditions 16-bit Differential
          5. 6.13.2.2.5  ADC Characteristics 12-bit Single-Ended
          6. 6.13.2.2.6  ADC Characteristics 12-bit Differential
          7. 6.13.2.2.7  ADC Characteristics 16-bit Single-Ended
          8. 6.13.2.2.8  ADC Characteristics 16-bit Differential
          9. 6.13.2.2.9  ADC Performance Per Pin
          10. 6.13.2.2.10 ADC Input Models
          11. 6.13.2.2.11 ADC Timing Diagrams
      3. 6.13.3 Temperature Sensor
        1. 6.13.3.1 Temperature Sensor Electrical Data and Timing
          1. 6.13.3.1.1 Temperature Sensor Characteristics
      4. 6.13.4 Comparator Subsystem (CMPSS)
        1. 6.13.4.1 CMPSS Connectivity Diagram
        2. 6.13.4.2 Block Diagram
        3. 6.13.4.3 CMPSS Electrical Data and Timing
          1. 6.13.4.3.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.13.4.3.2 CMPSS DAC Static Electrical Characteristics
          4. 6.13.4.3.3 CMPSS Illustrative Graphs
          5. 6.13.4.3.4 CMPSS DAC Dynamic Error
      5. 6.13.5 Buffered Digital-to-Analog Converter (DAC)
        1. 6.13.5.1 Buffered DAC Electrical Data and Timing
          1. 6.13.5.1.1 Buffered DAC Operating Conditions
          2. 6.13.5.1.2 Buffered DAC Electrical Characteristics
    14. 6.14 C28x Control Peripherals
      1. 6.14.1 Enhanced Capture (eCAP)
        1. 6.14.1.1 eCAP Block Diagram
        2. 6.14.1.2 eCAP Synchronization
        3. 6.14.1.3 eCAP Electrical Data and Timing
          1. 6.14.1.3.1 eCAP Timing Requirements
          2. 6.14.1.3.2 eCAP Switching Characteristics
      2. 6.14.2 High-Resolution Capture (HRCAP)
        1. 6.14.2.1 eCAP and HRCAP Block Diagram
        2. 6.14.2.2 HRCAP Electrical Data and Timing
          1. 6.14.2.2.1 HRCAP Switching Characteristics
          2. 6.14.2.2.2 HRCAP Figure and Graph
      3. 6.14.3 Enhanced Pulse Width Modulator (ePWM)
        1. 6.14.3.1 Control Peripherals Synchronization
        2. 6.14.3.2 ePWM Electrical Data and Timing
          1. 6.14.3.2.1 ePWM Timing Requirements
          2. 6.14.3.2.2 ePWM Switching Characteristics
          3. 6.14.3.2.3 Trip-Zone Input Timing
            1. 6.14.3.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.14.3.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      4. 6.14.4 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.14.4.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.14.4.2 ADCSOCAO or ADCSOCBO Timing Diagram
      5. 6.14.5 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.14.5.1 HRPWM Electrical Data and Timing
          1. 6.14.5.1.1 High-Resolution PWM Characteristics
      6. 6.14.6 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.14.6.1 eQEP Electrical Data and Timing
          1. 6.14.6.1.1 eQEP Timing Requirements
          2. 6.14.6.1.2 eQEP Switching Characteristics
      7. 6.14.7 Sigma-Delta Filter Module (SDFM)
        1. 6.14.7.1 SDFM Electrical Data and Timing
          1. 6.14.7.1.1 SDFM Timing Requirements When Using Asynchronous GPIO ASYNC Option
    15. 6.15 C28x Communications Peripherals
      1. 6.15.1  Controller Area Network (CAN)
      2. 6.15.2  Modular Controller Area Network (MCAN)
      3. 6.15.3  Fast Serial Interface (FSI)
        1. 6.15.3.1 FSI Transmitter
          1. 6.15.3.1.1 FSITX Electrical Data and Timing
            1. 6.15.3.1.1.1 FSITX Switching Characteristics
            2. 6.15.3.1.1.2 FSITX Timings
        2. 6.15.3.2 FSI Receiver
          1. 6.15.3.2.1 FSIRX Electrical Data and Timing
            1. 6.15.3.2.1.1 FSIRX Timing Requirements
            2. 6.15.3.2.1.2 FSIRX Switching Characteristics
            3. 6.15.3.2.1.3 FSIRX Timings
        3. 6.15.3.3 FSI SPI Compatibility Mode
          1. 6.15.3.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.15.3.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.15.3.3.1.2 FSITX SPI Signaling Mode Timings
      4. 6.15.4  Inter-Integrated Circuit (I2C)
        1. 6.15.4.1 I2C Electrical Data and Timing
          1. 6.15.4.1.1 I2C Timing Requirements
          2. 6.15.4.1.2 I2C Switching Characteristics
          3. 6.15.4.1.3 I2C Timing Diagram
      5. 6.15.5  Power Management Bus (PMBus) Interface
        1. 6.15.5.1 PMBus Electrical Data and Timing
          1. 6.15.5.1.1 PMBus Electrical Characteristics
          2. 6.15.5.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.15.5.1.3 PMBus Standard Mode Switching Characteristics
      6. 6.15.6  Serial Communications Interface (SCI)
      7. 6.15.7  Serial Peripheral Interface (SPI)
        1. 6.15.7.1 SPI Controller Mode Timings
          1. 6.15.7.1.1 SPI Controller Mode Switching Characteristics Clock Phase 0
          2. 6.15.7.1.2 SPI Controller Mode Switching Characteristics Clock Phase 1
          3. 6.15.7.1.3 SPI Controller Mode Timing Requirements
          4. 6.15.7.1.4 SPI Controller Mode Timing Diagrams
        2. 6.15.7.2 SPI Peripheral Mode Timings
          1. 6.15.7.2.1 SPI Peripheral Mode Switching Characteristics
          2. 6.15.7.2.2 SPI Peripheral Mode Timing Requirements
          3. 6.15.7.2.3 SPI Peripheral Mode Timing Diagrams
      8. 6.15.8  Local Interconnect Network (LIN)
      9. 6.15.9  EtherCAT SubordinateDevice Controller (ESC)
        1. 6.15.9.1 ESC Features
        2. 6.15.9.2 ESC Subsystem Integrated Features
        3. 6.15.9.3 EtherCAT IP Block Diagram
        4. 6.15.9.4 EtherCAT Electrical Data and Timing
          1. 6.15.9.4.1 EtherCAT Timing Requirements
          2. 6.15.9.4.2 EtherCAT Switching Characteristics
          3. 6.15.9.4.3 EtherCAT Timing Diagrams
      10. 6.15.10 Universal Serial Bus (USB)
        1. 6.15.10.1 USB Electrical Data and Timing
          1. 6.15.10.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.15.10.1.2 USB Output Ports DP and DM Switching Characteristics
      11. 6.15.11 Universal Asynchronous Receiver-Transmitter (UART)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Memory
      1. 7.3.1 C28x Memory Map
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 EMIF Chip Select Memory Map
      5. 7.3.5 Peripheral Registers Memory Map
      6. 7.3.6 Memory Types
        1. 7.3.6.1 Dedicated RAM (Mx and Dx RAM)
        2. 7.3.6.2 Local Shared RAM (LSx RAM)
        3. 7.3.6.3 Global Shared RAM (GSx RAM)
        4. 7.3.6.4 CPU Message RAM (CPU MSGRAM)
        5. 7.3.6.5 CLA Message RAM (CLA MSGRAM)
        6. 7.3.6.6 CLA - DMA Message RAM (CLA-DMA MSGRAM)
    4. 7.4 Identification
    5. 7.5 Bus Architecture – Peripheral Connectivity
    6. 7.6 Boot ROM
      1. 7.6.1 Device Boot
      2. 7.6.2 Device Boot Modes
      3. 7.6.3 Device Boot Configurations
      4. 7.6.4 GPIO Assignments
    7. 7.7 Security
      1. 7.7.1 Securing the Boundary of the Chip
        1. 7.7.1.1 JTAGLOCK
        2. 7.7.1.2 Zero-pin Boot
      2. 7.7.2 Dual-Zone Security
      3. 7.7.3 Disclaimer
    8. 7.8 Advanced Encryption Standard (AES) Accelerator
    9. 7.9 C28x (CPU1/CPU2) Subsystem
      1. 7.9.1  C28x Processor
        1. 7.9.1.1 Floating-Point Unit (FPU)
        2. 7.9.1.2 Fast Integer Division Unit
        3. 7.9.1.3 Trigonometric Math Unit (TMU)
        4. 7.9.1.4 VCRC Unit
        5. 7.9.1.5 Lockstep Compare Module (LCM)
      2. 7.9.2  Control Law Accelerator (CLA)
      3. 7.9.3  Embedded Real-Time Analysis and Diagnostic (ERAD)
      4. 7.9.4  Background CRC-32 (BGCRC)
      5. 7.9.5  Direct Memory Access (DMA)
      6. 7.9.6  Interprocessor Communication (IPC) Module
      7. 7.9.7  C28x Timers
      8. 7.9.8  Dual-Clock Comparator (DCC)
        1. 7.9.8.1 Features
        2. 7.9.8.2 Mapping of DCCx Clock Source Inputs
      9. 7.9.9  Nonmaskable Interrupt With Watchdog Timer (NMIWD)
      10. 7.9.10 Watchdog
      11. 7.9.11 Configurable Logic Block (CLB)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 Servo Drive Control Module
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Servo Drive Control Module Resources
        2. 8.3.1.2 Solar Micro Inverter
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 Solar Micro Inverter Resources
        3. 8.3.1.3 EV Charging Station Power Module
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 EV Charging Station Power Module Resources
        4. 8.3.1.4 On-Board Charger (OBC)
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 OBC Resources
        5. 8.3.1.5 High-Voltage Traction Inverter
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 High-Voltage Traction Inverter Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZP|100
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5.1 GPIO Muxed Pins

Table 5-7 GPIO Muxed Pins
0, 4, 8, 12 1 2 3 5 6 7 9 10 11 13 14 15 ALT
GPIO0 EPWM1_A CLB_OUTPUTXBAR1 I2CA_SDA EMIF1_A13 ESC_GPI0 FSITXA_D0
GPIO1 EPWM1_B CLB_OUTPUTXBAR2 I2CA_SCL EMIF1_A14 ESC_GPI1 FSITXA_D1
GPIO2 EPWM2_A OUTPUTXBAR1 I2CB_SDA UARTA_TX EMIF1_A15 ESC_GPI2 FSITXA_CLK
GPIO3 EPWM2_B OUTPUTXBAR2 OUTPUTXBAR2 I2CB_SCL UARTA_RX ESC_GPI3 FSIRXA_D0
GPIO4 EPWM3_A OUTPUTXBAR3 CANA_TX MCANA_TX ESC_GPI4 FSIRXA_D1
GPIO5 EPWM3_B OUTPUTXBAR3 CLB_OUTPUTXBAR3 CANA_RX MCANA_RX ESC_GPI5 FSIRXA_CLK
GPIO6 EPWM4_A OUTPUTXBAR4 EXTSYNCOUT EQEP3_A MCANB_TX LINA_TX EMIF1_DQM0 ESC_GPI6 FSITXB_D0
GPIO7 EPWM4_B OUTPUTXBAR5 EQEP3_B MCANB_RX LINA_RX EMIF1_DQM1 ESC_GPI7 FSITXB_D1
GPIO8 EPWM5_A EMIF1_RAS ADCSOCAO EQEP3_STROBE SCIA_TX CLB_OUTPUTXBAR4 MCANA_TX ESC_GPO0 FSITXB_CLK FSITXA_D1 FSIRXA_D0
GPIO9 EPWM5_B SCIB_TX OUTPUTXBAR6 EQEP3_INDEX SCIA_RX ESC_GPO1 FSIRXB_D0 FSITXA_D0 FSIRXA_CLK
GPIO10 EPWM6_A EMIF1_CAS ADCSOCBO EQEP1_A SCIB_TX SD4_C1 MCANA_RX CLB_OUTPUTXBAR5 ESC_TX0_DATA0 FSIRXB_D1 FSITXA_CLK FSIRXA_D1
GPIO11 EPWM6_B SCIB_RX OUTPUTXBAR7 EQEP1_B SCIB_RX SD4_D1 ESC_GPO3 ESC_TX0_DATA1 FSIRXB_CLK FSIRXA_D1 PMBUSA_ALERT
GPIO12 EPWM7_A CLB_OUTPUTXBAR6 ADCSOCAO EQEP1_STROBE SCIA_TX SD4_C2 EMIF1_A1 ESC_GPO4 ESC_TX0_DATA2 FSIRXC_D0 FSIRXA_D0 PMBUSA_CTL
GPIO13 EPWM7_B CLB_OUTPUTXBAR7 EQEP5_STROBE EQEP1_INDEX SCIA_RX SD4_D2 EMIF1_CS0n ESC_GPO5 ESC_TX0_DATA3 FSIRXC_D1 FSIRXA_CLK PMBUSA_SDA
GPIO14 EPWM8_A SCIB_TX EQEP5_INDEX LINA_TX OUTPUTXBAR3 OUTPUTXBAR8 ESC_GPO6 ESC_PHY1_LINKSTATUS FSIRXC_CLK EMIF1_D17 PMBUSA_SCL
GPIO15 EPWM8_B SCIB_RX LINA_RX OUTPUTXBAR4 CLB_OUTPUTXBAR8 ESC_GPO7 EQEP5_A FSIRXD_D0 EMIF1_DQM2
GPIO16 SPIA_PICO OUTPUTXBAR7 EPWM9_A SD1_D1 EQEP5_B FSIRXD_D1 ESC_RX1_CLK
GPIO17 SPIA_POCI OUTPUTXBAR8 EPWM9_B SD1_C1 EQEP5_STROBE FSIRXD_CLK ESC_RX1_DV
GPIO18 SPIA_CLK SCIB_TX CANA_RX EPWM10_A SD1_D2 MCANA_RX EMIF1_CS2n EQEP5_INDEX ESC_RX1_ERR
GPIO19 SPIA_PTE SCIB_RX CANA_TX EPWM10_B SD1_C2 MCANA_TX EMIF1_CS3n ESC_TX1_DATA3
GPIO20 EQEP1_A EPWM11_A SD1_D3 MCANB_TX EMIF1_BA0 SPIC_PICO ESC_TX1_DATA2
GPIO21 EQEP1_B EPWM11_B SD1_C3 MCANB_RX EMIF1_BA1 SPIC_POCI ESC_TX1_DATA1
GPIO22 EQEP1_STROBE SCIB_TX EPWM12_A SPIB_CLK SD1_D4 MCANA_TX EMIF1_RAS SPIC_CLK ESC_TX1_DATA0
GPIO23 EQEP1_INDEX SCIB_RX EPWM12_B SPIB_PTE SD1_C4 MCANA_RX EMIF1_CAS SPIC_PTE ESC_PHY_RESETn
GPIO24 OUTPUTXBAR1 EQEP2_A LINB_TX SPIB_PICO SD2_D1 PMBUSA_SCL EMIF1_DQM0 EPWM13_A ESC_RX0_DATA1 ESC_RX0_CLK
GPIO25 OUTPUTXBAR2 EQEP2_B LINB_RX SPIB_POCI SD2_C1 PMBUSA_SDA EMIF1_DQM1 EQEP5_B EPWM13_B FSITXA_D1 ESC_RX0_DV
GPIO26 OUTPUTXBAR3 EQEP2_INDEX OUTPUTXBAR3 SPIB_CLK SD2_D2 PMBUSA_ALERT EMIF1_DQM2 ESC_MDIO_CLK EPWM14_A FSITXA_D0 ESC_RX0_ERR
GPIO27 OUTPUTXBAR4 EQEP2_STROBE OUTPUTXBAR4 SPIB_PTE SD2_C2 PMBUSA_CTL EMIF1_DQM3 ESC_MDIO_DATA EPWM14_B FSITXA_CLK ESC_RX0_DATA0
GPIO28 SCIA_RX EMIF1_CS4n UARTA_RX OUTPUTXBAR5 EQEP3_A SD2_D3 EMIF1_CS2n EPWM15_A ESC_RX0_DATA1
GPIO29 SCIA_TX EMIF1_SDCKE UARTA_TX OUTPUTXBAR6 EQEP3_B SD2_C3 EMIF1_CS3n ESC_LATCH0 ESC_I2C_SDA EPWM15_B ESC_SYNC0 ESC_RX0_DATA2
GPIO30 CANA_RX EMIF1_CLK MCANA_RX OUTPUTXBAR7 EQEP3_STROBE SD2_D4 EMIF1_CS4n ESC_LATCH1 ESC_I2C_SCL EPWM16_A ESC_SYNC1 SPID_PICO
GPIO31 CANA_TX EMIF1_WEn MCANA_TX OUTPUTXBAR8 EQEP3_INDEX SD2_C4 EMIF1_RNW I2CA_SDA EPWM16_B SPID_POCI
GPIO32 I2CA_SDA EMIF1_CS0n SPIA_PICO EQEP4_A LINB_TX CLB_OUTPUTXBAR1 EMIF1_OEn I2CA_SCL SPID_CLK
GPIO33 I2CA_SCL EMIF1_RNW SPIA_POCI EQEP4_B CLB_OUTPUTXBAR2 EMIF1_BA0 ESC_LED_ERR SPID_PTE
GPIO34 OUTPUTXBAR1 EMIF1_CS2n SPIA_CLK EQEP4_STROBE I2CB_SDA CLB_OUTPUTXBAR3 EMIF1_BA1 ESC_LATCH0 EPWM18_A SCIA_TX ESC_SYNC0
GPIO35 SCIA_RX EMIF1_CS3n SPIA_PTE EQEP4_INDEX I2CB_SCL CLB_OUTPUTXBAR4 EMIF1_A0 ESC_LATCH1 EPWM18_B SCIA_RX ESC_SYNC1
GPIO36 SCIA_TX EMIF1_WAIT CANA_RX CLB_OUTPUTXBAR5 EMIF1_A1 MCANA_RX SD1_D1 EMIF1_WEn
GPIO37 OUTPUTXBAR2 EMIF1_OEn EPWM18_A CANA_TX CLB_OUTPUTXBAR6 EMIF1_A2 MCANA_TX SD1_D2 EMIF1_D24
GPIO38 EMIF1_A0 EPWM18_B UARTA_TX SCIB_TX CLB_OUTPUTXBAR7 EMIF1_A3 SD1_D3 EMIF1_CS2n
GPIO39 EMIF1_A1 UARTA_RX SCIB_RX CLB_OUTPUTXBAR8 EMIF1_A4 ESC_MDIO_DATA ESC_LED_RUN SD1_D4 FSIRXD_CLK
GPIO40 EMIF1_A2 EPWM13_A MCANB_RX I2CB_SDA SD4_C3 ESC_GPO2 CLB_OUTPUTXBAR1 SD2_C1 ESC_I2C_SDA
GPIO41 EMIF1_A3 EPWM13_B MCANB_TX I2CB_SCL SD4_D3 CLB_OUTPUTXBAR2 SD2_D1 ESC_I2C_SCL FSIRXD_CLK
GPIO42 EPWM14_A EQEP4_A I2CA_SDA SD4_C4 CLB_OUTPUTXBAR5 UARTA_TX FSIRXD_D0 SCIA_TX USB0DM
GPIO43 EPWM14_B EQEP4_B I2CA_SCL SD4_D4 CLB_OUTPUTXBAR6 UARTA_RX FSIRXD_D1 SCIA_RX USB0DP
GPIO44 SPID_POCI EMIF1_A4 MCANB_RX SD3_C4 UARTB_TX CLB_OUTPUTXBAR6 FSIRXD_CLK ESC_TX1_CLK
GPIO45 SPID_PTE EMIF1_A5 MCANB_TX SD3_D4 UARTB_RX CLB_OUTPUTXBAR7 ESC_TX1_ENA
GPIO46 EPWM4_A EMIF1_A6 EPWM14_A SCIA_RX SD3_C4 ESC_MDIO_CLK
GPIO47 EPWM4_B EMIF1_A7 EPWM14_B SCIA_TX SD4_C3 ESC_MDIO_DATA
GPIO48 OUTPUTXBAR3 EMIF1_A8 SCIA_TX SD1_D1 SD2_C2 ESC_PHY_CLK
GPIO49 OUTPUTXBAR4 EMIF1_A9 SCIA_RX SD1_C1 EMIF1_A5 SD2_D1 FSITXA_D0
GPIO50 EQEP1_A EMIF1_A10 EPWM15_A SPIC_PICO SD1_D2 EMIF1_A6 ESC_LATCH0 SD2_D2 FSITXA_D1
GPIO51 EQEP1_B EMIF1_A11 EPWM15_B SPIC_POCI SD1_C2 EMIF1_A7 ESC_LATCH1 SD2_D3 FSITXA_CLK
GPIO52 EQEP1_STROBE EMIF1_A12 EPWM16_A SPIC_CLK SD1_D3 EMIF1_A8 ESC_MDIO_CLK SD2_D4 FSIRXA_D0
GPIO53 EQEP1_INDEX EMIF1_D31 SPIC_PTE SD1_C3 EMIF1_A9 ESC_MDIO_DATA SD1_C1 FSIRXA_D1
GPIO54 SPIA_PICO EMIF1_D30 EQEP2_A SCIB_TX SD1_D4 EMIF1_A10 ESC_PHY_CLK SD1_C2 FSIRXA_CLK
GPIO55 SPIA_POCI EMIF1_D29 EPWM16_B EQEP2_B SCIB_RX SD1_C4 EMIF1_D0 ESC_PHY0_LINKSTATUS SD1_C3 FSITXB_D0
GPIO56 SPIA_CLK EMIF1_D28 EPWM17_A EQEP2_STROBE SD2_D1 EMIF1_D1 I2CA_SDA ESC_TX0_ENA SD1_C4 FSITXB_CLK
GPIO57 SPIA_PTE EMIF1_D27 EPWM17_B EQEP2_INDEX SD2_C1 EMIF1_D2 I2CA_SCL ESC_TX0_CLK SD3_D3 FSITXB_D1
GPIO58 SPIA_PICO EMIF1_D26 EPWM8_A OUTPUTXBAR1 SPIB_CLK SD2_D2 EMIF1_D3 ESC_LED_LINK0_ACTIVE CANA_RX SD2_C2 FSIRXB_D0 SPIA_PICO
GPIO59 EPWM5_A EMIF1_D25 EPWM8_B OUTPUTXBAR2 SPIB_PTE SD2_C2 EMIF1_D4 ESC_LED_LINK1_ACTIVE CANA_TX SD2_C3 FSIRXB_D1 SPIA_POCI
GPIO60 EPWM3_B EMIF1_D24 ESC_LATCH0 OUTPUTXBAR3 SPIB_PICO SD2_D3 EMIF1_D5 ESC_LED_ERR SD2_C4 FSIRXB_CLK SPIA_CLK
GPIO61 EPWM17_B EMIF1_D23 ESC_LATCH1 OUTPUTXBAR4 SPIB_POCI SD2_C3 EMIF1_D6 ESC_LED_RUN CANA_RX SPIA_PTE
GPIO62 SCIA_RX EMIF1_D22 ESC_MDIO_CLK EQEP3_A CANA_RX SD2_D4 EMIF1_D7 ESC_LED_STATE_RUN CANA_TX
GPIO63 SCIA_TX EMIF1_D21 EPWM9_A EQEP3_B CANA_TX SD2_C4 EMIF1_RNW EMIF1_BA0 SD1_D1 ESC_RX1_DATA0 SPIB_PICO
GPIO64 EMIF1_D20 EPWM9_B EQEP3_STROBE SCIA_RX EMIF1_WAIT EMIF1_BA1 SD1_C1 ESC_RX1_DATA1 SPIB_POCI
GPIO65 EMIF1_D19 EPWM10_A EQEP3_INDEX SCIA_TX EMIF1_WEn FSITXB_CLK SD1_D2 ESC_RX1_DATA2 SPIB_CLK
GPIO66 EQEP6_B EMIF1_D18 EPWM10_B I2CB_SDA EMIF1_OEn FSITXB_D1 SD1_C2 ESC_RX1_DATA3 SPIB_PTE
GPIO67 EMIF1_D17 EPWM17_A LINB_TX ESC_I2C_SDA SD1_D3
GPIO68 EMIF1_D16 EPWM17_B LINB_RX ESC_I2C_SCL SD1_C3 ESC_PHY1_LINKSTATUS
GPIO69 EMIF1_D15 EPWM11_A I2CB_SCL FSITXB_D0 SD1_D4 ESC_RX1_CLK SPIC_PICO
GPIO70 EMIF1_D14 EPWM11_B CANA_RX SCIB_TX UARTB_TX MCANA_RX FSIRXB_D0 SD1_C4 ESC_RX1_DV SPIC_POCI
GPIO71 EMIF1_D13 EPWM12_A CANA_TX SCIB_RX UARTB_RX MCANA_TX SD3_D1 ESC_RX1_ERR SPIC_CLK
GPIO72 EQEP6_STROBE EMIF1_D12 EPWM12_B OUTPUTXBAR8 UARTA_TX MCANB_RX SD3_C1 ESC_TX1_DATA3 SPIC_PTE
GPIO73 EQEP6_INDEX EMIF1_D11 XCLKOUT OUTPUTXBAR6 UARTA_RX EPWM5_B MCANB_TX SD4_D4 SD2_D2 ESC_TX1_DATA2
GPIO74 EPWM8_A EMIF1_D10 EQEP5_A MCANA_TX SD1_D4 SD2_C2 ESC_TX1_DATA1
GPIO75 EPWM8_B EMIF1_D9 EQEP5_B SPID_CLK MCANA_RX CLB_OUTPUTXBAR8 SD2_D3 ESC_TX1_DATA0
GPIO76 EPWM9_A EMIF1_D8 EQEP5_STROBE SD3_C1 SD4_D4 SD2_C3 ESC_PHY_RESETn
GPIO77 EPWM9_B EMIF1_D7 EQEP5_INDEX SD3_D1 SD1_D4 SD2_D4 ESC_RX0_CLK
GPIO78 EPWM10_A EMIF1_D6 EQEP2_A SD3_C2 SD4_D4 SD2_C4 ESC_RX0_DV
GPIO79 EPWM10_B EMIF1_D5 ERRORSTS EQEP2_B SD3_D2 SD2_D1 ESC_RX0_ERR
GPIO80 EPWM11_A EMIF1_D4 ERRORSTS EQEP2_STROBE SD3_C3 SD1_D4 SD2_C1 ESC_RX0_DATA0
GPIO81 EPWM11_B EMIF1_D3 EQEP2_INDEX SD3_D3 ESC_RX0_DATA1
GPIO82 EPWM12_A EMIF1_D2 SD3_C2 ESC_RX0_DATA2
GPIO83 EPWM12_B EMIF1_D1 SD3_D2 ESC_RX0_DATA3
GPIO84 EPWM12_B EMIF1_D1 EMIF1_CS4n SCIA_TX EQEP6_A SD3_D2 UARTA_TX SD3_C2 ESC_TX0_ENA ESC_RX0_DATA3
GPIO85 EPWM13_A EMIF1_D0 SCIA_RX EQEP6_B SD3_D1 UARTA_RX SD3_D3 ESC_TX0_CLK EMIF1_DQM2
GPIO86 EPWM13_B EMIF1_A13 EMIF1_CAS SCIB_TX EQEP6_STROBE SD3_C3 ESC_PHY0_LINKSTATUS
GPIO87 EPWM14_A EMIF1_A14 EMIF1_RAS SCIB_RX EQEP6_INDEX EMIF1_DQM3 SD3_D4 ESC_TX0_DATA0
GPIO88 EPWM14_B EMIF1_A15 EMIF1_DQM0 EMIF1_DQM1 SD3_C4 ESC_TX0_DATA1
GPIO89 EPWM15_A EMIF1_A16 EMIF1_DQM1 SD1_D3 EMIF1_CAS SD4_D1 ESC_TX0_DATA2 SPID_PTE
GPIO90 EPWM15_B EMIF1_A17 EMIF1_DQM2 SD1_C3 EMIF1_RAS SD4_C1 ESC_TX0_DATA3 SPID_CLK
GPIO91 EPWM16_A EMIF1_A18 EMIF1_DQM3 I2CA_SDA SD4_D2 EMIF1_DQM2 PMBUSA_SCL CLB_OUTPUTXBAR1 SPID_PICO
GPIO92 EPWM16_B EMIF1_A19 EMIF1_BA1 I2CA_SCL SD4_C2 EMIF1_DQM0 PMBUSA_SDA FSIRXD_CLK CLB_OUTPUTXBAR2 SPID_POCI
GPIO93 EPWM17_A EMIF1_BA0 SD4_D3 PMBUSA_ALERT ESC_TX1_CLK CLB_OUTPUTXBAR3 SPID_CLK
GPIO94 EPWM17_B SD4_C3 EMIF1_BA1 PMBUSA_CTL ESC_TX1_ENA CLB_OUTPUTXBAR4 SPID_PTE
GPIO95 EPWM18_A EQEP4_A SD1_D1 ESC_GPO10 CLB_OUTPUTXBAR5
GPIO96 EPWM18_B EQEP4_B EQEP1_A SD1_C1 ESC_GPO11 CLB_OUTPUTXBAR6
GPIO97 EQEP4_STROBE EQEP1_B SD1_D2 ESC_GPI17 CLB_OUTPUTXBAR7
GPIO98 EQEP4_INDEX EQEP1_STROBE SD1_C2 ESC_GPI18 CLB_OUTPUTXBAR8
GPIO99 EMIF1_DQM3 EPWM8_A EQEP1_INDEX SD4_D4 ESC_GPI21 EMIF1_D17
GPIO100 SPIA_PICO EMIF1_BA1 EPWM9_A EQEP2_A SPIC_PICO SD4_C4 SD1_D1 ESC_GPI0 FSIRXD_D1 FSITXA_D0 EMIF1_D24
GPIO101 EPWM18_A EQEP2_B SPIC_POCI ESC_GPI1 EMIF1_A5 FSITXA_D1
GPIO102 EPWM18_B EQEP2_STROBE SPIC_CLK ESC_GPI2 EMIF1_A6 FSITXA_CLK
GPIO103 EMIF1_BA0 EPWM8_B EQEP2_INDEX SPIC_PTE SD4_C4 ESC_GPI3 FSIRXA_D0
GPIO104 I2CA_SDA EPWM18_A EQEP3_A SD3_D1 ESC_GPI4 FSIRXA_D1 ESC_SYNC0
GPIO105 I2CA_SCL EPWM18_B EQEP3_B SD3_C1 ESC_GPI5 FSIRXA_CLK ESC_SYNC1
GPIO106 EPWM16_A EMIF1_A10 EQEP3_STROBE SD3_D2 ESC_GPI6 FSITXB_D0
GPIO107 EPWM16_B EQEP3_INDEX SD3_C2 ESC_GPI7 FSITXB_D1
GPIO108 EPWM17_A EMIF1_A12 EQEP5_A SD3_D3 ESC_GPI8 FSITXB_CLK
GPIO109 EPWM17_B EMIF1_A11 EQEP5_B SD3_C3 ESC_GPI9
GPIO110 EMIF1_D31 EQEP5_STROBE SD3_D4 ESC_GPI10 FSIRXB_D0
GPIO111 EMIF1_D30 EQEP5_INDEX SD3_C4 ESC_GPI11 FSIRXB_D1
GPIO112 EMIF1_D29 SD1_D3 ESC_GPI12 FSIRXB_CLK
GPIO113 EMIF1_D28 SD1_C3 ESC_GPI13
GPIO114 EMIF1_D27 SD1_D4 ESC_GPI14
GPIO115 EMIF1_D26 OUTPUTXBAR5 SD1_C4 ESC_GPI15 FSIRXC_D0
GPIO116 OUTPUTXBAR6 ESC_GPI16 FSIRXC_D1
GPIO119 EMIF1_D25 MCANB_TX ESC_GPI19 FSIRXD_D1
GPIO120 EMIF1_D24 MCANB_RX ESC_GPI20 FSIRXD_CLK
GPIO122 EMIF1_D23 SPIC_PICO SD1_D1 ESC_GPI22
GPIO123 EMIF1_D22 SPIC_POCI SD1_C1 ESC_GPI23
GPIO124 EMIF1_D21 SPIC_CLK SD1_D2 ESC_GPI24
GPIO125 EMIF1_D20 SPIC_PTE SD1_C2 ESC_GPI25 ESC_LATCH0
GPIO126 EMIF1_D19 SPID_PICO SD1_D3 ESC_GPI26 ESC_LATCH1
GPIO127 EMIF1_D18 SPID_POCI SD1_C3 ESC_GPI27 ESC_SYNC0
GPIO128 EMIF1_D17 SPID_CLK SD1_D4 ESC_GPI28 ESC_SYNC1
GPIO129 EMIF1_D16 SPID_PTE SD1_C4 ESC_GPI29 ESC_TX1_ENA
GPIO130 EPWM13_A SD2_D1 ESC_GPI30 ESC_TX1_CLK
GPIO131 EPWM13_B SD2_C1 ESC_GPI31 ESC_TX1_DATA0
GPIO132 EPWM14_A SD2_D2 ESC_GPO0 ESC_TX1_DATA1
GPIO133 EMIF1_A11 EPWM9_A SD2_C2 ESC_LED_STATE_RUN
GPIO134 EPWM14_B SD2_D3 ESC_GPO1 SD2_C1 ESC_TX1_DATA2
GPIO141 EPWM15_A SCIB_TX ESC_GPO8 ESC_RX1_DATA2
GPIO142 EPWM15_B SCIB_RX ESC_GPO9 ESC_RX1_DATA3
GPIO145 EPWM1_A MCANB_TX ESC_GPO12 ESC_LED_ERR
GPIO146 EPWM1_B MCANB_RX ESC_GPO13 ESC_LED_RUN
GPIO147 EPWM2_A EQEP5_A ESC_GPO14 ESC_LED_STATE_RUN
GPIO148 EPWM2_B EQEP5_B ESC_GPO15 ESC_PHY0_LINKSTATUS
GPIO149 EPWM3_A EQEP5_STROBE ESC_GPO16 ESC_PHY1_LINKSTATUS
GPIO150 EPWM3_B EQEP5_INDEX ESC_GPO17 ESC_I2C_SDA
GPIO151 EPWM4_A PMBUSA_SCL ESC_GPO18 FSITXA_D0 ESC_I2C_SCL
GPIO152 EPWM4_B PMBUSA_SDA ESC_GPO19 FSITXA_D1 ESC_MDIO_CLK
GPIO153 EPWM5_A PMBUSA_ALERT ESC_GPO20 FSITXA_CLK ESC_MDIO_DATA
GPIO154 EPWM5_B PMBUSA_CTL ESC_GPO21 FSIRXA_D0 ESC_PHY_CLK
GPIO155 EPWM6_A ESC_GPO22 FSIRXA_D1 ESC_PHY_RESETn
GPIO156 EPWM6_B ESC_GPO23 FSIRXA_CLK ESC_TX0_ENA
GPIO157 EPWM7_A ESC_GPO24 FSITXB_D0 ESC_TX0_CLK
GPIO158 EPWM7_B ESC_GPO25 FSITXB_D1 ESC_TX0_DATA0
GPIO159 EPWM8_A ESC_GPO26 FSITXB_CLK ESC_TX0_DATA1
GPIO160 EPWM8_B ESC_GPO27 FSIRXB_D0 ESC_TX0_DATA2
GPIO161 EPWM9_A ESC_GPO28 FSIRXB_D1 ESC_TX0_DATA3
GPIO162 EPWM9_B ESC_GPO29 FSIRXB_CLK ESC_RX0_DV
GPIO163 EPWM10_A ESC_GPO30 FSIRXC_D0 ESC_RX0_CLK
GPIO164 EPWM10_B ESC_GPO31 FSIRXC_D1 ESC_RX0_ERR
GPIO165 EPWM11_A FSIRXC_CLK ESC_RX0_DATA0
GPIO166 EPWM11_B FSIRXD_D0 ESC_RX0_DATA1
GPIO167 EPWM12_A FSIRXD_D1 ESC_RX0_DATA2
GPIO168 EPWM12_B FSIRXD_CLK ESC_RX0_DATA3
GPIO198 EQEP1_A EPWM9_B SPIA_PICO ESC_PDI_UC_IRQ
GPIO199 EQEP1_STROBE EPWM17_A SCIB_TX EPWM12_A SPIB_CLK SD1_D4 MCANA_TX EMIF1_RAS SPIC_CLK
GPIO200 EQEP1_INDEX EPWM17_B SCIB_RX EPWM12_B SPIB_PTE SD1_C4 MCANA_RX EMIF1_CAS ESC_TX1_DATA1 SPIC_PTE
GPIO201 OUTPUTXBAR1 EQEP2_A EPWM18_A LINB_TX SPIB_PICO SD2_D1 PMBUSA_SCL EMIF1_DQM0 ESC_TX1_DATA2 EPWM13_A
GPIO202 OUTPUTXBAR2 EQEP2_B EPWM18_B LINB_RX SPIB_POCI SD2_C1 PMBUSA_SDA EMIF1_DQM1 ESC_TX1_DATA3 EPWM13_B FSITXA_D1
GPIO203 OUTPUTXBAR3 EQEP2_INDEX SPIA_POCI OUTPUTXBAR3 SPIB_CLK SD3_D1 PMBUSA_ALERT EMIF1_DQM2 ESC_MDIO_CLK EPWM14_A FSITXA_D0 EPWM8_B
GPIO204 OUTPUTXBAR4 EQEP2_STROBE SPIA_CLK OUTPUTXBAR4 SPIB_PTE SD2_C2 PMBUSA_CTL EMIF1_DQM3 ESC_MDIO_DATA EPWM14_B FSITXA_CLK SD1_D3
GPIO205 EQEP1_INDEX EPWM10_A SPIA_PTE OUTPUTXBAR1 SD1_C3
GPIO206 EMIF1_A11 EPWM10_B EMIF1_WEn OUTPUTXBAR2 ESC_PHY_CLK ESC_LED_STATE_RUN
GPIO207 EQEP2_A EPWM11_A EXTSYNCOUT CANA_TX SD4_D1 SCIA_RX LINA_RX I2CB_SCL OUTPUTXBAR3 ESC_RX1_CLK PMBUSA_ALERT
GPIO208 EQEP2_B EPWM11_B EMIF1_D13 SPIB_PICO SD4_C1 SCIA_TX OUTPUTXBAR4 ESC_RX1_DV PMBUSA_CTL
GPIO209 EQEP2_STROBE EPWM12_A EMIF1_D14 SPIB_POCI SD4_D2 EPWM12_B LINB_RX OUTPUTXBAR5 ESC_RX1_ERR PMBUSA_SDA
GPIO210 EQEP2_INDEX EPWM12_B EMIF1_D15 SD4_C2 LINB_TX OUTPUTXBAR6 ESC_RX0_DATA2 PMBUSA_SCL
GPIO211 EQEP6_A EPWM14_A SD4_D3 OUTPUTXBAR7 ESC_LED_LINK0_ACTIVE
GPIO212 EQEP6_B EPWM14_B SD4_C3 ESC_LED_LINK1_ACTIVE
GPIO213 EQEP6_STROBE EPWM8_A SD4_D4 LINB_TX ESC_LED_ERR
GPIO214 CANA_RX EMIF1_CLK MCANA_RX OUTPUTXBAR7 EQEP3_STROBE SD2_D4 EMIF1_CS4n ESC_LATCH1 ESC_I2C_SCL EPWM16_A ESC_SYNC1 SPID_PICO
GPIO215 SCIA_RX EMIF1_CS4n CANA_RX OUTPUTXBAR5 EQEP3_A SD2_D3 EMIF1_CS2n I2CB_SDA SPIC_POCI EPWM15_A LINA_TX EMIF1_D12
GPIO216 SCIA_TX EMIF1_SDCKE SPID_CLK OUTPUTXBAR6 EQEP3_B SD2_C3 EMIF1_CS3n ESC_LATCH0 ESC_I2C_SDA EPWM15_B ESC_SYNC0 EMIF1_D13
GPIO217 CANA_TX EMIF1_WEn MCANA_TX OUTPUTXBAR8 EQEP3_INDEX SD2_C4 EMIF1_RNW I2CA_SDA SPID_PTE EPWM16_B LINB_TX SPID_POCI
GPIO218 I2CA_SDA EMIF1_CS0n SPIA_PICO EQEP4_A LINB_TX CLB_OUTPUTXBAR1 EMIF1_OEn I2CA_SCL SPID_CLK
GPIO219 EQEP6_INDEX EPWM8_B SD4_C4 ESC_LED_RUN
GPIO220 EPWM6_A SPID_POCI OUTPUTXBAR2 SCIB_TX MCANA_TX PMBUSA_ALERT X1
GPIO221 EPWM6_B SPID_PTE OUTPUTXBAR3 SCIB_RX MCANA_RX PMBUSA_CTL X2
GPIO222 TDI EPWM7_A SPIA_PICO OUTPUTXBAR4 SCIA_RX UARTB_TX I2CA_SDA SPIC_CLK ESC_PDI_UC_IRQ PMBUSA_SDA
GPIO223 TDO EPWM7_B EMIF1_A11 OUTPUTXBAR5 SCIA_TX UARTB_RX I2CA_SCL SPIC_PTE PMBUSA_SCL
GPIO224 ERRORSTS EMIF1_SDCKE XCLKOUT OUTPUTXBAR1 SD2_C1 ESC_PDI_UC_IRQ
AIO225
AIO226
AIO227
AIO228
AIO229
AIO230
AIO231
AIO232
AIO233
AIO234
AIO235
AIO236
AIO237
AIO238
AIO239
AIO240
AIO241
AIO242