SPRSP69B July   2023  – November 2023 TMS320F28P650DK , TMS320F28P659DK-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pins With Internal Pullup and Pulldown
    5. 5.5 Pin Multiplexing
      1. 5.5.1 GPIO Muxed Pins
      2. 5.5.2 USB Pin Muxing
      3. 5.5.3 High-Speed SPI Pin Muxing
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption VREG Enabled
      2. 6.5.2 System Current Consumption VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Current Consumption Graphs
      5. 6.5.5 Reducing Current Consumption
        1. 6.5.5.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics for ZEJ Package
    8. 6.8  Thermal Resistance Characteristics for PTP Package
    9. 6.9  Thermal Resistance Characteristics for NMR Package
    10. 6.10 Thermal Resistance Characteristics for PZP Package
    11. 6.11 Thermal Design Considerations
    12. 6.12 System
      1. 6.12.1  Power Management Module (PMM)
        1. 6.12.1.1 Introduction
        2. 6.12.1.2 Overview
          1. 6.12.1.2.1 Power Rail Monitors
            1. 6.12.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.12.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.12.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.12.1.2.2 External Supervisor Usage
          3. 6.12.1.2.3 Delay Blocks
          4. 6.12.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.12.1.2.5 VREGENZ
        3. 6.12.1.3 External Components
          1. 6.12.1.3.1 Decoupling Capacitors
            1. 6.12.1.3.1.1 VDDIO Decoupling
            2. 6.12.1.3.1.2 VDD Decoupling
        4. 6.12.1.4 Power Sequencing
          1. 6.12.1.4.1 Supply Pins Ganging
          2. 6.12.1.4.2 Signal Pins Power Sequence
          3. 6.12.1.4.3 Supply Pins Power Sequence
            1. 6.12.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.12.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.12.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.12.1.4.3.4 Supply Slew Rate
        5. 6.12.1.5 Power Management Module Electrical Data and Timing
          1. 6.12.1.5.1 Power Management Module Operating Conditions
          2. 6.12.1.5.2 Power Management Module Characteristics
      2. 6.12.2  Reset Timing
        1. 6.12.2.1 Reset Sources
        2. 6.12.2.2 Reset Electrical Data and Timing
          1. 6.12.2.2.1 Reset XRSn Timing Requirements
          2. 6.12.2.2.2 Reset XRSn Switching Characteristics
          3. 6.12.2.2.3 Reset Timing Diagrams
      3. 6.12.3  Clock Specifications
        1. 6.12.3.1 Clock Sources
        2. 6.12.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.12.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.12.3.2.1.1 Input Clock Frequency
            2. 6.12.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.12.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source Not a Crystal
            4. 6.12.3.2.1.4 X1 Timing Requirements
            5. 6.12.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.12.3.2.1.6 APLL Characteristics
            7. 6.12.3.2.1.7 XCLKOUT Switching Characteristics PLL Bypassed or Enabled
            8. 6.12.3.2.1.8 Internal Clock Frequencies
        3. 6.12.3.3 Input Clocks
        4. 6.12.3.4 XTAL Oscillator
          1. 6.12.3.4.1 Introduction
          2. 6.12.3.4.2 Overview
            1. 6.12.3.4.2.1 Electrical Oscillator
              1. 6.12.3.4.2.1.1 Modes of Operation
                1. 6.12.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.12.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.12.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.12.3.4.2.2 Quartz Crystal
            3. 6.12.3.4.2.3 GPIO Modes of Operation
          3. 6.12.3.4.3 Functional Operation
            1. 6.12.3.4.3.1 ESR – Effective Series Resistance
            2. 6.12.3.4.3.2 Rneg – Negative Resistance
            3. 6.12.3.4.3.3 Start-up Time
            4. 6.12.3.4.3.4 DL – Drive Level
          4. 6.12.3.4.4 How to Choose a Crystal
          5. 6.12.3.4.5 Testing
          6. 6.12.3.4.6 Common Problems and Debug Tips
          7. 6.12.3.4.7 Crystal Oscillator Specifications
            1. 6.12.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.12.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.12.3.4.7.3 Crystal Oscillator Parameters
            4. 6.12.3.4.7.4 Crystal Oscillator Electrical Characteristics
        5. 6.12.3.5 Internal Oscillators
          1. 6.12.3.5.1 INTOSC Characteristics
      4. 6.12.4  Flash Parameters
        1. 6.12.4.1 Flash Parameters 
      5. 6.12.5  RAM Specifications
      6. 6.12.6  ROM Specifications
      7. 6.12.7  Emulation/JTAG
        1. 6.12.7.1 JTAG Electrical Data and Timing
          1. 6.12.7.1.1 JTAG Timing Requirements
          2. 6.12.7.1.2 JTAG Switching Characteristics
          3. 6.12.7.1.3 JTAG Timing Diagram
        2. 6.12.7.2 cJTAG Electrical Data and Timing
          1. 6.12.7.2.1 cJTAG Timing Requirements
          2. 6.12.7.2.2 cJTAG Switching Characteristics
          3. 6.12.7.2.3 cJTAG Timing Diagram
      8. 6.12.8  GPIO Electrical Data and Timing
        1. 6.12.8.1 GPIO – Output Timing
          1. 6.12.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.12.8.1.2 General-Purpose Output Timing Diagram
        2. 6.12.8.2 GPIO – Input Timing
          1. 6.12.8.2.1 General-Purpose Input Timing Requirements
          2. 6.12.8.2.2 Sampling Mode
        3. 6.12.8.3 Sampling Window Width for Input Signals
      9. 6.12.9  Interrupts
        1. 6.12.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.12.9.1.1 External Interrupt Timing Requirements
          2. 6.12.9.1.2 External Interrupt Switching Characteristics
          3. 6.12.9.1.3 External Interrupt Timing
      10. 6.12.10 Low-Power Modes
        1. 6.12.10.1 Clock-Gating Low-Power Modes
        2. 6.12.10.2 Low-Power Mode Wake-up Timing
          1. 6.12.10.2.1 IDLE Mode Timing Requirements
          2. 6.12.10.2.2 IDLE Mode Switching Characteristics
          3. 6.12.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.12.10.2.4 STANDBY Mode Timing Requirements
          5. 6.12.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.12.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.12.10.2.7 HALT Mode Timing Requirements
          8. 6.12.10.2.8 HALT Mode Switching Characteristics
          9. 6.12.10.2.9 HALT Entry and Exit Timing Diagram
      11. 6.12.11 External Memory Interface (EMIF)
        1. 6.12.11.1 Asynchronous Memory Support
        2. 6.12.11.2 Synchronous DRAM Support
        3. 6.12.11.3 EMIF Electrical Data and Timing
          1. 6.12.11.3.1 EMIF Synchronous Memory Timing Requirements
          2. 6.12.11.3.2 EMIF Synchronous Memory Switching Characteristics
          3. 6.12.11.3.3 EMIF Synchronous Memory Timing Diagrams
          4. 6.12.11.3.4 EMIF Asynchronous Memory Timing Requirements
          5. 6.12.11.3.5 EMIF Asynchronous Memory Switching Characteristics
          6. 6.12.11.3.6 EMIF Asynchronous Memory Timing Diagrams
    13. 6.13 C28x Analog Peripherals
      1. 6.13.1 Analog Subsystem
        1. 6.13.1.1 Features
        2. 6.13.1.2 Block Diagram
      2. 6.13.2 Analog-to-Digital Converter (ADC)
        1. 6.13.2.1 ADC Configurability
          1. 6.13.2.1.1 Signal Mode
        2. 6.13.2.2 ADC Electrical Data and Timing
          1. 6.13.2.2.1  ADC Operating Conditions 12-bit Single-Ended
          2. 6.13.2.2.2  ADC Operating Conditions 12-bit Differential
          3. 6.13.2.2.3  ADC Operating Conditions 16-bit Single-Ended
          4. 6.13.2.2.4  ADC Operating Conditions 16-bit Differential
          5. 6.13.2.2.5  ADC Characteristics 12-bit Single-Ended
          6. 6.13.2.2.6  ADC Characteristics 12-bit Differential
          7. 6.13.2.2.7  ADC Characteristics 16-bit Single-Ended
          8. 6.13.2.2.8  ADC Characteristics 16-bit Differential
          9. 6.13.2.2.9  ADC Performance Per Pin
          10. 6.13.2.2.10 ADC Input Models
          11. 6.13.2.2.11 ADC Timing Diagrams
      3. 6.13.3 Temperature Sensor
        1. 6.13.3.1 Temperature Sensor Electrical Data and Timing
          1. 6.13.3.1.1 Temperature Sensor Characteristics
      4. 6.13.4 Comparator Subsystem (CMPSS)
        1. 6.13.4.1 CMPSS Connectivity Diagram
        2. 6.13.4.2 Block Diagram
        3. 6.13.4.3 CMPSS Electrical Data and Timing
          1. 6.13.4.3.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.13.4.3.2 CMPSS DAC Static Electrical Characteristics
          4. 6.13.4.3.3 CMPSS Illustrative Graphs
          5. 6.13.4.3.4 CMPSS DAC Dynamic Error
      5. 6.13.5 Buffered Digital-to-Analog Converter (DAC)
        1. 6.13.5.1 Buffered DAC Electrical Data and Timing
          1. 6.13.5.1.1 Buffered DAC Operating Conditions
          2. 6.13.5.1.2 Buffered DAC Electrical Characteristics
    14. 6.14 C28x Control Peripherals
      1. 6.14.1 Enhanced Capture (eCAP)
        1. 6.14.1.1 eCAP Block Diagram
        2. 6.14.1.2 eCAP Synchronization
        3. 6.14.1.3 eCAP Electrical Data and Timing
          1. 6.14.1.3.1 eCAP Timing Requirements
          2. 6.14.1.3.2 eCAP Switching Characteristics
      2. 6.14.2 High-Resolution Capture (HRCAP)
        1. 6.14.2.1 eCAP and HRCAP Block Diagram
        2. 6.14.2.2 HRCAP Electrical Data and Timing
          1. 6.14.2.2.1 HRCAP Switching Characteristics
          2. 6.14.2.2.2 HRCAP Figure and Graph
      3. 6.14.3 Enhanced Pulse Width Modulator (ePWM)
        1. 6.14.3.1 Control Peripherals Synchronization
        2. 6.14.3.2 ePWM Electrical Data and Timing
          1. 6.14.3.2.1 ePWM Timing Requirements
          2. 6.14.3.2.2 ePWM Switching Characteristics
          3. 6.14.3.2.3 Trip-Zone Input Timing
            1. 6.14.3.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.14.3.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      4. 6.14.4 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.14.4.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.14.4.2 ADCSOCAO or ADCSOCBO Timing Diagram
      5. 6.14.5 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.14.5.1 HRPWM Electrical Data and Timing
          1. 6.14.5.1.1 High-Resolution PWM Characteristics
      6. 6.14.6 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.14.6.1 eQEP Electrical Data and Timing
          1. 6.14.6.1.1 eQEP Timing Requirements
          2. 6.14.6.1.2 eQEP Switching Characteristics
      7. 6.14.7 Sigma-Delta Filter Module (SDFM)
        1. 6.14.7.1 SDFM Electrical Data and Timing
          1. 6.14.7.1.1 SDFM Timing Requirements When Using Asynchronous GPIO ASYNC Option
    15. 6.15 C28x Communications Peripherals
      1. 6.15.1  Controller Area Network (CAN)
      2. 6.15.2  Modular Controller Area Network (MCAN)
      3. 6.15.3  Fast Serial Interface (FSI)
        1. 6.15.3.1 FSI Transmitter
          1. 6.15.3.1.1 FSITX Electrical Data and Timing
            1. 6.15.3.1.1.1 FSITX Switching Characteristics
            2. 6.15.3.1.1.2 FSITX Timings
        2. 6.15.3.2 FSI Receiver
          1. 6.15.3.2.1 FSIRX Electrical Data and Timing
            1. 6.15.3.2.1.1 FSIRX Timing Requirements
            2. 6.15.3.2.1.2 FSIRX Switching Characteristics
            3. 6.15.3.2.1.3 FSIRX Timings
        3. 6.15.3.3 FSI SPI Compatibility Mode
          1. 6.15.3.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.15.3.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.15.3.3.1.2 FSITX SPI Signaling Mode Timings
      4. 6.15.4  Inter-Integrated Circuit (I2C)
        1. 6.15.4.1 I2C Electrical Data and Timing
          1. 6.15.4.1.1 I2C Timing Requirements
          2. 6.15.4.1.2 I2C Switching Characteristics
          3. 6.15.4.1.3 I2C Timing Diagram
      5. 6.15.5  Power Management Bus (PMBus) Interface
        1. 6.15.5.1 PMBus Electrical Data and Timing
          1. 6.15.5.1.1 PMBus Electrical Characteristics
          2. 6.15.5.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.15.5.1.3 PMBus Standard Mode Switching Characteristics
      6. 6.15.6  Serial Communications Interface (SCI)
      7. 6.15.7  Serial Peripheral Interface (SPI)
        1. 6.15.7.1 SPI Controller Mode Timings
          1. 6.15.7.1.1 SPI Controller Mode Switching Characteristics Clock Phase 0
          2. 6.15.7.1.2 SPI Controller Mode Switching Characteristics Clock Phase 1
          3. 6.15.7.1.3 SPI Controller Mode Timing Requirements
          4. 6.15.7.1.4 SPI Controller Mode Timing Diagrams
        2. 6.15.7.2 SPI Peripheral Mode Timings
          1. 6.15.7.2.1 SPI Peripheral Mode Switching Characteristics
          2. 6.15.7.2.2 SPI Peripheral Mode Timing Requirements
          3. 6.15.7.2.3 SPI Peripheral Mode Timing Diagrams
      8. 6.15.8  Local Interconnect Network (LIN)
      9. 6.15.9  EtherCAT SubordinateDevice Controller (ESC)
        1. 6.15.9.1 ESC Features
        2. 6.15.9.2 ESC Subsystem Integrated Features
        3. 6.15.9.3 EtherCAT IP Block Diagram
        4. 6.15.9.4 EtherCAT Electrical Data and Timing
          1. 6.15.9.4.1 EtherCAT Timing Requirements
          2. 6.15.9.4.2 EtherCAT Switching Characteristics
          3. 6.15.9.4.3 EtherCAT Timing Diagrams
      10. 6.15.10 Universal Serial Bus (USB)
        1. 6.15.10.1 USB Electrical Data and Timing
          1. 6.15.10.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.15.10.1.2 USB Output Ports DP and DM Switching Characteristics
      11. 6.15.11 Universal Asynchronous Receiver-Transmitter (UART)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Memory
      1. 7.3.1 C28x Memory Map
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 EMIF Chip Select Memory Map
      5. 7.3.5 Peripheral Registers Memory Map
      6. 7.3.6 Memory Types
        1. 7.3.6.1 Dedicated RAM (Mx and Dx RAM)
        2. 7.3.6.2 Local Shared RAM (LSx RAM)
        3. 7.3.6.3 Global Shared RAM (GSx RAM)
        4. 7.3.6.4 CPU Message RAM (CPU MSGRAM)
        5. 7.3.6.5 CLA Message RAM (CLA MSGRAM)
        6. 7.3.6.6 CLA - DMA Message RAM (CLA-DMA MSGRAM)
    4. 7.4 Identification
    5. 7.5 Bus Architecture – Peripheral Connectivity
    6. 7.6 Boot ROM
      1. 7.6.1 Device Boot
      2. 7.6.2 Device Boot Modes
      3. 7.6.3 Device Boot Configurations
      4. 7.6.4 GPIO Assignments
    7. 7.7 Security
      1. 7.7.1 Securing the Boundary of the Chip
        1. 7.7.1.1 JTAGLOCK
        2. 7.7.1.2 Zero-pin Boot
      2. 7.7.2 Dual-Zone Security
      3. 7.7.3 Disclaimer
    8. 7.8 Advanced Encryption Standard (AES) Accelerator
    9. 7.9 C28x (CPU1/CPU2) Subsystem
      1. 7.9.1  C28x Processor
        1. 7.9.1.1 Floating-Point Unit (FPU)
        2. 7.9.1.2 Fast Integer Division Unit
        3. 7.9.1.3 Trigonometric Math Unit (TMU)
        4. 7.9.1.4 VCRC Unit
        5. 7.9.1.5 Lockstep Compare Module (LCM)
      2. 7.9.2  Control Law Accelerator (CLA)
      3. 7.9.3  Embedded Real-Time Analysis and Diagnostic (ERAD)
      4. 7.9.4  Background CRC-32 (BGCRC)
      5. 7.9.5  Direct Memory Access (DMA)
      6. 7.9.6  Interprocessor Communication (IPC) Module
      7. 7.9.7  C28x Timers
      8. 7.9.8  Dual-Clock Comparator (DCC)
        1. 7.9.8.1 Features
        2. 7.9.8.2 Mapping of DCCx Clock Source Inputs
      9. 7.9.9  Nonmaskable Interrupt With Watchdog Timer (NMIWD)
      10. 7.9.10 Watchdog
      11. 7.9.11 Configurable Logic Block (CLB)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 Servo Drive Control Module
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Servo Drive Control Module Resources
        2. 8.3.1.2 Solar Micro Inverter
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 Solar Micro Inverter Resources
        3. 8.3.1.3 EV Charging Station Power Module
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 EV Charging Station Power Module Resources
        4. 8.3.1.4 On-Board Charger (OBC)
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 OBC Resources
        5. 8.3.1.5 High-Voltage Traction Inverter
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 High-Voltage Traction Inverter Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZP|100
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.2 Pin Attributes

Table 5-1 Pin Attributes
SIGNAL NAME MUX POSITION 256 ZEJ 176 PTP 169 NMR 100 PZP PIN TYPE DESCRIPTION
ANALOG
A0 P1 43 L3 25 I ADC-A Input 0
CMP1_HP1 I CMPSS-1 High Comparator Positive Input 1
CMP1_LP1 I CMPSS-1 Low Comparator Positive Input 1
CMP9_HN0 I CMPSS-9 High Comparator Negative Input 0
CMP9_LN0 I CMPSS-9 Low Comparator Negative Input 0
DACA_OUT O Buffered DAC-A Output.
AIO227 0, 4, 8, 12 I Analog Pin Used For Digital Input 227
A1 P2 42 K3 24 I ADC-A Input 1
CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1
CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2
CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1
CMP1_LP2 I CMPSS-1 Low Comparator Positive Input 2
AIO228 0, 4, 8, 12 I Analog Pin Used For Digital Input 228
A2 N3 41 J3 23 I ADC-A Input 2
CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0
CMP1_LP0 I CMPSS-1 Low Comparator Positive Input 0
CMP2_HN1 I CMPSS-2 High Comparator Negative Input 1
CMP2_LN1 I CMPSS-2 Low Comparator Negative Input 1
AIO229 0, 4, 8, 12 I Analog Pin Used For Digital Input 229
A3 N4 40 H3 22 I ADC-A Input 3
CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0
CMP1_HP3 I CMPSS-1 High Comparator Positive Input 3
CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0
AIO230 0, 4, 8, 12 I Analog Pin Used For Digital Input 230
A4 M4 39 H2 21 I ADC-A Input 4
CMP2_HP0 I CMPSS-2 High Comparator Positive Input 0
CMP2_LP0 I CMPSS-2 Low Comparator Positive Input 0
AIO231 0, 4, 8, 12 I Analog Pin Used For Digital Input 231
A5 M5 38 H1 20 I ADC-A Input 5
CMP2_HN0 I CMPSS-2 High Comparator Negative Input 0
CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3
CMP2_LN0 I CMPSS-2 Low Comparator Negative Input 0
CMP9_LP2 I CMPSS-9 Low Comparator Positive Input 2
AIO232 0, 4, 8, 12 I Analog Pin Used For Digital Input 232
A6 N6 57 J5 38 I ADC-A Input 6
CMP7_HP0 I CMPSS-7 High Comparator Positive Input 0
CMP7_LP0 I CMPSS-7 Low Comparator Positive Input 0
GPIO209 I/O General-Purpose Input Output 209 This pin also has digital mux functions which are described in the GPIO section of this table.
A7 P6 58 K5 I ADC-A Input 7
CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3
CMP7_HN0 I CMPSS-7 High Comparator Negative Input 0
CMP7_LN0 I CMPSS-7 Low Comparator Negative Input 0
CMP9_HP2 I CMPSS-9 High Comparator Positive Input 2
GPIO210 I/O General-Purpose Input Output 210 This pin also has digital mux functions which are described in the GPIO section of this table.
A8 R6 59 J6 I ADC-A Input 8
CMP8_HP0 I CMPSS-8 High Comparator Positive Input 0
CMP8_LP0 I CMPSS-8 Low Comparator Positive Input 0
GPIO211 I/O General-Purpose Input Output 211 This pin also has digital mux functions which are described in the GPIO section of this table.
A9 T7 60 K6 I ADC-A Input 9
CMP5_LP3 I CMPSS-5 Low Comparator Positive Input 3
CMP8_HN0 I CMPSS-8 High Comparator Negative Input 0
CMP8_LN0 I CMPSS-8 Low Comparator Negative Input 0
GPIO212 I/O General-Purpose Input Output 212 This pin also has digital mux functions which are described in the GPIO section of this table.
A10 T8 62 L5 39 I ADC-A Input 10
CMP8_HN1 I CMPSS-8 High Comparator Negative Input 1
CMP8_HP1 I CMPSS-8 High Comparator Positive Input 1
CMP8_LN1 I CMPSS-8 Low Comparator Negative Input 1
CMP8_LP1 I CMPSS-8 Low Comparator Positive Input 1
GPIO213 I/O General-Purpose Input Output 213 This pin also has digital mux functions which are described in the GPIO section of this table.
A11 R8 63 L6 40 I ADC-A Input 11
CMP8_HP2 I CMPSS-8 High Comparator Positive Input 2
CMP8_LP2 I CMPSS-8 Low Comparator Positive Input 2
GPIO214 I/O General-Purpose Input Output 214 This pin also has digital mux functions which are described in the GPIO section of this table.
A14 R1 44 M1 26 I ADC-A Input 14
B14 I ADC-B Input 14
C14 I ADC-C Input 14
CMP4_HP0 I CMPSS-4 High Comparator Positive Input 0
CMP4_LP0 I CMPSS-4 Low Comparator Positive Input 0
AIO225 0, 4, 8, 12 I Analog Pin Used For Digital Input 225
A15 R2 45 M2 27 I ADC-A Input 15
B15 I ADC-B Input 15
C15 I ADC-C Input 15
CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0
CMP4_HP3 I CMPSS-4 High Comparator Positive Input 3
CMP4_LN0 I CMPSS-4 Low Comparator Negative Input 0
AIO226 0, 4, 8, 12 I Analog Pin Used For Digital Input 226
B0 T2 46 N2 28 I ADC-B Input 0
CMP3_HP1 I CMPSS-3 High Comparator Positive Input 1
CMP3_LP1 I CMPSS-3 Low Comparator Positive Input 1
CMP11_HN0 I CMPSS-11 High Comparator Negative Input 0
CMP11_LN0 I CMPSS-11 Low Comparator Negative Input 0
VDAC I Optional external reference voltage for on-chip DACs.
AIO233 0, 4, 8, 12 I Analog Pin Used For Digital Input 233
B1 T3 47 N3 29 I ADC-B Input 1
CMP3_HP2 I CMPSS-3 High Comparator Positive Input 2
CMP3_LP2 I CMPSS-3 Low Comparator Positive Input 2
DACC_OUT O Buffered DAC-C Output.
AIO234 0, 4, 8, 12 I Analog Pin Used For Digital Input 234
B2 R3 48 M3 30 I ADC-B Input 2
CMP3_HP0 I CMPSS-3 High Comparator Positive Input 0
CMP3_LP0 I CMPSS-3 Low Comparator Positive Input 0
AIO235 0, 4, 8, 12 I Analog Pin Used For Digital Input 235
B3 P3 49 L4 31 I ADC-B Input 3
CMP1_LP3 I CMPSS-1 Low Comparator Positive Input 3
CMP3_HN0 I CMPSS-3 High Comparator Negative Input 0
CMP3_LN0 I CMPSS-3 Low Comparator Negative Input 0
AIO236 0, 4, 8, 12 I Analog Pin Used For Digital Input 236
B4 P7 64 M6 I ADC-B Input 4
CMP5_HN1 I CMPSS-5 High Comparator Negative Input 1
CMP5_HP1 I CMPSS-5 High Comparator Positive Input 1
CMP5_LN1 I CMPSS-5 Low Comparator Negative Input 1
CMP5_LP1 I CMPSS-5 Low Comparator Positive Input 1
GPIO215 I/O General-Purpose Input Output 215 This pin also has digital mux functions which are described in the GPIO section of this table.
B5 N7 65 N6 I ADC-B Input 5
CMP5_HP2 I CMPSS-5 High Comparator Positive Input 2
CMP5_LP2 I CMPSS-5 Low Comparator Positive Input 2
GPIO216 I/O General-Purpose Input Output 216 This pin also has digital mux functions which are described in the GPIO section of this table.
B6 N5 55 J4 36 I ADC-B Input 6
CMP7_HN1 I CMPSS-7 High Comparator Negative Input 1
CMP7_HP1 I CMPSS-7 High Comparator Positive Input 1
CMP7_LN1 I CMPSS-7 Low Comparator Negative Input 1
CMP7_LP1 I CMPSS-7 Low Comparator Positive Input 1
GPIO207 I/O General-Purpose Input Output 207 This pin also has digital mux functions which are described in the GPIO section of this table.
B7 P5 56 K4 37 I ADC-B Input 7
CMP3_HN1 I CMPSS-3 High Comparator Negative Input 1
CMP3_LN1 I CMPSS-3 Low Comparator Negative Input 1
CMP7_HP2 I CMPSS-7 High Comparator Positive Input 2
CMP7_LP2 I CMPSS-7 Low Comparator Positive Input 2
GPIO208 I/O General-Purpose Input Output 208 This pin also has digital mux functions which are described in the GPIO section of this table.
B8 P8 66 M7 I ADC-B Input 8
CMP2_HP1 I CMPSS-2 High Comparator Positive Input 1
CMP2_LP1 I CMPSS-2 Low Comparator Positive Input 1
CMP10_HN0 I CMPSS-10 High Comparator Negative Input 0
CMP10_LN0 I CMPSS-10 Low Comparator Negative Input 0
GPIO217 I/O General-Purpose Input Output 217 This pin also has digital mux functions which are described in the GPIO section of this table.
B9 N8 67 N7 I ADC-B Input 9
CMP2_HP2 I CMPSS-2 High Comparator Positive Input 2
CMP2_LP2 I CMPSS-2 Low Comparator Positive Input 2
CMP9_HN1 I CMPSS-9 High Comparator Negative Input 1
CMP9_LN1 I CMPSS-9 Low Comparator Negative Input 1
GPIO218 I/O General-Purpose Input Output 218 This pin also has digital mux functions which are described in the GPIO section of this table.
B10 R7 61 I ADC-B Input 10
CMP4_HN1 I CMPSS-4 High Comparator Negative Input 1
CMP4_HP1 I CMPSS-4 High Comparator Positive Input 1
CMP4_LN1 I CMPSS-4 Low Comparator Negative Input 1
CMP4_LP1 I CMPSS-4 Low Comparator Positive Input 1
GPIO219 I/O General-Purpose Input Output 219 This pin also has digital mux functions which are described in the GPIO section of this table.
B11 P4 51 I ADC-B Input 11
CMP4_HP2 I CMPSS-4 High Comparator Positive Input 2
CMP4_LP2 I CMPSS-4 Low Comparator Positive Input 2
AIO240 0, 4, 8, 12 I Analog Pin Used For Digital Input 240
B13 R5 I ADC-B Input 13
CMP9_HP0 I CMPSS-9 High Comparator Positive Input 0
CMP9_LP0 I CMPSS-9 Low Comparator Positive Input 0
AIO238 0, 4, 8, 12 I Analog Pin Used For Digital Input 238
C0 H1 22 F1 9 I ADC-C Input 0
CMP6_HN1 I CMPSS-6 High Comparator Negative Input 1
CMP6_HP1 I CMPSS-6 High Comparator Positive Input 1
CMP6_LN1 I CMPSS-6 Low Comparator Negative Input 1
CMP6_LP1 I CMPSS-6 Low Comparator Positive Input 1
GPIO199 I/O General-Purpose Input Output 199 This pin also has digital mux functions which are described in the GPIO section of this table.
C1 J1 23 G1 10 I ADC-C Input 1
CMP6_HP2 I CMPSS-6 High Comparator Positive Input 2
CMP6_LP2 I CMPSS-6 Low Comparator Positive Input 2
GPIO200 I/O General-Purpose Input Output 200 This pin also has digital mux functions which are described in the GPIO section of this table.
C2 L4 31 H4 15 I ADC-C Input 2
CMP6_HP0 I CMPSS-6 High Comparator Positive Input 0
CMP6_LP0 I CMPSS-6 Low Comparator Positive Input 0
AIO237 0, 4, 8, 12 I Analog Pin Used For Digital Input 237
C3 L5 30 H5 14 I ADC-C Input 3
CMP3_LP3 I CMPSS-3 Low Comparator Positive Input 3
CMP6_HN0 I CMPSS-6 High Comparator Negative Input 0
CMP6_LN0 I CMPSS-6 Low Comparator Negative Input 0
GPIO206 I/O General-Purpose Input Output 206 This pin also has digital mux functions which are described in the GPIO section of this table.
C4 M6 29 H6 13 I ADC-C Input 4
CMP5_HP0 I CMPSS-5 High Comparator Positive Input 0
CMP5_LP0 I CMPSS-5 Low Comparator Positive Input 0
CMP10_HN1 I CMPSS-10 High Comparator Negative Input 1
CMP10_LN1 I CMPSS-10 Low Comparator Negative Input 1
GPIO205 I/O General-Purpose Input Output 205 This pin also has digital mux functions which are described in the GPIO section of this table.
C5 L6 28 G6 12 I ADC-C Input 5
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3
CMP5_HN0 I CMPSS-5 High Comparator Negative Input 0
CMP5_LN0 I CMPSS-5 Low Comparator Negative Input 0
GPIO204 I/O General-Purpose Input Output 204 This pin also has digital mux functions which are described in the GPIO section of this table.
C6 K5 27 G5 11 I ADC-C Input 6
CMP10_HP1 I CMPSS-10 High Comparator Positive Input 1
CMP10_LP1 I CMPSS-10 Low Comparator Positive Input 1
GPIO203 I/O General-Purpose Input Output 203 This pin also has digital mux functions which are described in the GPIO section of this table.
C7 K4 26 G4 I ADC-C Input 7
CMP11_HP1 I CMPSS-11 High Comparator Positive Input 1
CMP11_LP1 I CMPSS-11 Low Comparator Positive Input 1
GPIO198 I/O General-Purpose Input Output 198 This pin also has digital mux functions which are described in the GPIO section of this table.
C8 K3 25 G3 I ADC-C Input 8
CMP10_HP2 I CMPSS-10 High Comparator Positive Input 2
CMP10_LP2 I CMPSS-10 Low Comparator Positive Input 2
GPIO202 I/O General-Purpose Input Output 202 This pin also has digital mux functions which are described in the GPIO section of this table.
C9 J2 24 G2 I ADC-C Input 9
CMP11_HP2 I CMPSS-11 High Comparator Positive Input 2
CMP11_LP2 I CMPSS-11 Low Comparator Positive Input 2
GPIO201 I/O General-Purpose Input Output 201 This pin also has digital mux functions which are described in the GPIO section of this table.
C10 L3 I ADC-C Input 10
CMP10_HP0 I CMPSS-10 High Comparator Positive Input 0
CMP10_LP0 I CMPSS-10 Low Comparator Positive Input 0
AIO241 0, 4, 8, 12 I Analog Pin Used For Digital Input 241
C11 K2 I ADC-C Input 11
CMP11_HP0 I CMPSS-11 High Comparator Positive Input 0
CMP11_LP0 I CMPSS-11 Low Comparator Positive Input 0
AIO242 0, 4, 8, 12 I Analog Pin Used For Digital Input 242
C13 K1 I ADC-C Input 13
CMP9_HP1 I CMPSS-9 High Comparator Positive Input 1
CMP9_LP1 I CMPSS-9 Low Comparator Positive Input 1
CMP11_HN1 I CMPSS-11 High Comparator Negative Input 1
CMP11_LN1 I CMPSS-11 Low Comparator Negative Input 1
AIO239 0, 4, 8, 12 I Analog Pin Used For Digital Input 239
VREFHIA M2 37 K2 19 I ADC-A high reference. This voltage must be driven into the pin from external circuitry. Place at least a 2.2-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIA and VREFLOA pins. NOTE: Do not load this pin externally
VREFHIB R4 53 M4 34 I ADC-B high reference. This voltage must be driven into the pin from external circuitry. Place at least a 2.2-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIB and VREFLOB pins. NOTE: Do not load this pin externally
VREFHIC L2 35 J2 19 I ADC-C high reference. This voltage must be driven into the pin from external circuitry. Place at least a 2.2-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIC and VREFLOC pins. NOTE: Do not load this pin externally
VREFLOA M1 33 K1 16 I ADC-A Low Reference
VREFLOB T4 50 N4 32 I ADC-B Low Reference
VREFLOC L1 32 J1 16 I ADC-C Low Reference
GPIO
GPIO0 0, 4, 8, 12 F8 160 E7 89 I/O General-Purpose Input Output 0
EPWM1_A 1 O ePWM-1 Output A
CLB_OUTPUTXBAR1 5 O CLB Output X-BAR Output 1
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
EMIF1_A13 9 O External Memory Interface 1 address line 13
ESC_GPI0 10 I EtherCAT General-Purpose Input 0
FSITXA_D0 13 O FSITX-A Primary Data Output
GPIO1 0, 4, 8, 12 A7 161 A6 90 I/O General-Purpose Input Output 1
EPWM1_B 1 O ePWM-1 Output B
CLB_OUTPUTXBAR2 5 O CLB Output X-BAR Output 2
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
EMIF1_A14 9 O External Memory Interface 1 address line 14
ESC_GPI1 10 I EtherCAT General-Purpose Input 1
FSITXA_D1 13 O FSITX-A Optional Additional Data Output
GPIO2 0, 4, 8, 12 B7 162 B6 91 I/O General-Purpose Input Output 2
EPWM2_A 1 O ePWM-2 Output A
OUTPUTXBAR1 5 O Output X-BAR Output 1
I2CB_SDA 6 I/OD I2C-B Open-Drain Bidirectional Data
UARTA_TX 7 I/O UART-A Serial Data Transmit
EMIF1_A15 9 O External Memory Interface 1 address line 15
ESC_GPI2 10 I EtherCAT General-Purpose Input 2
FSITXA_CLK 13 O FSITX-A Output Clock
GPIO3 0, 4, 8, 12 C7 163 C6 92 I/O General-Purpose Input Output 3
EPWM2_B 1 O ePWM-2 Output B
OUTPUTXBAR2 2, 5 O Output X-BAR Output 2
I2CB_SCL 6 I/OD I2C-B Open-Drain Bidirectional Clock
UARTA_RX 7 I/O UART-A Serial Data Receive
ESC_GPI3 10 I EtherCAT General-Purpose Input 3
FSIRXA_D0 13 I FSIRX-A Primary Data Input
GPIO4 0, 4, 8, 12 D7 164 D6 93 I/O General-Purpose Input Output 4
EPWM3_A 1 O ePWM-3 Output A
OUTPUTXBAR3 5 O Output X-BAR Output 3
CANA_TX 6 O CAN-A Transmit
MCANA_TX 9 O CAN/CAN FD-A Transmit
ESC_GPI4 10 I EtherCAT General-Purpose Input 4
FSIRXA_D1 13 I FSIRX-A Optional Additional Data Input
GPIO5 0, 4, 8, 12 E7 165 E6 I/O General-Purpose Input Output 5
EPWM3_B 1 O ePWM-3 Output B
OUTPUTXBAR3 3 O Output X-BAR Output 3
CLB_OUTPUTXBAR3 5 O CLB Output X-BAR Output 3
CANA_RX 6 I CAN-A Receive
MCANA_RX 9 I CAN/CAN FD-A Receive
ESC_GPI5 10 I EtherCAT General-Purpose Input 5
FSIRXA_CLK 13 I FSIRX-A Input Clock
GPIO6 0, 4, 8, 12 F7 166 A5 I/O General-Purpose Input Output 6
EPWM4_A 1 O ePWM-4 Output A
OUTPUTXBAR4 2 O Output X-BAR Output 4
EXTSYNCOUT 3 O External ePWM Synchronization Pulse
EQEP3_A 5 I eQEP-3 Input A
MCANB_TX 6 O CAN/CAN FD-B Transmit
LINA_TX 7 O LIN-A Transmit
EMIF1_DQM0 9 O External Memory Interface 1 Input/output mask for byte 0
ESC_GPI6 10 I EtherCAT General-Purpose Input 6
FSITXB_D0 13 O FSITX-B Primary Data Output
GPIO7 0, 4, 8, 12 A6 167 B5 I/O General-Purpose Input Output 7
EPWM4_B 1 O ePWM-4 Output B
OUTPUTXBAR5 3 O Output X-BAR Output 5
EQEP3_B 5 I eQEP-3 Input B
MCANB_RX 6 I CAN/CAN FD-B Receive
LINA_RX 7 I LIN-A Receive
EMIF1_DQM1 9 O External Memory Interface 1 Input/output mask for byte 1
ESC_GPI7 10 I EtherCAT General-Purpose Input 7
FSITXB_D1 13 O FSITX-B Optional Additional Data Output
GPIO8 0, 4, 8, 12 D1 18 E3 I/O General-Purpose Input Output 8
EPWM5_A 1 O ePWM-5 Output A
EMIF1_RAS 2 O External Memory Interface 1 row address strobe
ADCSOCAO 3 O ADC Start of Conversion A Output for External ADC (from ePWM modules)
EQEP3_STROBE 5 I/O eQEP-3 Strobe
SCIA_TX 6 O SCI-A Transmit Data
CLB_OUTPUTXBAR4 7 O CLB Output X-BAR Output 4
MCANA_TX 9 O CAN/CAN FD-A Transmit
ESC_GPO0 10 O EtherCAT General-Purpose Output 0
FSITXB_CLK 13 O FSITX-B Output Clock
FSITXA_D1 14 O FSITX-A Optional Additional Data Output
FSIRXA_D0 15 I FSIRX-A Primary Data Input
GPIO9 0, 4, 8, 12 E1 19 F3 I/O General-Purpose Input Output 9
EPWM5_B 1 O ePWM-5 Output B
SCIB_TX 2 O SCI-B Transmit Data
OUTPUTXBAR6 3 O Output X-BAR Output 6
EQEP3_INDEX 5 I/O eQEP-3 Index
SCIA_RX 6 I SCI-A Receive Data
ESC_GPO1 10 O EtherCAT General-Purpose Output 1
FSIRXB_D0 13 I FSIRX-B Primary Data Input
FSITXA_D0 14 O FSITX-A Primary Data Output
FSIRXA_CLK 15 I FSIRX-A Input Clock
GPIO10 0, 4, 8, 12 D4 1 B3 100 I/O General-Purpose Input Output 10
EPWM6_A 1 O ePWM-6 Output A
EMIF1_CAS 2 O External Memory Interface 1 column address strobe
ADCSOCBO 3 O ADC Start of Conversion B Output for External ADC (from ePWM modules)
EQEP1_A 5 I eQEP-1 Input A
SCIB_TX 6 O SCI-B Transmit Data
SD4_C1 7 I SDFM-4 Channel 1 Clock Input
MCANA_RX 9 I CAN/CAN FD-A Receive
CLB_OUTPUTXBAR5 10 O CLB Output X-BAR Output 5
ESC_TX0_DATA0 11 O EtherCAT MII Transmit-0 Data-0
FSIRXB_D1 13 I FSIRX-B Optional Additional Data Input
FSITXA_CLK 14 O FSITX-A Output Clock
FSIRXA_D1 15 I FSIRX-A Optional Additional Data Input
GPIO11 0, 4, 8, 12 E4 2 B2 1 I/O General-Purpose Input Output 11
EPWM6_B 1 O ePWM-6 Output B
SCIB_RX 2, 6 I SCI-B Receive Data
OUTPUTXBAR7 3 O Output X-BAR Output 7
EQEP1_B 5 I eQEP-1 Input B
SD4_D1 7 I SDFM-4 Channel 1 Data Input
ESC_GPO3 10 O EtherCAT General-Purpose Output 3
ESC_TX0_DATA1 11 O EtherCAT MII Transmit-0 Data-1
FSIRXB_CLK 13 I FSIRX-B Input Clock
FSIRXA_D1 14 I FSIRX-A Optional Additional Data Input
PMBUSA_ALERT 15 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
GPIO12 0, 4, 8, 12 G4 4 B1 3 I/O General-Purpose Input Output 12
EPWM7_A 1 O ePWM-7 Output A
CLB_OUTPUTXBAR6 2 O CLB Output X-BAR Output 6
ADCSOCAO 3 O ADC Start of Conversion A Output for External ADC (from ePWM modules)
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SCIA_TX 6 O SCI-A Transmit Data
SD4_C2 7 I SDFM-4 Channel 2 Clock Input
EMIF1_A1 9 O External Memory Interface 1 address line 1
ESC_GPO4 10 O EtherCAT General-Purpose Output 4
ESC_TX0_DATA2 11 O EtherCAT MII Transmit-0 Data-2
FSIRXC_D0 13 I FSIRX-C Primary Data Input
FSIRXA_D0 14 I FSIRX-A Primary Data Input
PMBUSA_CTL 15 I/O PMBus-A Control Signal - Target Input/Controller Output
GPIO13 0, 4, 8, 12 A3 5 C1 4 I/O General-Purpose Input Output 13
EPWM7_B 1 O ePWM-7 Output B
CLB_OUTPUTXBAR7 2 O CLB Output X-BAR Output 7
EQEP5_STROBE 3 I/O eQEP-5 Strobe
EQEP1_INDEX 5 I/O eQEP-1 Index
SCIA_RX 6 I SCI-A Receive Data
SD4_D2 7 I SDFM-4 Channel 2 Data Input
EMIF1_CS0n 9 O External Memory Interface 1 chip select 0
ESC_GPO5 10 O EtherCAT General-Purpose Output 5
ESC_TX0_DATA3 11 O EtherCAT MII Transmit-0 Data-3
FSIRXC_D1 13 I FSIRX-C Optional Additional Data Input
FSIRXA_CLK 14 I FSIRX-A Input Clock
PMBUSA_SDA 15 I/OD PMBus-A Open-Drain Bidirectional Data
GPIO14 0, 4, 8, 12 B3 6 C2 5 I/O General-Purpose Input Output 14
EPWM8_A 1 O ePWM-8 Output A
SCIB_TX 2 O SCI-B Transmit Data
EQEP5_INDEX 3 I/O eQEP-5 Index
LINA_TX 5 O LIN-A Transmit
OUTPUTXBAR3 6 O Output X-BAR Output 3
OUTPUTXBAR8 7 O Output X-BAR Output 8
ESC_GPO6 10 O EtherCAT General-Purpose Output 6
ESC_PHY1_LINKSTATUS 11 I EtherCAT PHY-1 Link Status
FSIRXC_CLK 13 I FSIRX-C Input Clock
EMIF1_D17 14 I/O External Memory Interface 1 data line 17
PMBUSA_SCL 15 I/OD PMBus-A Open-Drain Bidirectional Clock
GPIO15 0, 4, 8, 12 C3 7 C3 6 I/O General-Purpose Input Output 15
EPWM8_B 1 O ePWM-8 Output B
SCIB_RX 2 I SCI-B Receive Data
LINA_RX 5 I LIN-A Receive
OUTPUTXBAR4 6 O Output X-BAR Output 4
CLB_OUTPUTXBAR8 7 O CLB Output X-BAR Output 8
ESC_GPO7 10 O EtherCAT General-Purpose Output 7
EQEP5_A 11 I eQEP-5 Input A
FSIRXD_D0 13 I FSIRX-D Primary Data Input
EMIF1_DQM2 15 O External Memory Interface 1 Input/output mask for byte 2
GPIO16 0, 4, 8, 12 D3 8 C4 I/O General-Purpose Input Output 16
SPIA_PICO 1 I/O SPI-A Peripheral In, Controller Out (PICO)
OUTPUTXBAR7 3 O Output X-BAR Output 7
EPWM9_A 5 O ePWM-9 Output A
SD1_D1 7 I SDFM-1 Channel 1 Data Input
EQEP5_B 11 I eQEP-5 Input B
FSIRXD_D1 13 I FSIRX-D Optional Additional Data Input
ESC_RX1_CLK 15 I EtherCAT MII Receive-1 Clock
GPIO17 0, 4, 8, 12 E3 9 D4 I/O General-Purpose Input Output 17
SPIA_POCI 1 I/O SPI-A Peripheral Out, Controller In (POCI)
OUTPUTXBAR8 3 O Output X-BAR Output 8
EPWM9_B 5 O ePWM-9 Output B
SD1_C1 7 I SDFM-1 Channel 1 Clock Input
EQEP5_STROBE 11 I/O eQEP-5 Strobe
FSIRXD_CLK 13 I FSIRX-D Input Clock
ESC_RX1_DV 15 I EtherCAT MII Receive-1 Data Valid
GPIO18 0, 4, 8, 12 F3 10 D3 I/O General-Purpose Input Output 18
SPIA_CLK 1 I/O SPI-A Clock
SCIB_TX 2 O SCI-B Transmit Data
CANA_RX 3 I CAN-A Receive
EPWM10_A 5 O ePWM-10 Output A
SD1_D2 7 I SDFM-1 Channel 2 Data Input
MCANA_RX 9 I CAN/CAN FD-A Receive
EMIF1_CS2n 10 O External Memory Interface 1 chip select 2
EQEP5_INDEX 11 I/O eQEP-5 Index
ESC_RX1_ERR 15 I EtherCAT MII Receive-1 Error
GPIO19 0, 4, 8, 12 B2 12 D1 I/O General-Purpose Input Output 19
SPIA_PTE 1 I/O SPI-A Peripheral Transmit Enable (PTE)
SCIB_RX 2 I SCI-B Receive Data
CANA_TX 3 O CAN-A Transmit
EPWM10_B 5 O ePWM-10 Output B
SD1_C2 7 I SDFM-1 Channel 2 Clock Input
MCANA_TX 9 O CAN/CAN FD-A Transmit
EMIF1_CS3n 10 O External Memory Interface 1 chip select 3
ESC_TX1_DATA3 15 O EtherCAT MII Transmit-1 Data-3
GPIO20 0, 4, 8, 12 C2 13 E1 I/O General-Purpose Input Output 20
EQEP1_A 1 I eQEP-1 Input A
EPWM11_A 5 O ePWM-11 Output A
SD1_D3 7 I SDFM-1 Channel 3 Data Input
MCANB_TX 9 O CAN/CAN FD-B Transmit
EMIF1_BA0 10 O External Memory Interface 1 bank address 0
SPIC_PICO 14 I/O SPI-C Peripheral In, Controller Out (PICO)
ESC_TX1_DATA2 15 O EtherCAT MII Transmit-1 Data-2
GPIO21 0, 4, 8, 12 D2 14 E2 I/O General-Purpose Input Output 21
EQEP1_B 1 I eQEP-1 Input B
EPWM11_B 5 O ePWM-11 Output B
SD1_C3 7 I SDFM-1 Channel 3 Clock Input
MCANB_RX 9 I CAN/CAN FD-B Receive
EMIF1_BA1 10 O External Memory Interface 1 bank address 1
SPIC_POCI 14 I/O SPI-C Peripheral Out, Controller In (POCI)
ESC_TX1_DATA1 15 O EtherCAT MII Transmit-1 Data-1
GPIO22 0, 4, 8, 12 A2 11 D2 I/O General-Purpose Input Output 22
EQEP1_STROBE 1 I/O eQEP-1 Strobe
SCIB_TX 3 O SCI-B Transmit Data
EPWM12_A 5 O ePWM-12 Output A
SPIB_CLK 6 I/O SPI-B Clock
SD1_D4 7 I SDFM-1 Channel 4 Data Input
MCANA_TX 9 O CAN/CAN FD-A Transmit
EMIF1_RAS 10 O External Memory Interface 1 row address strobe
SPIC_CLK 14 I/O SPI-C Clock
ESC_TX1_DATA0 15 O EtherCAT MII Transmit-1 Data-0
GPIO23 0, 4, 8, 12 G1 21 F2 I/O General-Purpose Input Output 23
EQEP1_INDEX 1 I/O eQEP-1 Index
SCIB_RX 3 I SCI-B Receive Data
EPWM12_B 5 O ePWM-12 Output B
SPIB_PTE 6 I/O SPI-B Peripheral Transmit Enable (PTE)
SD1_C4 7 I SDFM-1 Channel 4 Clock Input
MCANA_RX 9 I CAN/CAN FD-A Receive
EMIF1_CAS 10 O External Memory Interface 1 column address strobe
SPIC_PTE 14 I/O SPI-C Peripheral Transmit Enable (PTE)
ESC_PHY_RESETn 15 O EtherCAT PHY Active Low Reset
GPIO24 0, 4, 8, 12 E8 159 D7 I/O General-Purpose Input Output 24
OUTPUTXBAR1 1 O Output X-BAR Output 1
EQEP2_A 2 I eQEP-2 Input A
LINB_TX 5 O LIN-B Transmit
SPIB_PICO 6 I/O SPI-B Peripheral In, Controller Out (PICO)
SD2_D1 7 I SDFM-2 Channel 1 Data Input
PMBUSA_SCL 9 I/OD PMBus-A Open-Drain Bidirectional Clock
EMIF1_DQM0 10 O External Memory Interface 1 Input/output mask for byte 0
EPWM13_A 13 O ePWM-13 Output A
ESC_RX0_DATA1 14 I EtherCAT MII Receive-0 Data-1
ESC_RX0_CLK 15 I EtherCAT MII Receive-0 Clock
GPIO25 0, 4, 8, 12 A10 153 B8 84 I/O General-Purpose Input Output 25
OUTPUTXBAR2 1 O Output X-BAR Output 2
EQEP2_B 2 I eQEP-2 Input B
LINB_RX 5 I LIN-B Receive
SPIB_POCI 6 I/O SPI-B Peripheral Out, Controller In (POCI)
SD2_C1 7 I SDFM-2 Channel 1 Clock Input
PMBUSA_SDA 9 I/OD PMBus-A Open-Drain Bidirectional Data
EMIF1_DQM1 10 O External Memory Interface 1 Input/output mask for byte 1
EQEP5_B 11 I eQEP-5 Input B
EPWM13_B 13 O ePWM-13 Output B
FSITXA_D1 14 O FSITX-A Optional Additional Data Output
ESC_RX0_DV 15 I EtherCAT MII Receive-0 Data Valid
GPIO26 0, 4, 8, 12 L11 82 L10 I/O General-Purpose Input Output 26
OUTPUTXBAR3 1, 5 O Output X-BAR Output 3
EQEP2_INDEX 2 I/O eQEP-2 Index
SPIB_CLK 6 I/O SPI-B Clock
SD2_D2 7 I SDFM-2 Channel 2 Data Input
PMBUSA_ALERT 9 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
EMIF1_DQM2 10 O External Memory Interface 1 Input/output mask for byte 2
ESC_MDIO_CLK 11 O EtherCAT MDIO Clock
EPWM14_A 13 O ePWM-14 Output A
FSITXA_D0 14 O FSITX-A Primary Data Output
ESC_RX0_ERR 15 I EtherCAT MII Receive-0 Error
GPIO27 0, 4, 8, 12 G13 125 D11 I/O General-Purpose Input Output 27
OUTPUTXBAR4 1, 5 O Output X-BAR Output 4
EQEP2_STROBE 2 I/O eQEP-2 Strobe
SPIB_PTE 6 I/O SPI-B Peripheral Transmit Enable (PTE)
SD2_C2 7 I SDFM-2 Channel 2 Clock Input
PMBUSA_CTL 9 I/O PMBus-A Control Signal - Target Input/Controller Output
EMIF1_DQM3 10 O External Memory Interface 1 Input/output mask for byte 3
ESC_MDIO_DATA 11 I/O EtherCAT MDIO Data
EPWM14_B 13 O ePWM-14 Output B
FSITXA_CLK 14 O FSITX-A Output Clock
ESC_RX0_DATA0 15 I EtherCAT MII Receive-0 Data-0
GPIO28 0, 4, 8, 12 N11 74 K8 I/O General-Purpose Input Output 28
SCIA_RX 1 I SCI-A Receive Data
EMIF1_CS4n 2 O External Memory Interface 1 chip select 4
UARTA_RX 3 I/O UART-A Serial Data Receive
OUTPUTXBAR5 5 O Output X-BAR Output 5
EQEP3_A 6 I eQEP-3 Input A
SD2_D3 7 I SDFM-2 Channel 3 Data Input
EMIF1_CS2n 9 O External Memory Interface 1 chip select 2
EPWM15_A 13 O ePWM-15 Output A
ESC_RX0_DATA1 15 I EtherCAT MII Receive-0 Data-1
GPIO29 0, 4, 8, 12 P11 73 L8 I/O General-Purpose Input Output 29
SCIA_TX 1 O SCI-A Transmit Data
EMIF1_SDCKE 2 O External Memory Interface 1 SDRAM clock enable
UARTA_TX 3 I/O UART-A Serial Data Transmit
OUTPUTXBAR6 5 O Output X-BAR Output 6
EQEP3_B 6 I eQEP-3 Input B
SD2_C3 7 I SDFM-2 Channel 3 Clock Input
EMIF1_CS3n 9 O External Memory Interface 1 chip select 3
ESC_LATCH0 10 I EtherCAT Latch Signal Input 0
ESC_I2C_SDA 11 I/OC EtherCAT I2C Data
EPWM15_B 13 O ePWM-15 Output B
ESC_SYNC0 14 O EtherCAT SyncSignal Output 0
ESC_RX0_DATA2 15 I EtherCAT MII Receive-0 Data-2
GPIO30 0, 4, 8, 12 L10 79 L9 48 I/O General-Purpose Input Output 30
CANA_RX 1 I CAN-A Receive
EMIF1_CLK 2 O External Memory Interface 1 clock
MCANA_RX 3 I CAN/CAN FD-A Receive
OUTPUTXBAR7 5 O Output X-BAR Output 7
EQEP3_STROBE 6 I/O eQEP-3 Strobe
SD2_D4 7 I SDFM-2 Channel 4 Data Input
EMIF1_CS4n 9 O External Memory Interface 1 chip select 4
ESC_LATCH1 10 I EtherCAT Latch Signal Input 1
ESC_I2C_SCL 11 I/OC EtherCAT I2C Clock
EPWM16_A 13 O ePWM-16 Output A
ESC_SYNC1 14 O EtherCAT SyncSignal Output 1
SPID_PICO 15 I/O SPI-D Peripheral In, Controller Out (PICO)
GPIO31 0, 4, 8, 12 D8 158 I/O General-Purpose Input Output 31
CANA_TX 1 O CAN-A Transmit
EMIF1_WEn 2 O External Memory Interface 1 write enable
MCANA_TX 3 O CAN/CAN FD-A Transmit
OUTPUTXBAR8 5 O Output X-BAR Output 8
EQEP3_INDEX 6 I/O eQEP-3 Index
SD2_C4 7 I SDFM-2 Channel 4 Clock Input
EMIF1_RNW 9 O External Memory Interface 1 read not write
I2CA_SDA 10 I/OD I2C-A Open-Drain Bidirectional Data
EPWM16_B 13 O ePWM-16 Output B
SPID_POCI 15 I/O SPI-D Peripheral Out, Controller In (POCI)
GPIO32 0, 4, 8, 12 J14 116 F12 I/O General-Purpose Input Output 32
I2CA_SDA 1 I/OD I2C-A Open-Drain Bidirectional Data
EMIF1_CS0n 2 O External Memory Interface 1 chip select 0
SPIA_PICO 3 I/O SPI-A Peripheral In, Controller Out (PICO)
EQEP4_A 5 I eQEP-4 Input A
LINB_TX 6 O LIN-B Transmit
CLB_OUTPUTXBAR1 7 O CLB Output X-BAR Output 1
EMIF1_OEn 9 O External Memory Interface 1 output enable
I2CA_SCL 10 I/OD I2C-A Open-Drain Bidirectional Clock
SPID_CLK 15 I/O SPI-D Clock
GPIO33 0, 4, 8, 12 R10 69 L7 I/O General-Purpose Input Output 33
I2CA_SCL 1 I/OD I2C-A Open-Drain Bidirectional Clock
EMIF1_RNW 2 O External Memory Interface 1 read not write
SPIA_POCI 3 I/O SPI-A Peripheral Out, Controller In (POCI)
EQEP4_B 5 I eQEP-4 Input B
CLB_OUTPUTXBAR2 7 O CLB Output X-BAR Output 2
EMIF1_BA0 9 O External Memory Interface 1 bank address 0
ESC_LED_ERR 11 O EtherCAT Error LED
SPID_PTE 15 I/O SPI-D Peripheral Transmit Enable (PTE)
GPIO34 0, 4, 8, 12 P10 70 K7 42 I/O General-Purpose Input Output 34
OUTPUTXBAR1 1 O Output X-BAR Output 1
EMIF1_CS2n 2 O External Memory Interface 1 chip select 2
SPIA_CLK 3 I/O SPI-A Clock
EQEP4_STROBE 5 I/O eQEP-4 Strobe
I2CB_SDA 6 I/OD I2C-B Open-Drain Bidirectional Data
CLB_OUTPUTXBAR3 7 O CLB Output X-BAR Output 3
EMIF1_BA1 9 O External Memory Interface 1 bank address 1
ESC_LATCH0 10 I EtherCAT Latch Signal Input 0
EPWM18_A 11 O ePWM-18 Output A
SCIA_TX 13 O SCI-A Transmit Data
ESC_SYNC0 14 O EtherCAT SyncSignal Output 0
GPIO35 0, 4, 8, 12 N10 71 N8 43 I/O General-Purpose Input Output 35
SCIA_RX 1, 13 I SCI-A Receive Data
EMIF1_CS3n 2 O External Memory Interface 1 chip select 3
SPIA_PTE 3 I/O SPI-A Peripheral Transmit Enable (PTE)
EQEP4_INDEX 5 I/O eQEP-4 Index
I2CB_SCL 6 I/OD I2C-B Open-Drain Bidirectional Clock
CLB_OUTPUTXBAR4 7 O CLB Output X-BAR Output 4
EMIF1_A0 9 O External Memory Interface 1 address line 0
ESC_LATCH1 10 I EtherCAT Latch Signal Input 1
EPWM18_B 11 O ePWM-18 Output B
ESC_SYNC1 14 O EtherCAT SyncSignal Output 1
GPIO36 0, 4, 8, 12 P12 83 N11 I/O General-Purpose Input Output 36
SCIA_TX 1 O SCI-A Transmit Data
EMIF1_WAIT 2 I External Memory Interface 1 Asynchronous SRAM WAIT
CANA_RX 6 I CAN-A Receive
CLB_OUTPUTXBAR5 7 O CLB Output X-BAR Output 5
EMIF1_A1 9 O External Memory Interface 1 address line 1
MCANA_RX 10 I CAN/CAN FD-A Receive
SD1_D1 13 I SDFM-1 Channel 1 Data Input
EMIF1_WEn 14 O External Memory Interface 1 write enable
GPIO37 0, 4, 8, 12 N12 84 M11 I/O General-Purpose Input Output 37
OUTPUTXBAR2 1 O Output X-BAR Output 2
EMIF1_OEn 2 O External Memory Interface 1 output enable
EPWM18_A 3 O ePWM-18 Output A
CANA_TX 6 O CAN-A Transmit
CLB_OUTPUTXBAR6 7 O CLB Output X-BAR Output 6
EMIF1_A2 9 O External Memory Interface 1 address line 2
MCANA_TX 10 O CAN/CAN FD-A Transmit
SD1_D2 13 I SDFM-1 Channel 2 Data Input
EMIF1_D24 14 I/O External Memory Interface 1 data line 24
GPIO38 0, 4, 8, 12 M12 85 L11 I/O General-Purpose Input Output 38
EMIF1_A0 2 O External Memory Interface 1 address line 0
EPWM18_B 3 O ePWM-18 Output B
UARTA_TX 5 I/O UART-A Serial Data Transmit
SCIB_TX 6 O SCI-B Transmit Data
CLB_OUTPUTXBAR7 7 O CLB Output X-BAR Output 7
EMIF1_A3 9 O External Memory Interface 1 address line 3
SD1_D3 13 I SDFM-1 Channel 3 Data Input
EMIF1_CS2n 14 O External Memory Interface 1 chip select 2
GPIO39 0, 4, 8, 12 L12 86 I/O General-Purpose Input Output 39
EMIF1_A1 2 O External Memory Interface 1 address line 1
UARTA_RX 5 I/O UART-A Serial Data Receive
SCIB_RX 6 I SCI-B Receive Data
CLB_OUTPUTXBAR8 7 O CLB Output X-BAR Output 8
EMIF1_A4 9 O External Memory Interface 1 address line 4
ESC_MDIO_DATA 10 I/O EtherCAT MDIO Data
ESC_LED_RUN 11 O EtherCAT Run LED
SD1_D4 13 I SDFM-1 Channel 4 Data Input
FSIRXD_CLK 14 I FSIRX-D Input Clock
GPIO40 0, 4, 8, 12 P13 87 N12 I/O General-Purpose Input Output 40
EMIF1_A2 2 O External Memory Interface 1 address line 2
EPWM13_A 3 O ePWM-13 Output A
MCANB_RX 5 I CAN/CAN FD-B Receive
I2CB_SDA 6 I/OD I2C-B Open-Drain Bidirectional Data
SD4_C3 7 I SDFM-4 Channel 3 Clock Input
ESC_GPO2 9 O EtherCAT General-Purpose Output 2
CLB_OUTPUTXBAR1 10 O CLB Output X-BAR Output 1
SD2_C1 13 I SDFM-2 Channel 1 Clock Input
ESC_I2C_SDA 14 I/OC EtherCAT I2C Data
GPIO41 0, 4, 8, 12 R15 89 M12 51 I/O General-Purpose Input Output 41
EMIF1_A3 2 O External Memory Interface 1 address line 3
EPWM13_B 3 O ePWM-13 Output B
MCANB_TX 5 O CAN/CAN FD-B Transmit
I2CB_SCL 6 I/OD I2C-B Open-Drain Bidirectional Clock
SD4_D3 7 I SDFM-4 Channel 3 Data Input
CLB_OUTPUTXBAR2 10 O CLB Output X-BAR Output 2
SD2_D1 13 I SDFM-2 Channel 1 Data Input
ESC_I2C_SCL 14 I/OC EtherCAT I2C Clock
FSIRXD_CLK 15 I FSIRX-D Input Clock
GPIO42 0, 4, 8, 12 E16 130 C12 73 I/O General-Purpose Input Output 42
EPWM14_A 3 O ePWM-14 Output A
EQEP4_A 5 I eQEP-4 Input A
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
SD4_C4 7 I SDFM-4 Channel 4 Clock Input
CLB_OUTPUTXBAR5 10 O CLB Output X-BAR Output 5
UARTA_TX 11 I/O UART-A Serial Data Transmit
FSIRXD_D0 14 I FSIRX-D Primary Data Input
SCIA_TX 15 O SCI-A Transmit Data
USB0DM ALT O USB-0 PHY differential data
GPIO43 0, 4, 8, 12 D16 131 C11 74 I/O General-Purpose Input Output 43
EPWM14_B 3 O ePWM-14 Output B
EQEP4_B 5 I eQEP-4 Input B
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
SD4_D4 7 I SDFM-4 Channel 4 Data Input
CLB_OUTPUTXBAR6 10 O CLB Output X-BAR Output 6
UARTA_RX 11 I/O UART-A Serial Data Receive
FSIRXD_D1 14 I FSIRX-D Optional Additional Data Input
SCIA_RX 15 I SCI-A Receive Data
USB0DP ALT O USB-0 PHY differential data
GPIO44 0, 4, 8, 12 J12 113 F10 I/O General-Purpose Input Output 44
SPID_POCI 1 I/O SPI-D Peripheral Out, Controller In (POCI)
EMIF1_A4 2 O External Memory Interface 1 address line 4
MCANB_RX 3 I CAN/CAN FD-B Receive
SD3_C4 6 I SDFM-3 Channel 4 Clock Input
UARTB_TX 7 I/O UART-B Serial Data Transmit
CLB_OUTPUTXBAR6 10 O CLB Output X-BAR Output 6
FSIRXD_CLK 13 I FSIRX-D Input Clock
ESC_TX1_CLK 14 I EtherCAT MII Transmit-1 Clock
GPIO45 0, 4, 8, 12 J13 115 F11 I/O General-Purpose Input Output 45
SPID_PTE 1 I/O SPI-D Peripheral Transmit Enable (PTE)
EMIF1_A5 2 O External Memory Interface 1 address line 5
MCANB_TX 3 O CAN/CAN FD-B Transmit
SD3_D4 6 I SDFM-3 Channel 4 Data Input
UARTB_RX 7 I/O UART-B Serial Data Receive
CLB_OUTPUTXBAR7 10 O CLB Output X-BAR Output 7
ESC_TX1_ENA 14 I/O EtherCAT MII Transmit-1 Enable
GPIO46 0, 4, 8, 12 F14 128 71 I/O General-Purpose Input Output 46
EPWM4_A 1 O ePWM-4 Output A
EMIF1_A6 2 O External Memory Interface 1 address line 6
EPWM14_A 3 O ePWM-14 Output A
SCIA_RX 6 I SCI-A Receive Data
SD3_C4 7 I SDFM-3 Channel 4 Clock Input
ESC_MDIO_CLK 14 O EtherCAT MDIO Clock
GPIO47 0, 4, 8, 12 E14 129 72 I/O General-Purpose Input Output 47
EPWM4_B 1 O ePWM-4 Output B
EMIF1_A7 2 O External Memory Interface 1 address line 7
EPWM14_B 3 O ePWM-14 Output B
SCIA_TX 6 O SCI-A Transmit Data
SD4_C3 7 I SDFM-4 Channel 3 Clock Input
ESC_MDIO_DATA 14 I/O EtherCAT MDIO Data
GPIO48 0, 4, 8, 12 R16 90 M13 I/O General-Purpose Input Output 48
OUTPUTXBAR3 1 O Output X-BAR Output 3
EMIF1_A8 2 O External Memory Interface 1 address line 8
SCIA_TX 6 O SCI-A Transmit Data
SD1_D1 7 I SDFM-1 Channel 1 Data Input
SD2_C2 13 I SDFM-2 Channel 2 Clock Input
ESC_PHY_CLK 14 O EtherCAT PHY Clock
GPIO49 0, 4, 8, 12 P15 93 L13 I/O General-Purpose Input Output 49
OUTPUTXBAR4 1 O Output X-BAR Output 4
EMIF1_A9 2 O External Memory Interface 1 address line 9
SCIA_RX 6 I SCI-A Receive Data
SD1_C1 7 I SDFM-1 Channel 1 Clock Input
EMIF1_A5 9 O External Memory Interface 1 address line 5
SD2_D1 13 I SDFM-2 Channel 1 Data Input
FSITXA_D0 14 O FSITX-A Primary Data Output
GPIO50 0, 4, 8, 12 P14 94 K9 I/O General-Purpose Input Output 50
EQEP1_A 1 I eQEP-1 Input A
EMIF1_A10 2 O External Memory Interface 1 address line 10
EPWM15_A 3 O ePWM-15 Output A
SPIC_PICO 6 I/O SPI-C Peripheral In, Controller Out (PICO)
SD1_D2 7 I SDFM-1 Channel 2 Data Input
EMIF1_A6 9 O External Memory Interface 1 address line 6
ESC_LATCH0 11 I EtherCAT Latch Signal Input 0
SD2_D2 13 I SDFM-2 Channel 2 Data Input
FSITXA_D1 14 O FSITX-A Optional Additional Data Output
GPIO51 0, 4, 8, 12 N14 95 K10 I/O General-Purpose Input Output 51
EQEP1_B 1 I eQEP-1 Input B
EMIF1_A11 2 O External Memory Interface 1 address line 11
EPWM15_B 3 O ePWM-15 Output B
SPIC_POCI 6 I/O SPI-C Peripheral Out, Controller In (POCI)
SD1_C2 7 I SDFM-1 Channel 2 Clock Input
EMIF1_A7 9 O External Memory Interface 1 address line 7
ESC_LATCH1 11 I EtherCAT Latch Signal Input 1
SD2_D3 13 I SDFM-2 Channel 3 Data Input
FSITXA_CLK 14 O FSITX-A Output Clock
GPIO52 0, 4, 8, 12 N15 96 K11 I/O General-Purpose Input Output 52
EQEP1_STROBE 1 I/O eQEP-1 Strobe
EMIF1_A12 2 O External Memory Interface 1 address line 12
EPWM16_A 3 O ePWM-16 Output A
SPIC_CLK 6 I/O SPI-C Clock
SD1_D3 7 I SDFM-1 Channel 3 Data Input
EMIF1_A8 9 O External Memory Interface 1 address line 8
ESC_MDIO_CLK 11 O EtherCAT MDIO Clock
SD2_D4 13 I SDFM-2 Channel 4 Data Input
FSIRXA_D0 14 I FSIRX-A Primary Data Input
GPIO53 0, 4, 8, 12 N16 97 K12 I/O General-Purpose Input Output 53
EQEP1_INDEX 1 I/O eQEP-1 Index
EMIF1_D31 2 I/O External Memory Interface 1 data line 31
SPIC_PTE 6 I/O SPI-C Peripheral Transmit Enable (PTE)
SD1_C3 7 I SDFM-1 Channel 3 Clock Input
EMIF1_A9 9 O External Memory Interface 1 address line 9
ESC_MDIO_DATA 11 I/O EtherCAT MDIO Data
SD1_C1 13 I SDFM-1 Channel 1 Clock Input
FSIRXA_D1 14 I FSIRX-A Optional Additional Data Input
GPIO54 0, 4, 8, 12 M13 98 K13 I/O General-Purpose Input Output 54
SPIA_PICO 1 I/O SPI-A Peripheral In, Controller Out (PICO)
EMIF1_D30 2 I/O External Memory Interface 1 data line 30
EQEP2_A 5 I eQEP-2 Input A
SCIB_TX 6 O SCI-B Transmit Data
SD1_D4 7 I SDFM-1 Channel 4 Data Input
EMIF1_A10 9 O External Memory Interface 1 address line 10
ESC_PHY_CLK 11 O EtherCAT PHY Clock
SD1_C2 13 I SDFM-1 Channel 2 Clock Input
FSIRXA_CLK 14 I FSIRX-A Input Clock
GPIO55 0, 4, 8, 12 M14 100 J13 I/O General-Purpose Input Output 55
SPIA_POCI 1 I/O SPI-A Peripheral Out, Controller In (POCI)
EMIF1_D29 2 I/O External Memory Interface 1 data line 29
EPWM16_B 3 O ePWM-16 Output B
EQEP2_B 5 I eQEP-2 Input B
SCIB_RX 6 I SCI-B Receive Data
SD1_C4 7 I SDFM-1 Channel 4 Clock Input
EMIF1_D0 9 I/O External Memory Interface 1 data line 0
ESC_PHY0_LINKSTATUS 11 I EtherCAT PHY-0 Link Status
SD1_C3 13 I SDFM-1 Channel 3 Clock Input
FSITXB_D0 14 O FSITX-B Primary Data Output
GPIO56 0, 4, 8, 12 M15 101 J12 I/O General-Purpose Input Output 56
SPIA_CLK 1 I/O SPI-A Clock
EMIF1_D28 2 I/O External Memory Interface 1 data line 28
EPWM17_A 3 O ePWM-17 Output A
EQEP2_STROBE 5 I/O eQEP-2 Strobe
SD2_D1 7 I SDFM-2 Channel 1 Data Input
EMIF1_D1 9 I/O External Memory Interface 1 data line 1
I2CA_SDA 10 I/OD I2C-A Open-Drain Bidirectional Data
ESC_TX0_ENA 11 I/O EtherCAT MII Transmit-0 Enable
SD1_C4 13 I SDFM-1 Channel 4 Clock Input
FSITXB_CLK 14 O FSITX-B Output Clock
GPIO57 0, 4, 8, 12 M16 102 J11 I/O General-Purpose Input Output 57
SPIA_PTE 1 I/O SPI-A Peripheral Transmit Enable (PTE)
EMIF1_D27 2 I/O External Memory Interface 1 data line 27
EPWM17_B 3 O ePWM-17 Output B
EQEP2_INDEX 5 I/O eQEP-2 Index
SD2_C1 7 I SDFM-2 Channel 1 Clock Input
EMIF1_D2 9 I/O External Memory Interface 1 data line 2
I2CA_SCL 10 I/OD I2C-A Open-Drain Bidirectional Clock
ESC_TX0_CLK 11 I EtherCAT MII Transmit-0 Clock
SD3_D3 13 I SDFM-3 Channel 3 Data Input
FSITXB_D1 14 O FSITX-B Optional Additional Data Output
GPIO58 0, 4, 8, 12 L13 103 J10 52 I/O General-Purpose Input Output 58
SPIA_PICO 1, 15 I/O SPI-A Peripheral In, Controller Out (PICO)
EMIF1_D26 2 I/O External Memory Interface 1 data line 26
EPWM8_A 3 O ePWM-8 Output A
OUTPUTXBAR1 5 O Output X-BAR Output 1
SPIB_CLK 6 I/O SPI-B Clock
SD2_D2 7 I SDFM-2 Channel 2 Data Input
EMIF1_D3 9 I/O External Memory Interface 1 data line 3
ESC_LED_LINK0_ACTIVE 10 O EtherCAT Link-0 Active
CANA_RX 11 I CAN-A Receive
SD2_C2 13 I SDFM-2 Channel 2 Clock Input
FSIRXB_D0 14 I FSIRX-B Primary Data Input
GPIO59 0, 4, 8, 12 L14 104 H13 53 I/O General-Purpose Input Output 59
EPWM5_A 1 O ePWM-5 Output A
EMIF1_D25 2 I/O External Memory Interface 1 data line 25
EPWM8_B 3 O ePWM-8 Output B
OUTPUTXBAR2 5 O Output X-BAR Output 2
SPIB_PTE 6 I/O SPI-B Peripheral Transmit Enable (PTE)
SD2_C2 7 I SDFM-2 Channel 2 Clock Input
EMIF1_D4 9 I/O External Memory Interface 1 data line 4
ESC_LED_LINK1_ACTIVE 10 O EtherCAT Link-1 Active
CANA_TX 11 O CAN-A Transmit
SD2_C3 13 I SDFM-2 Channel 3 Clock Input
FSIRXB_D1 14 I FSIRX-B Optional Additional Data Input
SPIA_POCI 15 I/O SPI-A Peripheral Out, Controller In (POCI)
GPIO60 0, 4, 8, 12 L15 105 54 I/O General-Purpose Input Output 60
EPWM3_B 1 O ePWM-3 Output B
EMIF1_D24 2 I/O External Memory Interface 1 data line 24
ESC_LATCH0 3 I EtherCAT Latch Signal Input 0
OUTPUTXBAR3 5 O Output X-BAR Output 3
SPIB_PICO 6 I/O SPI-B Peripheral In, Controller Out (PICO)
SD2_D3 7 I SDFM-2 Channel 3 Data Input
EMIF1_D5 9 I/O External Memory Interface 1 data line 5
ESC_LED_ERR 10 O EtherCAT Error LED
SD2_C4 13 I SDFM-2 Channel 4 Clock Input
FSIRXB_CLK 14 I FSIRX-B Input Clock
SPIA_CLK 15 I/O SPI-A Clock
GPIO61 0, 4, 8, 12 K16 107 H11 56 I/O General-Purpose Input Output 61
EPWM17_B 1 O ePWM-17 Output B
EMIF1_D23 2 I/O External Memory Interface 1 data line 23
ESC_LATCH1 3 I EtherCAT Latch Signal Input 1
OUTPUTXBAR4 5 O Output X-BAR Output 4
SPIB_POCI 6 I/O SPI-B Peripheral Out, Controller In (POCI)
SD2_C3 7 I SDFM-2 Channel 3 Clock Input
EMIF1_D6 9 I/O External Memory Interface 1 data line 6
ESC_LED_RUN 10 O EtherCAT Run LED
CANA_RX 14 I CAN-A Receive
SPIA_PTE 15 I/O SPI-A Peripheral Transmit Enable (PTE)
GPIO62 0, 4, 8, 12 K15 108 H10 57 I/O General-Purpose Input Output 62
SCIA_RX 1 I SCI-A Receive Data
EMIF1_D22 2 I/O External Memory Interface 1 data line 22
ESC_MDIO_CLK 3 O EtherCAT MDIO Clock
EQEP3_A 5 I eQEP-3 Input A
CANA_RX 6 I CAN-A Receive
SD2_D4 7 I SDFM-2 Channel 4 Data Input
EMIF1_D7 9 I/O External Memory Interface 1 data line 7
ESC_LED_STATE_RUN 10 O EtherCAT LED State Run
CANA_TX 14 O CAN-A Transmit
GPIO63 0, 4, 8, 12 K14 109 G13 58 I/O General-Purpose Input Output 63
SCIA_TX 1 O SCI-A Transmit Data
EMIF1_D21 2 I/O External Memory Interface 1 data line 21
EPWM9_A 3 O ePWM-9 Output A
EQEP3_B 5 I eQEP-3 Input B
CANA_TX 6 O CAN-A Transmit
SD2_C4 7 I SDFM-2 Channel 4 Clock Input
EMIF1_RNW 9 O External Memory Interface 1 read not write
EMIF1_BA0 10 O External Memory Interface 1 bank address 0
SD1_D1 13 I SDFM-1 Channel 1 Data Input
ESC_RX1_DATA0 14 I EtherCAT MII Receive-1 Data-0
SPIB_PICO 15 I/O SPI-B Peripheral In, Controller Out (PICO)
GPIO64 0, 4, 8, 12 K13 110 G12 59 I/O General-Purpose Input Output 64
EMIF1_D20 2 I/O External Memory Interface 1 data line 20
EPWM9_B 3 O ePWM-9 Output B
EQEP3_STROBE 5 I/O eQEP-3 Strobe
SCIA_RX 6 I SCI-A Receive Data
EMIF1_WAIT 9 I External Memory Interface 1 Asynchronous SRAM WAIT
EMIF1_BA1 10 O External Memory Interface 1 bank address 1
SD1_C1 13 I SDFM-1 Channel 1 Clock Input
ESC_RX1_DATA1 14 I EtherCAT MII Receive-1 Data-1
SPIB_POCI 15 I/O SPI-B Peripheral Out, Controller In (POCI)
GPIO65 0, 4, 8, 12 K12 111 G11 60 I/O General-Purpose Input Output 65
EMIF1_D19 2 I/O External Memory Interface 1 data line 19
EPWM10_A 3 O ePWM-10 Output A
EQEP3_INDEX 5 I/O eQEP-3 Index
SCIA_TX 6 O SCI-A Transmit Data
EMIF1_WEn 9 O External Memory Interface 1 write enable
FSITXB_CLK 11 O FSITX-B Output Clock
SD1_D2 13 I SDFM-1 Channel 2 Data Input
ESC_RX1_DATA2 14 I EtherCAT MII Receive-1 Data-2
SPIB_CLK 15 I/O SPI-B Clock
GPIO66 0, 4, 8, 12 K11 112 G10 61 I/O General-Purpose Input Output 66
EQEP6_B 1 I eQEP-6 Input B
EMIF1_D18 2 I/O External Memory Interface 1 data line 18
EPWM10_B 3 O ePWM-10 Output B
I2CB_SDA 6 I/OD I2C-B Open-Drain Bidirectional Data
EMIF1_OEn 9 O External Memory Interface 1 output enable
FSITXB_D1 11 O FSITX-B Optional Additional Data Output
SD1_C2 13 I SDFM-1 Channel 2 Clock Input
ESC_RX1_DATA3 14 I EtherCAT MII Receive-1 Data-3
SPIB_PTE 15 I/O SPI-B Peripheral Transmit Enable (PTE)
GPIO67 0, 4, 8, 12 D15 132 I/O General-Purpose Input Output 67
EMIF1_D17 2 I/O External Memory Interface 1 data line 17
EPWM17_A 3 O ePWM-17 Output A
LINB_TX 5 O LIN-B Transmit
ESC_I2C_SDA 11 I/OC EtherCAT I2C Data
SD1_D3 13 I SDFM-1 Channel 3 Data Input
GPIO68 0, 4, 8, 12 C16 133 B13 I/O General-Purpose Input Output 68
EMIF1_D16 2 I/O External Memory Interface 1 data line 16
EPWM17_B 3 O ePWM-17 Output B
LINB_RX 5 I LIN-B Receive
ESC_I2C_SCL 11 I/OC EtherCAT I2C Clock
SD1_C3 13 I SDFM-1 Channel 3 Clock Input
ESC_PHY1_LINKSTATUS 14 I EtherCAT PHY-1 Link Status
GPIO69 0, 4, 8, 12 B16 134 B12 75 I/O General-Purpose Input Output 69
EMIF1_D15 2 I/O External Memory Interface 1 data line 15
EPWM11_A 3 O ePWM-11 Output A
I2CB_SCL 6 I/OD I2C-B Open-Drain Bidirectional Clock
FSITXB_D0 11 O FSITX-B Primary Data Output
SD1_D4 13 I SDFM-1 Channel 4 Data Input
ESC_RX1_CLK 14 I EtherCAT MII Receive-1 Clock
SPIC_PICO 15 I/O SPI-C Peripheral In, Controller Out (PICO)
GPIO70 0, 4, 8, 12 C15 135 A12 76 I/O General-Purpose Input Output 70
EMIF1_D14 2 I/O External Memory Interface 1 data line 14
EPWM11_B 3 O ePWM-11 Output B
CANA_RX 5 I CAN-A Receive
SCIB_TX 6 O SCI-B Transmit Data
UARTB_TX 7 I/O UART-B Serial Data Transmit
MCANA_RX 9 I CAN/CAN FD-A Receive
FSIRXB_D0 11 I FSIRX-B Primary Data Input
SD1_C4 13 I SDFM-1 Channel 4 Clock Input
ESC_RX1_DV 14 I EtherCAT MII Receive-1 Data Valid
SPIC_POCI 15 I/O SPI-C Peripheral Out, Controller In (POCI)
GPIO71 0, 4, 8, 12 B15 136 B11 77 I/O General-Purpose Input Output 71
EMIF1_D13 2 I/O External Memory Interface 1 data line 13
EPWM12_A 3 O ePWM-12 Output A
CANA_TX 5 O CAN-A Transmit
SCIB_RX 6 I SCI-B Receive Data
UARTB_RX 7 I/O UART-B Serial Data Receive
MCANA_TX 9 O CAN/CAN FD-A Transmit
SD3_D1 13 I SDFM-3 Channel 1 Data Input
ESC_RX1_ERR 14 I EtherCAT MII Receive-1 Error
SPIC_CLK 15 I/O SPI-C Clock
GPIO72 0, 4, 8, 12 A15 139 A11 80 I/O General-Purpose Input Output 72
EQEP6_STROBE 1 I/O eQEP-6 Strobe
EMIF1_D12 2 I/O External Memory Interface 1 data line 12
EPWM12_B 3 O ePWM-12 Output B
OUTPUTXBAR8 5 O Output X-BAR Output 8
UARTA_TX 6 I/O UART-A Serial Data Transmit
MCANB_RX 9 I CAN/CAN FD-B Receive
SD3_C1 13 I SDFM-3 Channel 1 Clock Input
ESC_TX1_DATA3 14 O EtherCAT MII Transmit-1 Data-3
SPIC_PTE 15 I/O SPI-C Peripheral Transmit Enable (PTE)
GPIO73 0, 4, 8, 12 D14 140 C10 81 I/O General-Purpose Input Output 73
EQEP6_INDEX 1 I/O eQEP-6 Index
EMIF1_D11 2 I/O External Memory Interface 1 data line 11
XCLKOUT 3 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
OUTPUTXBAR6 5 O Output X-BAR Output 6
UARTA_RX 6 I/O UART-A Serial Data Receive
EPWM5_B 7 O ePWM-5 Output B
MCANB_TX 9 O CAN/CAN FD-B Transmit
SD4_D4 10 I SDFM-4 Channel 4 Data Input
SD2_D2 13 I SDFM-2 Channel 2 Data Input
ESC_TX1_DATA2 14 O EtherCAT MII Transmit-1 Data-2
GPIO74 0, 4, 8, 12 C14 141 B10 I/O General-Purpose Input Output 74
EPWM8_A 1 O ePWM-8 Output A
EMIF1_D10 2 I/O External Memory Interface 1 data line 10
EQEP5_A 6 I eQEP-5 Input A
MCANA_TX 9 O CAN/CAN FD-A Transmit
SD1_D4 10 I SDFM-1 Channel 4 Data Input
SD2_C2 13 I SDFM-2 Channel 2 Clock Input
ESC_TX1_DATA1 14 O EtherCAT MII Transmit-1 Data-1
GPIO75 0, 4, 8, 12 B14 142 A10 I/O General-Purpose Input Output 75
EPWM8_B 1 O ePWM-8 Output B
EMIF1_D9 2 I/O External Memory Interface 1 data line 9
EQEP5_B 6 I eQEP-5 Input B
SPID_CLK 7 I/O SPI-D Clock
MCANA_RX 9 I CAN/CAN FD-A Receive
CLB_OUTPUTXBAR8 10 O CLB Output X-BAR Output 8
SD2_D3 13 I SDFM-2 Channel 3 Data Input
ESC_TX1_DATA0 14 O EtherCAT MII Transmit-1 Data-0
GPIO76 0, 4, 8, 12 A14 143 E9 I/O General-Purpose Input Output 76
EPWM9_A 1 O ePWM-9 Output A
EMIF1_D8 2 I/O External Memory Interface 1 data line 8
EQEP5_STROBE 6 I/O eQEP-5 Strobe
SD3_C1 7 I SDFM-3 Channel 1 Clock Input
SD4_D4 10 I SDFM-4 Channel 4 Data Input
SD2_C3 13 I SDFM-2 Channel 3 Clock Input
ESC_PHY_RESETn 14 O EtherCAT PHY Active Low Reset
GPIO77 0, 4, 8, 12 F13 144 D9 I/O General-Purpose Input Output 77
EPWM9_B 1 O ePWM-9 Output B
EMIF1_D7 2 I/O External Memory Interface 1 data line 7
EQEP5_INDEX 6 I/O eQEP-5 Index
SD3_D1 7 I SDFM-3 Channel 1 Data Input
SD1_D4 10 I SDFM-1 Channel 4 Data Input
SD2_D4 13 I SDFM-2 Channel 4 Data Input
ESC_RX0_CLK 14 I EtherCAT MII Receive-0 Clock
GPIO78 0, 4, 8, 12 E13 145 C9 82 I/O General-Purpose Input Output 78
EPWM10_A 1 O ePWM-10 Output A
EMIF1_D6 2 I/O External Memory Interface 1 data line 6
EQEP2_A 6 I eQEP-2 Input A
SD3_C2 7 I SDFM-3 Channel 2 Clock Input
SD4_D4 10 I SDFM-4 Channel 4 Data Input
SD2_C4 13 I SDFM-2 Channel 4 Clock Input
ESC_RX0_DV 14 I EtherCAT MII Receive-0 Data Valid
GPIO79 0, 4, 8, 12 D13 146 B9 I/O General-Purpose Input Output 79
EPWM10_B 1 O ePWM-10 Output B
EMIF1_D5 2 I/O External Memory Interface 1 data line 5
ERRORSTS 5 O Error Status Output. This signal requires an external pulldown.
EQEP2_B 6 I eQEP-2 Input B
SD3_D2 7 I SDFM-3 Channel 2 Data Input
SD2_D1 13 I SDFM-2 Channel 1 Data Input
ESC_RX0_ERR 14 I EtherCAT MII Receive-0 Error
GPIO80 0, 4, 8, 12 A13 148 E8 83 I/O General-Purpose Input Output 80
EPWM11_A 1 O ePWM-11 Output A
EMIF1_D4 2 I/O External Memory Interface 1 data line 4
ERRORSTS 5 O Error Status Output. This signal requires an external pulldown.
EQEP2_STROBE 6 I/O eQEP-2 Strobe
SD3_C3 7 I SDFM-3 Channel 3 Clock Input
SD1_D4 10 I SDFM-1 Channel 4 Data Input
SD2_C1 13 I SDFM-2 Channel 1 Clock Input
ESC_RX0_DATA0 14 I EtherCAT MII Receive-0 Data-0
GPIO81 0, 4, 8, 12 F12 149 I/O General-Purpose Input Output 81
EPWM11_B 1 O ePWM-11 Output B
EMIF1_D3 2 I/O External Memory Interface 1 data line 3
EQEP2_INDEX 6 I/O eQEP-2 Index
SD3_D3 7 I SDFM-3 Channel 3 Data Input
ESC_RX0_DATA1 14 I EtherCAT MII Receive-0 Data-1
GPIO82 0, 4, 8, 12 E12 150 D8 I/O General-Purpose Input Output 82
EPWM12_A 1 O ePWM-12 Output A
EMIF1_D2 2 I/O External Memory Interface 1 data line 2
SD3_C2 13 I SDFM-3 Channel 2 Clock Input
ESC_RX0_DATA2 14 I EtherCAT MII Receive-0 Data-2
GPIO83 0, 4, 8, 12 D12 151 C8 I/O General-Purpose Input Output 83
EPWM12_B 1 O ePWM-12 Output B
EMIF1_D1 2 I/O External Memory Interface 1 data line 1
SD3_D2 13 I SDFM-3 Channel 2 Data Input
ESC_RX0_DATA3 14 I EtherCAT MII Receive-0 Data-3
GPIO84 0, 4, 8, 12 D9 154 A8 85 I/O General-Purpose Input Output 84
EPWM12_B 1 O ePWM-12 Output B
EMIF1_D1 2 I/O External Memory Interface 1 data line 1
EMIF1_CS4n 3 O External Memory Interface 1 chip select 4
SCIA_TX 5 O SCI-A Transmit Data
EQEP6_A 6 I eQEP-6 Input A
SD3_D2 9 I SDFM-3 Channel 2 Data Input
UARTA_TX 11 I/O UART-A Serial Data Transmit
SD3_C2 13 I SDFM-3 Channel 2 Clock Input
ESC_TX0_ENA 14 I/O EtherCAT MII Transmit-0 Enable
ESC_RX0_DATA3 15 I EtherCAT MII Receive-0 Data-3
GPIO85 0, 4, 8, 12 C9 155 A7 86 I/O General-Purpose Input Output 85
EPWM13_A 1 O ePWM-13 Output A
EMIF1_D0 2 I/O External Memory Interface 1 data line 0
SCIA_RX 5 I SCI-A Receive Data
EQEP6_B 6 I eQEP-6 Input B
SD3_D1 7 I SDFM-3 Channel 1 Data Input
UARTA_RX 11 I/O UART-A Serial Data Receive
SD3_D3 13 I SDFM-3 Channel 3 Data Input
ESC_TX0_CLK 14 I EtherCAT MII Transmit-0 Clock
EMIF1_DQM2 15 O External Memory Interface 1 Input/output mask for byte 2
GPIO86 0, 4, 8, 12 B9 156 B7 87 I/O General-Purpose Input Output 86
EPWM13_B 1 O ePWM-13 Output B
EMIF1_A13 2 O External Memory Interface 1 address line 13
EMIF1_CAS 3 O External Memory Interface 1 column address strobe
SCIB_TX 5 O SCI-B Transmit Data
EQEP6_STROBE 6 I/O eQEP-6 Strobe
SD3_C3 13 I SDFM-3 Channel 3 Clock Input
ESC_PHY0_LINKSTATUS 14 I EtherCAT PHY-0 Link Status
GPIO87 0, 4, 8, 12 A9 157 C7 88 I/O General-Purpose Input Output 87
EPWM14_A 1 O ePWM-14 Output A
EMIF1_A14 2 O External Memory Interface 1 address line 14
EMIF1_RAS 3 O External Memory Interface 1 row address strobe
SCIB_RX 5 I SCI-B Receive Data
EQEP6_INDEX 6 I/O eQEP-6 Index
EMIF1_DQM3 9 O External Memory Interface 1 Input/output mask for byte 3
SD3_D4 13 I SDFM-3 Channel 4 Data Input
ESC_TX0_DATA0 14 O EtherCAT MII Transmit-0 Data-0
GPIO88 0, 4, 8, 12 B6 170 C5 I/O General-Purpose Input Output 88
EPWM14_B 1 O ePWM-14 Output B
EMIF1_A15 2 O External Memory Interface 1 address line 15
EMIF1_DQM0 3 O External Memory Interface 1 Input/output mask for byte 0
EMIF1_DQM1 9 O External Memory Interface 1 Input/output mask for byte 1
SD3_C4 13 I SDFM-3 Channel 4 Clock Input
ESC_TX0_DATA1 14 O EtherCAT MII Transmit-0 Data-1
GPIO89 0, 4, 8, 12 C6 171 D5 96 I/O General-Purpose Input Output 89
EPWM15_A 1 O ePWM-15 Output A
EMIF1_A16 2 O External Memory Interface 1 address line 16
EMIF1_DQM1 3 O External Memory Interface 1 Input/output mask for byte 1
SD1_D3 7 I SDFM-1 Channel 3 Data Input
EMIF1_CAS 9 O External Memory Interface 1 column address strobe
SD4_D1 13 I SDFM-4 Channel 1 Data Input
ESC_TX0_DATA2 14 O EtherCAT MII Transmit-0 Data-2
SPID_PTE 15 I/O SPI-D Peripheral Transmit Enable (PTE)
GPIO90 0, 4, 8, 12 D6 172 E5 97 I/O General-Purpose Input Output 90
EPWM15_B 1 O ePWM-15 Output B
EMIF1_A17 2 O External Memory Interface 1 address line 17
EMIF1_DQM2 3 O External Memory Interface 1 Input/output mask for byte 2
SD1_C3 7 I SDFM-1 Channel 3 Clock Input
EMIF1_RAS 9 O External Memory Interface 1 row address strobe
SD4_C1 13 I SDFM-4 Channel 1 Clock Input
ESC_TX0_DATA3 14 O EtherCAT MII Transmit-0 Data-3
SPID_CLK 15 I/O SPI-D Clock
GPIO91 0, 4, 8, 12 E6 173 B4 98 I/O General-Purpose Input Output 91
EPWM16_A 1 O ePWM-16 Output A
EMIF1_A18 2 O External Memory Interface 1 address line 18
EMIF1_DQM3 3 O External Memory Interface 1 Input/output mask for byte 3
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
SD4_D2 7 I SDFM-4 Channel 2 Data Input
EMIF1_DQM2 9 O External Memory Interface 1 Input/output mask for byte 2
PMBUSA_SCL 10 I/OD PMBus-A Open-Drain Bidirectional Clock
CLB_OUTPUTXBAR1 14 O CLB Output X-BAR Output 1
SPID_PICO 15 I/O SPI-D Peripheral In, Controller Out (PICO)
GPIO92 0, 4, 8, 12 A5 174 A4 99 I/O General-Purpose Input Output 92
EPWM16_B 1 O ePWM-16 Output B
EMIF1_A19 2 O External Memory Interface 1 address line 19
EMIF1_BA1 3 O External Memory Interface 1 bank address 1
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
SD4_C2 7 I SDFM-4 Channel 2 Clock Input
EMIF1_DQM0 9 O External Memory Interface 1 Input/output mask for byte 0
PMBUSA_SDA 10 I/OD PMBus-A Open-Drain Bidirectional Data
FSIRXD_CLK 11 I FSIRX-D Input Clock
CLB_OUTPUTXBAR2 14 O CLB Output X-BAR Output 2
SPID_POCI 15 I/O SPI-D Peripheral Out, Controller In (POCI)
GPIO93 0, 4, 8, 12 C5 175 A3 I/O General-Purpose Input Output 93
EPWM17_A 1 O ePWM-17 Output A
EMIF1_BA0 3 O External Memory Interface 1 bank address 0
SD4_D3 7 I SDFM-4 Channel 3 Data Input
PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
ESC_TX1_CLK 11 I EtherCAT MII Transmit-1 Clock
CLB_OUTPUTXBAR3 14 O CLB Output X-BAR Output 3
SPID_CLK 15 I/O SPI-D Clock
GPIO94 0, 4, 8, 12 D5 176 A2 I/O General-Purpose Input Output 94
EPWM17_B 1 O ePWM-17 Output B
SD4_C3 7 I SDFM-4 Channel 3 Clock Input
EMIF1_BA1 9 O External Memory Interface 1 bank address 1
PMBUSA_CTL 10 I/O PMBus-A Control Signal - Target Input/Controller Output
ESC_TX1_ENA 11 I/O EtherCAT MII Transmit-1 Enable
CLB_OUTPUTXBAR4 14 O CLB Output X-BAR Output 4
SPID_PTE 15 I/O SPI-D Peripheral Transmit Enable (PTE)
GPIO95 0, 4, 8, 12 A4 I/O General-Purpose Input Output 95
EPWM18_A 1 O ePWM-18 Output A
EQEP4_A 2 I eQEP-4 Input A
SD1_D1 6 I SDFM-1 Channel 1 Data Input
ESC_GPO10 10 O EtherCAT General-Purpose Output 10
CLB_OUTPUTXBAR5 14 O CLB Output X-BAR Output 5
GPIO96 0, 4, 8, 12 B4 I/O General-Purpose Input Output 96
EPWM18_B 1 O ePWM-18 Output B
EQEP4_B 2 I eQEP-4 Input B
EQEP1_A 5 I eQEP-1 Input A
SD1_C1 6 I SDFM-1 Channel 1 Clock Input
ESC_GPO11 10 O EtherCAT General-Purpose Output 11
CLB_OUTPUTXBAR6 14 O CLB Output X-BAR Output 6
GPIO97 0, 4, 8, 12 C4 I/O General-Purpose Input Output 97
EQEP4_STROBE 2 I/O eQEP-4 Strobe
EQEP1_B 5 I eQEP-1 Input B
SD1_D2 6 I SDFM-1 Channel 2 Data Input
ESC_GPI17 10 I EtherCAT General-Purpose Input 17
CLB_OUTPUTXBAR7 14 O CLB Output X-BAR Output 7
GPIO98 0, 4, 8, 12 E2 I/O General-Purpose Input Output 98
EQEP4_INDEX 2 I/O eQEP-4 Index
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SD1_C2 6 I SDFM-1 Channel 2 Clock Input
ESC_GPI18 10 I EtherCAT General-Purpose Input 18
CLB_OUTPUTXBAR8 14 O CLB Output X-BAR Output 8
GPIO99 0, 4, 8, 12 C1 17 E4 I/O General-Purpose Input Output 99
EMIF1_DQM3 2 O External Memory Interface 1 Input/output mask for byte 3
EPWM8_A 3 O ePWM-8 Output A
EQEP1_INDEX 5 I/O eQEP-1 Index
SD4_D4 7 I SDFM-4 Channel 4 Data Input
ESC_GPI21 10 I EtherCAT General-Purpose Input 21
EMIF1_D17 14 I/O External Memory Interface 1 data line 17
GPIO100 0, 4, 8, 12 F4 2 I/O General-Purpose Input Output 100
SPIA_PICO 1 I/O SPI-A Peripheral In, Controller Out (PICO)
EMIF1_BA1 2 O External Memory Interface 1 bank address 1
EPWM9_A 3 O ePWM-9 Output A
EQEP2_A 5 I eQEP-2 Input A
SPIC_PICO 6 I/O SPI-C Peripheral In, Controller Out (PICO)
SD4_C4 7 I SDFM-4 Channel 4 Clock Input
SD1_D1 9 I SDFM-1 Channel 1 Data Input
ESC_GPI0 10 I EtherCAT General-Purpose Input 0
FSIRXD_D1 11 I FSIRX-D Optional Additional Data Input
FSITXA_D0 13 O FSITX-A Primary Data Output
EMIF1_D24 14 I/O External Memory Interface 1 data line 24
GPIO101 0, 4, 8, 12 N9 I/O General-Purpose Input Output 101
EPWM18_A 1 O ePWM-18 Output A
EQEP2_B 5 I eQEP-2 Input B
SPIC_POCI 6 I/O SPI-C Peripheral Out, Controller In (POCI)
ESC_GPI1 10 I EtherCAT General-Purpose Input 1
EMIF1_A5 11 O External Memory Interface 1 address line 5
FSITXA_D1 13 O FSITX-A Optional Additional Data Output
GPIO102 0, 4, 8, 12 C13 I/O General-Purpose Input Output 102
EPWM18_B 1 O ePWM-18 Output B
EQEP2_STROBE 5 I/O eQEP-2 Strobe
SPIC_CLK 6 I/O SPI-C Clock
ESC_GPI2 10 I EtherCAT General-Purpose Input 2
EMIF1_A6 11 O External Memory Interface 1 address line 6
FSITXA_CLK 13 O FSITX-A Output Clock
GPIO103 0, 4, 8, 12 G12 126 D10 I/O General-Purpose Input Output 103
EMIF1_BA0 2 O External Memory Interface 1 bank address 0
EPWM8_B 3 O ePWM-8 Output B
EQEP2_INDEX 5 I/O eQEP-2 Index
SPIC_PTE 6 I/O SPI-C Peripheral Transmit Enable (PTE)
SD4_C4 7 I SDFM-4 Channel 4 Clock Input
ESC_GPI3 10 I EtherCAT General-Purpose Input 3
FSIRXA_D0 13 I FSIRX-A Primary Data Input
GPIO104 0, 4, 8, 12 B13 147 A9 I/O General-Purpose Input Output 104
I2CA_SDA 1 I/OD I2C-A Open-Drain Bidirectional Data
EPWM18_A 2 O ePWM-18 Output A
EQEP3_A 5 I eQEP-3 Input A
SD3_D1 6 I SDFM-3 Channel 1 Data Input
ESC_GPI4 10 I EtherCAT General-Purpose Input 4
FSIRXA_D1 13 I FSIRX-A Optional Additional Data Input
ESC_SYNC0 14 O EtherCAT SyncSignal Output 0
GPIO105 0, 4, 8, 12 L16 106 H12 I/O General-Purpose Input Output 105
I2CA_SCL 1 I/OD I2C-A Open-Drain Bidirectional Clock
EPWM18_B 2 O ePWM-18 Output B
EQEP3_B 5 I eQEP-3 Input B
SD3_C1 6 I SDFM-3 Channel 1 Clock Input
ESC_GPI5 10 I EtherCAT General-Purpose Input 5
FSIRXA_CLK 13 I FSIRX-A Input Clock
ESC_SYNC1 14 O EtherCAT SyncSignal Output 1
GPIO106 0, 4, 8, 12 F1 20 I/O General-Purpose Input Output 106
EPWM16_A 1 O ePWM-16 Output A
EMIF1_A10 2 O External Memory Interface 1 address line 10
EQEP3_STROBE 5 I/O eQEP-3 Strobe
SD3_D2 6 I SDFM-3 Channel 2 Data Input
ESC_GPI6 10 I EtherCAT General-Purpose Input 6
FSITXB_D0 13 O FSITX-B Primary Data Output
GPIO107 0, 4, 8, 12 F2 I/O General-Purpose Input Output 107
EPWM16_B 1 O ePWM-16 Output B
EQEP3_INDEX 5 I/O eQEP-3 Index
SD3_C2 6 I SDFM-3 Channel 2 Clock Input
ESC_GPI7 10 I EtherCAT General-Purpose Input 7
FSITXB_D1 13 O FSITX-B Optional Additional Data Output
GPIO108 0, 4, 8, 12 G2 I/O General-Purpose Input Output 108
EPWM17_A 1 O ePWM-17 Output A
EMIF1_A12 2 O External Memory Interface 1 address line 12
EQEP5_A 5 I eQEP-5 Input A
SD3_D3 6 I SDFM-3 Channel 3 Data Input
ESC_GPI8 10 I EtherCAT General-Purpose Input 8
FSITXB_CLK 13 O FSITX-B Output Clock
GPIO109 0, 4, 8, 12 G3 I/O General-Purpose Input Output 109
EPWM17_B 1 O ePWM-17 Output B
EMIF1_A11 2 O External Memory Interface 1 address line 11
EQEP5_B 5 I eQEP-5 Input B
SD3_C3 6 I SDFM-3 Channel 3 Clock Input
ESC_GPI9 10 I EtherCAT General-Purpose Input 9
GPIO110 0, 4, 8, 12 H2 I/O General-Purpose Input Output 110
EMIF1_D31 1 I/O External Memory Interface 1 data line 31
EQEP5_STROBE 5 I/O eQEP-5 Strobe
SD3_D4 6 I SDFM-3 Channel 4 Data Input
ESC_GPI10 10 I EtherCAT General-Purpose Input 10
FSIRXB_D0 13 I FSIRX-B Primary Data Input
GPIO111 0, 4, 8, 12 H3 I/O General-Purpose Input Output 111
EMIF1_D30 1 I/O External Memory Interface 1 data line 30
EQEP5_INDEX 5 I/O eQEP-5 Index
SD3_C4 6 I SDFM-3 Channel 4 Clock Input
ESC_GPI11 10 I EtherCAT General-Purpose Input 11
FSIRXB_D1 13 I FSIRX-B Optional Additional Data Input
GPIO112 0, 4, 8, 12 H4 I/O General-Purpose Input Output 112
EMIF1_D29 1 I/O External Memory Interface 1 data line 29
SD1_D3 7 I SDFM-1 Channel 3 Data Input
ESC_GPI12 10 I EtherCAT General-Purpose Input 12
FSIRXB_CLK 13 I FSIRX-B Input Clock
GPIO113 0, 4, 8, 12 J3 I/O General-Purpose Input Output 113
EMIF1_D28 1 I/O External Memory Interface 1 data line 28
SD1_C3 7 I SDFM-1 Channel 3 Clock Input
ESC_GPI13 10 I EtherCAT General-Purpose Input 13
GPIO114 0, 4, 8, 12 J4 I/O General-Purpose Input Output 114
EMIF1_D27 1 I/O External Memory Interface 1 data line 27
SD1_D4 7 I SDFM-1 Channel 4 Data Input
ESC_GPI14 10 I EtherCAT General-Purpose Input 14
GPIO115 0, 4, 8, 12 P9 I/O General-Purpose Input Output 115
EMIF1_D26 1 I/O External Memory Interface 1 data line 26
OUTPUTXBAR5 5 O Output X-BAR Output 5
SD1_C4 7 I SDFM-1 Channel 4 Clock Input
ESC_GPI15 10 I EtherCAT General-Purpose Input 15
FSIRXC_D0 13 I FSIRX-C Primary Data Input
GPIO116 0, 4, 8, 12 H11 I/O General-Purpose Input Output 116
OUTPUTXBAR6 5 O Output X-BAR Output 6
ESC_GPI16 10 I EtherCAT General-Purpose Input 16
FSIRXC_D1 13 I FSIRX-C Optional Additional Data Input
GPIO119 0, 4, 8, 12 M10 I/O General-Purpose Input Output 119
EMIF1_D25 1 I/O External Memory Interface 1 data line 25
MCANB_TX 5 O CAN/CAN FD-B Transmit
ESC_GPI19 10 I EtherCAT General-Purpose Input 19
FSIRXD_D1 13 I FSIRX-D Optional Additional Data Input
GPIO120 0, 4, 8, 12 M11 I/O General-Purpose Input Output 120
EMIF1_D24 1 I/O External Memory Interface 1 data line 24
MCANB_RX 5 I CAN/CAN FD-B Receive
ESC_GPI20 10 I EtherCAT General-Purpose Input 20
FSIRXD_CLK 13 I FSIRX-D Input Clock
GPIO122 0, 4, 8, 12 L7 I/O General-Purpose Input Output 122
EMIF1_D23 1 I/O External Memory Interface 1 data line 23
SPIC_PICO 6 I/O SPI-C Peripheral In, Controller Out (PICO)
SD1_D1 7 I SDFM-1 Channel 1 Data Input
ESC_GPI22 10 I EtherCAT General-Purpose Input 22
GPIO123 0, 4, 8, 12 M7 I/O General-Purpose Input Output 123
EMIF1_D22 1 I/O External Memory Interface 1 data line 22
SPIC_POCI 6 I/O SPI-C Peripheral Out, Controller In (POCI)
SD1_C1 7 I SDFM-1 Channel 1 Clock Input
ESC_GPI23 10 I EtherCAT General-Purpose Input 23
GPIO124 0, 4, 8, 12 L8 I/O General-Purpose Input Output 124
EMIF1_D21 1 I/O External Memory Interface 1 data line 21
SPIC_CLK 6 I/O SPI-C Clock
SD1_D2 7 I SDFM-1 Channel 2 Data Input
ESC_GPI24 10 I EtherCAT General-Purpose Input 24
GPIO125 0, 4, 8, 12 M8 I/O General-Purpose Input Output 125
EMIF1_D20 1 I/O External Memory Interface 1 data line 20
SPIC_PTE 6 I/O SPI-C Peripheral Transmit Enable (PTE)
SD1_C2 7 I SDFM-1 Channel 2 Clock Input
ESC_GPI25 10 I EtherCAT General-Purpose Input 25
ESC_LATCH0 14 I EtherCAT Latch Signal Input 0
GPIO126 0, 4, 8, 12 T9 I/O General-Purpose Input Output 126
EMIF1_D19 1 I/O External Memory Interface 1 data line 19
SPID_PICO 6 I/O SPI-D Peripheral In, Controller Out (PICO)
SD1_D3 7 I SDFM-1 Channel 3 Data Input
ESC_GPI26 10 I EtherCAT General-Purpose Input 26
ESC_LATCH1 14 I EtherCAT Latch Signal Input 1
GPIO127 0, 4, 8, 12 R9 I/O General-Purpose Input Output 127
EMIF1_D18 1 I/O External Memory Interface 1 data line 18
SPID_POCI 6 I/O SPI-D Peripheral Out, Controller In (POCI)
SD1_C3 7 I SDFM-1 Channel 3 Clock Input
ESC_GPI27 10 I EtherCAT General-Purpose Input 27
ESC_SYNC0 14 O EtherCAT SyncSignal Output 0
GPIO128 0, 4, 8, 12 M9 I/O General-Purpose Input Output 128
EMIF1_D17 1 I/O External Memory Interface 1 data line 17
SPID_CLK 6 I/O SPI-D Clock
SD1_D4 7 I SDFM-1 Channel 4 Data Input
ESC_GPI28 10 I EtherCAT General-Purpose Input 28
ESC_SYNC1 14 O EtherCAT SyncSignal Output 1
GPIO129 0, 4, 8, 12 L9 I/O General-Purpose Input Output 129
EMIF1_D16 1 I/O External Memory Interface 1 data line 16
SPID_PTE 6 I/O SPI-D Peripheral Transmit Enable (PTE)
SD1_C4 7 I SDFM-1 Channel 4 Clock Input
ESC_GPI29 10 I EtherCAT General-Purpose Input 29
ESC_TX1_ENA 14 I/O EtherCAT MII Transmit-1 Enable
GPIO130 0, 4, 8, 12 T10 I/O General-Purpose Input Output 130
EPWM13_A 1 O ePWM-13 Output A
SD2_D1 7 I SDFM-2 Channel 1 Data Input
ESC_GPI30 10 I EtherCAT General-Purpose Input 30
ESC_TX1_CLK 14 I EtherCAT MII Transmit-1 Clock
GPIO131 0, 4, 8, 12 N13 I/O General-Purpose Input Output 131
EPWM13_B 1 O ePWM-13 Output B
SD2_C1 7 I SDFM-2 Channel 1 Clock Input
ESC_GPI31 10 I EtherCAT General-Purpose Input 31
ESC_TX1_DATA0 14 O EtherCAT MII Transmit-1 Data-0
GPIO132 0, 4, 8, 12 T14 I/O General-Purpose Input Output 132
EPWM14_A 1 O ePWM-14 Output A
SD2_D2 7 I SDFM-2 Channel 2 Data Input
ESC_GPO0 10 O EtherCAT General-Purpose Output 0
ESC_TX1_DATA1 14 O EtherCAT MII Transmit-1 Data-1
GPIO133 0, 4, 8, 12 J15 118 F13 I/O General-Purpose Input Output 133
EMIF1_A11 1 O External Memory Interface 1 address line 11
EPWM9_A 2 O ePWM-9 Output A
SD2_C2 7 I SDFM-2 Channel 2 Clock Input
ESC_LED_STATE_RUN 11 O EtherCAT LED State Run
GPIO134 0, 4, 8, 12 R14 I/O General-Purpose Input Output 134
EPWM14_B 1 O ePWM-14 Output B
SD2_D3 7 I SDFM-2 Channel 3 Data Input
ESC_GPO1 10 O EtherCAT General-Purpose Output 1
SD2_C1 13 I SDFM-2 Channel 1 Clock Input
ESC_TX1_DATA2 14 O EtherCAT MII Transmit-1 Data-2
GPIO141 0, 4, 8, 12 H13 I/O General-Purpose Input Output 141
EPWM15_A 1 O ePWM-15 Output A
SCIB_TX 6 O SCI-B Transmit Data
ESC_GPO8 10 O EtherCAT General-Purpose Output 8
ESC_RX1_DATA2 14 I EtherCAT MII Receive-1 Data-2
GPIO142 0, 4, 8, 12 H14 I/O General-Purpose Input Output 142
EPWM15_B 1 O ePWM-15 Output B
SCIB_RX 6 I SCI-B Receive Data
ESC_GPO9 10 O EtherCAT General-Purpose Output 9
ESC_RX1_DATA3 14 I EtherCAT MII Receive-1 Data-3
GPIO145 0, 4, 8, 12 H15 I/O General-Purpose Input Output 145
EPWM1_A 1 O ePWM-1 Output A
MCANB_TX 6 O CAN/CAN FD-B Transmit
ESC_GPO12 10 O EtherCAT General-Purpose Output 12
ESC_LED_ERR 14 O EtherCAT Error LED
GPIO146 0, 4, 8, 12 H16 I/O General-Purpose Input Output 146
EPWM1_B 1 O ePWM-1 Output B
MCANB_RX 6 I CAN/CAN FD-B Receive
ESC_GPO13 10 O EtherCAT General-Purpose Output 13
ESC_LED_RUN 14 O EtherCAT Run LED
GPIO147 0, 4, 8, 12 H12 I/O General-Purpose Input Output 147
EPWM2_A 1 O ePWM-2 Output A
EQEP5_A 6 I eQEP-5 Input A
ESC_GPO14 10 O EtherCAT General-Purpose Output 14
ESC_LED_STATE_RUN 14 O EtherCAT LED State Run
GPIO148 0, 4, 8, 12 C12 I/O General-Purpose Input Output 148
EPWM2_B 1 O ePWM-2 Output B
EQEP5_B 6 I eQEP-5 Input B
ESC_GPO15 10 O EtherCAT General-Purpose Output 15
ESC_PHY0_LINKSTATUS 14 I EtherCAT PHY-0 Link Status
GPIO149 0, 4, 8, 12 B12 I/O General-Purpose Input Output 149
EPWM3_A 1 O ePWM-3 Output A
EQEP5_STROBE 6 I/O eQEP-5 Strobe
ESC_GPO16 10 O EtherCAT General-Purpose Output 16
ESC_PHY1_LINKSTATUS 14 I EtherCAT PHY-1 Link Status
GPIO150 0, 4, 8, 12 A12 I/O General-Purpose Input Output 150
EPWM3_B 1 O ePWM-3 Output B
EQEP5_INDEX 6 I/O eQEP-5 Index
ESC_GPO17 10 O EtherCAT General-Purpose Output 17
ESC_I2C_SDA 14 I/OC EtherCAT I2C Data
GPIO151 0, 4, 8, 12 F11 I/O General-Purpose Input Output 151
EPWM4_A 1 O ePWM-4 Output A
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
ESC_GPO18 10 O EtherCAT General-Purpose Output 18
FSITXA_D0 13 O FSITX-A Primary Data Output
ESC_I2C_SCL 14 I/OC EtherCAT I2C Clock
GPIO152 0, 4, 8, 12 E11 I/O General-Purpose Input Output 152
EPWM4_B 1 O ePWM-4 Output B
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
ESC_GPO19 10 O EtherCAT General-Purpose Output 19
FSITXA_D1 13 O FSITX-A Optional Additional Data Output
ESC_MDIO_CLK 14 O EtherCAT MDIO Clock
GPIO153 0, 4, 8, 12 D11 I/O General-Purpose Input Output 153
EPWM5_A 1 O ePWM-5 Output A
PMBUSA_ALERT 6 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
ESC_GPO20 10 O EtherCAT General-Purpose Output 20
FSITXA_CLK 13 O FSITX-A Output Clock
ESC_MDIO_DATA 14 I/O EtherCAT MDIO Data
GPIO154 0, 4, 8, 12 C11 I/O General-Purpose Input Output 154
EPWM5_B 1 O ePWM-5 Output B
PMBUSA_CTL 6 I/O PMBus-A Control Signal - Target Input/Controller Output
ESC_GPO21 10 O EtherCAT General-Purpose Output 21
FSIRXA_D0 13 I FSIRX-A Primary Data Input
ESC_PHY_CLK 14 O EtherCAT PHY Clock
GPIO155 0, 4, 8, 12 B11 I/O General-Purpose Input Output 155
EPWM6_A 1 O ePWM-6 Output A
ESC_GPO22 10 O EtherCAT General-Purpose Output 22
FSIRXA_D1 13 I FSIRX-A Optional Additional Data Input
ESC_PHY_RESETn 14 O EtherCAT PHY Active Low Reset
GPIO156 0, 4, 8, 12 A11 I/O General-Purpose Input Output 156
EPWM6_B 1 O ePWM-6 Output B
ESC_GPO23 10 O EtherCAT General-Purpose Output 23
FSIRXA_CLK 13 I FSIRX-A Input Clock
ESC_TX0_ENA 14 I/O EtherCAT MII Transmit-0 Enable
GPIO157 0, 4, 8, 12 E10 I/O General-Purpose Input Output 157
EPWM7_A 1 O ePWM-7 Output A
ESC_GPO24 10 O EtherCAT General-Purpose Output 24
FSITXB_D0 13 O FSITX-B Primary Data Output
ESC_TX0_CLK 14 I EtherCAT MII Transmit-0 Clock
GPIO158 0, 4, 8, 12 D10 I/O General-Purpose Input Output 158
EPWM7_B 1 O ePWM-7 Output B
ESC_GPO25 10 O EtherCAT General-Purpose Output 25
FSITXB_D1 13 O FSITX-B Optional Additional Data Output
ESC_TX0_DATA0 14 O EtherCAT MII Transmit-0 Data-0
GPIO159 0, 4, 8, 12 C10 I/O General-Purpose Input Output 159
EPWM8_A 1 O ePWM-8 Output A
ESC_GPO26 10 O EtherCAT General-Purpose Output 26
FSITXB_CLK 13 O FSITX-B Output Clock
ESC_TX0_DATA1 14 O EtherCAT MII Transmit-0 Data-1
GPIO160 0, 4, 8, 12 B10 I/O General-Purpose Input Output 160
EPWM8_B 1 O ePWM-8 Output B
ESC_GPO27 10 O EtherCAT General-Purpose Output 27
FSIRXB_D0 13 I FSIRX-B Primary Data Input
ESC_TX0_DATA2 14 O EtherCAT MII Transmit-0 Data-2
GPIO161 0, 4, 8, 12 E9 I/O General-Purpose Input Output 161
EPWM9_A 1 O ePWM-9 Output A
ESC_GPO28 10 O EtherCAT General-Purpose Output 28
FSIRXB_D1 13 I FSIRX-B Optional Additional Data Input
ESC_TX0_DATA3 14 O EtherCAT MII Transmit-0 Data-3
GPIO162 0, 4, 8, 12 A8 I/O General-Purpose Input Output 162
EPWM9_B 1 O ePWM-9 Output B
ESC_GPO29 10 O EtherCAT General-Purpose Output 29
FSIRXB_CLK 13 I FSIRX-B Input Clock
ESC_RX0_DV 14 I EtherCAT MII Receive-0 Data Valid
GPIO163 0, 4, 8, 12 B8 I/O General-Purpose Input Output 163
EPWM10_A 1 O ePWM-10 Output A
ESC_GPO30 10 O EtherCAT General-Purpose Output 30
FSIRXC_D0 13 I FSIRX-C Primary Data Input
ESC_RX0_CLK 14 I EtherCAT MII Receive-0 Clock
GPIO164 0, 4, 8, 12 C8 I/O General-Purpose Input Output 164
EPWM10_B 1 O ePWM-10 Output B
ESC_GPO31 10 O EtherCAT General-Purpose Output 31
FSIRXC_D1 13 I FSIRX-C Optional Additional Data Input
ESC_RX0_ERR 14 I EtherCAT MII Receive-0 Error
GPIO165 0, 4, 8, 12 F6 I/O General-Purpose Input Output 165
EPWM11_A 1 O ePWM-11 Output A
FSIRXC_CLK 13 I FSIRX-C Input Clock
ESC_RX0_DATA0 14 I EtherCAT MII Receive-0 Data-0
GPIO166 0, 4, 8, 12 B5 I/O General-Purpose Input Output 166
EPWM11_B 1 O ePWM-11 Output B
FSIRXD_D0 13 I FSIRX-D Primary Data Input
ESC_RX0_DATA1 14 I EtherCAT MII Receive-0 Data-1
GPIO167 0, 4, 8, 12 E5 I/O General-Purpose Input Output 167
EPWM12_A 1 O ePWM-12 Output A
FSIRXD_D1 13 I FSIRX-D Optional Additional Data Input
ESC_RX0_DATA2 14 I EtherCAT MII Receive-0 Data-2
GPIO168 0, 4, 8, 12 F5 I/O General-Purpose Input Output 168
EPWM12_B 1 O ePWM-12 Output B
FSIRXD_CLK 13 I FSIRX-D Input Clock
ESC_RX0_DATA3 14 I EtherCAT MII Receive-0 Data-3
GPIO198 0, 4, 8, 12 K4 26 G4 I/O General-Purpose Input Output 198 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP1_A 1 I eQEP-1 Input A
EPWM9_B 2 O ePWM-9 Output B
SPIA_PICO 3 I/O SPI-A Peripheral In, Controller Out (PICO)
ESC_PDI_UC_IRQ 14 O EtherCAT PDI IRQ Interrupt Line
GPIO199 0, 4, 8, 12 H1 22 F1 9 I/O General-Purpose Input Output 199 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP1_STROBE 1 I/O eQEP-1 Strobe
EPWM17_A 2 O ePWM-17 Output A
SCIB_TX 3 O SCI-B Transmit Data
EPWM12_A 5 O ePWM-12 Output A
SPIB_CLK 6 I/O SPI-B Clock
SD1_D4 7 I SDFM-1 Channel 4 Data Input
MCANA_TX 9 O CAN/CAN FD-A Transmit
EMIF1_RAS 10 O External Memory Interface 1 row address strobe
SPIC_CLK 14 I/O SPI-C Clock
GPIO200 0, 4, 8, 12 J1 23 G1 10 I/O General-Purpose Input Output 200 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP1_INDEX 1 I/O eQEP-1 Index
EPWM17_B 2 O ePWM-17 Output B
SCIB_RX 3 I SCI-B Receive Data
EPWM12_B 5 O ePWM-12 Output B
SPIB_PTE 6 I/O SPI-B Peripheral Transmit Enable (PTE)
SD1_C4 7 I SDFM-1 Channel 4 Clock Input
MCANA_RX 9 I CAN/CAN FD-A Receive
EMIF1_CAS 10 O External Memory Interface 1 column address strobe
ESC_TX1_DATA1 11 O EtherCAT MII Transmit-1 Data-1
SPIC_PTE 14 I/O SPI-C Peripheral Transmit Enable (PTE)
GPIO201 0, 4, 8, 12 J2 24 G2 I/O General-Purpose Input Output 201 This pin also has analog functions which are described in the ANALOG section of this table.
OUTPUTXBAR1 1 O Output X-BAR Output 1
EQEP2_A 2 I eQEP-2 Input A
EPWM18_A 3 O ePWM-18 Output A
LINB_TX 5 O LIN-B Transmit
SPIB_PICO 6 I/O SPI-B Peripheral In, Controller Out (PICO)
SD2_D1 7 I SDFM-2 Channel 1 Data Input
PMBUSA_SCL 9 I/OD PMBus-A Open-Drain Bidirectional Clock
EMIF1_DQM0 10 O External Memory Interface 1 Input/output mask for byte 0
ESC_TX1_DATA2 11 O EtherCAT MII Transmit-1 Data-2
EPWM13_A 13 O ePWM-13 Output A
GPIO202 0, 4, 8, 12 K3 25 G3 I/O General-Purpose Input Output 202 This pin also has analog functions which are described in the ANALOG section of this table.
OUTPUTXBAR2 1 O Output X-BAR Output 2
EQEP2_B 2 I eQEP-2 Input B
EPWM18_B 3 O ePWM-18 Output B
LINB_RX 5 I LIN-B Receive
SPIB_POCI 6 I/O SPI-B Peripheral Out, Controller In (POCI)
SD2_C1 7 I SDFM-2 Channel 1 Clock Input
PMBUSA_SDA 9 I/OD PMBus-A Open-Drain Bidirectional Data
EMIF1_DQM1 10 O External Memory Interface 1 Input/output mask for byte 1
ESC_TX1_DATA3 11 O EtherCAT MII Transmit-1 Data-3
EPWM13_B 13 O ePWM-13 Output B
FSITXA_D1 14 O FSITX-A Optional Additional Data Output
GPIO203 0, 4, 8, 12 K5 27 G5 11 I/O General-Purpose Input Output 203 This pin also has analog functions which are described in the ANALOG section of this table.
OUTPUTXBAR3 1, 5 O Output X-BAR Output 3
EQEP2_INDEX 2 I/O eQEP-2 Index
SPIA_POCI 3 I/O SPI-A Peripheral Out, Controller In (POCI)
SPIB_CLK 6 I/O SPI-B Clock
SD3_D1 7 I SDFM-3 Channel 1 Data Input
PMBUSA_ALERT 9 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
EMIF1_DQM2 10 O External Memory Interface 1 Input/output mask for byte 2
ESC_MDIO_CLK 11 O EtherCAT MDIO Clock
EPWM14_A 13 O ePWM-14 Output A
FSITXA_D0 14 O FSITX-A Primary Data Output
EPWM8_B 15 O ePWM-8 Output B
GPIO204 0, 4, 8, 12 L6 28 G6 12 I/O General-Purpose Input Output 204 This pin also has analog functions which are described in the ANALOG section of this table.
OUTPUTXBAR4 1, 5 O Output X-BAR Output 4
EQEP2_STROBE 2 I/O eQEP-2 Strobe
SPIA_CLK 3 I/O SPI-A Clock
SPIB_PTE 6 I/O SPI-B Peripheral Transmit Enable (PTE)
SD2_C2 7 I SDFM-2 Channel 2 Clock Input
PMBUSA_CTL 9 I/O PMBus-A Control Signal - Target Input/Controller Output
EMIF1_DQM3 10 O External Memory Interface 1 Input/output mask for byte 3
ESC_MDIO_DATA 11 I/O EtherCAT MDIO Data
EPWM14_B 13 O ePWM-14 Output B
FSITXA_CLK 14 O FSITX-A Output Clock
SD1_D3 15 I SDFM-1 Channel 3 Data Input
GPIO205 0, 4, 8, 12 M6 29 H6 13 I/O General-Purpose Input Output 205 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP1_INDEX 1 I/O eQEP-1 Index
EPWM10_A 2 O ePWM-10 Output A
SPIA_PTE 3 I/O SPI-A Peripheral Transmit Enable (PTE)
OUTPUTXBAR1 11 O Output X-BAR Output 1
SD1_C3 15 I SDFM-1 Channel 3 Clock Input
GPIO206 0, 4, 8, 12 L5 30 H5 14 I/O General-Purpose Input Output 206 This pin also has analog functions which are described in the ANALOG section of this table.
EMIF1_A11 1 O External Memory Interface 1 address line 11
EPWM10_B 2 O ePWM-10 Output B
EMIF1_WEn 3 O External Memory Interface 1 write enable
OUTPUTXBAR2 11 O Output X-BAR Output 2
ESC_PHY_CLK 14 O EtherCAT PHY Clock
ESC_LED_STATE_RUN 15 O EtherCAT LED State Run
GPIO207 0, 4, 8, 12 N5 55 J4 36 I/O General-Purpose Input Output 207 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP2_A 1 I eQEP-2 Input A
EPWM11_A 2 O ePWM-11 Output A
EXTSYNCOUT 3 O External ePWM Synchronization Pulse
CANA_TX 5 O CAN-A Transmit
SD4_D1 6 I SDFM-4 Channel 1 Data Input
SCIA_RX 7 I SCI-A Receive Data
LINA_RX 9 I LIN-A Receive
I2CB_SCL 10 I/OD I2C-B Open-Drain Bidirectional Clock
OUTPUTXBAR3 11 O Output X-BAR Output 3
ESC_RX1_CLK 14 I EtherCAT MII Receive-1 Clock
PMBUSA_ALERT 15 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
GPIO208 0, 4, 8, 12 P5 56 K4 37 I/O General-Purpose Input Output 208 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP2_B 1 I eQEP-2 Input B
EPWM11_B 2 O ePWM-11 Output B
EMIF1_D13 3 I/O External Memory Interface 1 data line 13
SPIB_PICO 5 I/O SPI-B Peripheral In, Controller Out (PICO)
SD4_C1 6 I SDFM-4 Channel 1 Clock Input
SCIA_TX 7 O SCI-A Transmit Data
OUTPUTXBAR4 11 O Output X-BAR Output 4
ESC_RX1_DV 14 I EtherCAT MII Receive-1 Data Valid
PMBUSA_CTL 15 I/O PMBus-A Control Signal - Target Input/Controller Output
GPIO209 0, 4, 8, 12 N6 57 J5 38 I/O General-Purpose Input Output 209 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP2_STROBE 1 I/O eQEP-2 Strobe
EPWM12_A 2 O ePWM-12 Output A
EMIF1_D14 3 I/O External Memory Interface 1 data line 14
SPIB_POCI 5 I/O SPI-B Peripheral Out, Controller In (POCI)
SD4_D2 6 I SDFM-4 Channel 2 Data Input
EPWM12_B 7 O ePWM-12 Output B
LINB_RX 10 I LIN-B Receive
OUTPUTXBAR5 11 O Output X-BAR Output 5
ESC_RX1_ERR 14 I EtherCAT MII Receive-1 Error
PMBUSA_SDA 15 I/OD PMBus-A Open-Drain Bidirectional Data
GPIO210 0, 4, 8, 12 P6 58 K5 I/O General-Purpose Input Output 210 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP2_INDEX 1 I/O eQEP-2 Index
EPWM12_B 2 O ePWM-12 Output B
EMIF1_D15 3 I/O External Memory Interface 1 data line 15
SD4_C2 6 I SDFM-4 Channel 2 Clock Input
LINB_TX 10 O LIN-B Transmit
OUTPUTXBAR6 11 O Output X-BAR Output 6
ESC_RX0_DATA2 14 I EtherCAT MII Receive-0 Data-2
PMBUSA_SCL 15 I/OD PMBus-A Open-Drain Bidirectional Clock
GPIO211 0, 4, 8, 12 R6 59 J6 I/O General-Purpose Input Output 211 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP6_A 1 I eQEP-6 Input A
EPWM14_A 2 O ePWM-14 Output A
SD4_D3 6 I SDFM-4 Channel 3 Data Input
OUTPUTXBAR7 11 O Output X-BAR Output 7
ESC_LED_LINK0_ACTIVE 14 O EtherCAT Link-0 Active
GPIO212 0, 4, 8, 12 T7 60 K6 I/O General-Purpose Input Output 212 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP6_B 1 I eQEP-6 Input B
EPWM14_B 2 O ePWM-14 Output B
SD4_C3 6 I SDFM-4 Channel 3 Clock Input
ESC_LED_LINK1_ACTIVE 14 O EtherCAT Link-1 Active
GPIO213 0, 4, 8, 12 T8 62 L5 39 I/O General-Purpose Input Output 213 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP6_STROBE 1 I/O eQEP-6 Strobe
EPWM8_A 2 O ePWM-8 Output A
SD4_D4 6 I SDFM-4 Channel 4 Data Input
LINB_TX 10 O LIN-B Transmit
ESC_LED_ERR 14 O EtherCAT Error LED
GPIO214 0, 4, 8, 12 R8 63 L6 40 I/O General-Purpose Input Output 214 This pin also has analog functions which are described in the ANALOG section of this table.
CANA_RX 1 I CAN-A Receive
EMIF1_CLK 2 O External Memory Interface 1 clock
MCANA_RX 3 I CAN/CAN FD-A Receive
OUTPUTXBAR7 5 O Output X-BAR Output 7
EQEP3_STROBE 6 I/O eQEP-3 Strobe
SD2_D4 7 I SDFM-2 Channel 4 Data Input
EMIF1_CS4n 9 O External Memory Interface 1 chip select 4
ESC_LATCH1 10 I EtherCAT Latch Signal Input 1
ESC_I2C_SCL 11 I/OC EtherCAT I2C Clock
EPWM16_A 13 O ePWM-16 Output A
ESC_SYNC1 14 O EtherCAT SyncSignal Output 1
SPID_PICO 15 I/O SPI-D Peripheral In, Controller Out (PICO)
GPIO215 0, 4, 8, 12 P7 64 M6 I/O General-Purpose Input Output 215 This pin also has analog functions which are described in the ANALOG section of this table.
SCIA_RX 1 I SCI-A Receive Data
EMIF1_CS4n 2 O External Memory Interface 1 chip select 4
CANA_RX 3 I CAN-A Receive
OUTPUTXBAR5 5 O Output X-BAR Output 5
EQEP3_A 6 I eQEP-3 Input A
SD2_D3 7 I SDFM-2 Channel 3 Data Input
EMIF1_CS2n 9 O External Memory Interface 1 chip select 2
I2CB_SDA 10 I/OD I2C-B Open-Drain Bidirectional Data
SPIC_POCI 11 I/O SPI-C Peripheral Out, Controller In (POCI)
EPWM15_A 13 O ePWM-15 Output A
LINA_TX 14 O LIN-A Transmit
EMIF1_D12 15 I/O External Memory Interface 1 data line 12
GPIO216 0, 4, 8, 12 N7 65 N6 I/O General-Purpose Input Output 216 This pin also has analog functions which are described in the ANALOG section of this table.
SCIA_TX 1 O SCI-A Transmit Data
EMIF1_SDCKE 2 O External Memory Interface 1 SDRAM clock enable
SPID_CLK 3 I/O SPI-D Clock
OUTPUTXBAR6 5 O Output X-BAR Output 6
EQEP3_B 6 I eQEP-3 Input B
SD2_C3 7 I SDFM-2 Channel 3 Clock Input
EMIF1_CS3n 9 O External Memory Interface 1 chip select 3
ESC_LATCH0 10 I EtherCAT Latch Signal Input 0
ESC_I2C_SDA 11 I/OC EtherCAT I2C Data
EPWM15_B 13 O ePWM-15 Output B
ESC_SYNC0 14 O EtherCAT SyncSignal Output 0
EMIF1_D13 15 I/O External Memory Interface 1 data line 13
GPIO217 0, 4, 8, 12 P8 66 M7 I/O General-Purpose Input Output 217 This pin also has analog functions which are described in the ANALOG section of this table.
CANA_TX 1 O CAN-A Transmit
EMIF1_WEn 2 O External Memory Interface 1 write enable
MCANA_TX 3 O CAN/CAN FD-A Transmit
OUTPUTXBAR8 5 O Output X-BAR Output 8
EQEP3_INDEX 6 I/O eQEP-3 Index
SD2_C4 7 I SDFM-2 Channel 4 Clock Input
EMIF1_RNW 9 O External Memory Interface 1 read not write
I2CA_SDA 10 I/OD I2C-A Open-Drain Bidirectional Data
SPID_PTE 11 I/O SPI-D Peripheral Transmit Enable (PTE)
EPWM16_B 13 O ePWM-16 Output B
LINB_TX 14 O LIN-B Transmit
SPID_POCI 15 I/O SPI-D Peripheral Out, Controller In (POCI)
GPIO218 0, 4, 8, 12 N8 67 N7 I/O General-Purpose Input Output 218 This pin also has analog functions which are described in the ANALOG section of this table.
I2CA_SDA 1 I/OD I2C-A Open-Drain Bidirectional Data
EMIF1_CS0n 2 O External Memory Interface 1 chip select 0
SPIA_PICO 3 I/O SPI-A Peripheral In, Controller Out (PICO)
EQEP4_A 5 I eQEP-4 Input A
LINB_TX 6 O LIN-B Transmit
CLB_OUTPUTXBAR1 7 O CLB Output X-BAR Output 1
EMIF1_OEn 9 O External Memory Interface 1 output enable
I2CA_SCL 10 I/OD I2C-A Open-Drain Bidirectional Clock
SPID_CLK 15 I/O SPI-D Clock
GPIO219 0, 4, 8, 12 R7 61 I/O General-Purpose Input Output 219 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP6_INDEX 1 I/O eQEP-6 Index
EPWM8_B 2 O ePWM-8 Output B
SD4_C4 6 I SDFM-4 Channel 4 Clock Input
ESC_LED_RUN 14 O EtherCAT Run LED
GPIO220 0, 4, 8, 12 F16 123 D13 68 I/O General-Purpose Input Output 220
EPWM6_A 2 O ePWM-6 Output A
SPID_POCI 3 I/O SPI-D Peripheral Out, Controller In (POCI)
OUTPUTXBAR2 5 O Output X-BAR Output 2
SCIB_TX 6 O SCI-B Transmit Data
MCANA_TX 7 O CAN/CAN FD-A Transmit
PMBUSA_ALERT 15 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
X1 ALT I/O Crystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock.
GPIO221 0, 4, 8, 12 G16 121 E13 66 I/O General-Purpose Input Output 221
EPWM6_B 2 O ePWM-6 Output B
SPID_PTE 3 I/O SPI-D Peripheral Transmit Enable (PTE)
OUTPUTXBAR3 5 O Output X-BAR Output 3
SCIB_RX 6 I SCI-B Receive Data
MCANA_RX 7 I CAN/CAN FD-A Receive
PMBUSA_CTL 15 I/O PMBus-A Control Signal - Target Input/Controller Output
X2 ALT I/O Crystal oscillator output.
GPIO222 0, 4, 8, 12 T12 77 N9 46 I/O General-Purpose Input Output 222
TDI 1 I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.
EPWM7_A 2 O ePWM-7 Output A
SPIA_PICO 3 I/O SPI-A Peripheral In, Controller Out (PICO)
OUTPUTXBAR4 5 O Output X-BAR Output 4
SCIA_RX 6 I SCI-A Receive Data
UARTB_TX 7 I/O UART-B Serial Data Transmit
I2CA_SDA 9 I/OD I2C-A Open-Drain Bidirectional Data
SPIC_CLK 10 I/O SPI-C Clock
ESC_PDI_UC_IRQ 14 O EtherCAT PDI IRQ Interrupt Line
PMBUSA_SDA 15 I/OD PMBus-A Open-Drain Bidirectional Data
GPIO223 0, 4, 8, 12 R12 78 M9 47 I/O General-Purpose Input Output 223
TDO 1 O JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK.
EPWM7_B 2 O ePWM-7 Output B
EMIF1_A11 3 O External Memory Interface 1 address line 11
OUTPUTXBAR5 5 O Output X-BAR Output 5
SCIA_TX 6 O SCI-A Transmit Data
UARTB_RX 7 I/O UART-B Serial Data Receive
I2CA_SCL 9 I/OD I2C-A Open-Drain Bidirectional Clock
SPIC_PTE 10 I/O SPI-C Peripheral Transmit Enable (PTE)
PMBUSA_SCL 15 I/OD PMBus-A Open-Drain Bidirectional Clock
GPIO224 0, 4, 8, 12 P16 92 L12 I/O General-Purpose Input Output 224
ERRORSTS 1 O Error Status Output. This signal requires an external pulldown.
EMIF1_SDCKE 2 O External Memory Interface 1 SDRAM clock enable
XCLKOUT 3 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
OUTPUTXBAR1 5 O Output X-BAR Output 1
SD2_C1 13 I SDFM-2 Channel 1 Clock Input
ESC_PDI_UC_IRQ 14 O EtherCAT PDI IRQ Interrupt Line
TEST, JTAG, AND RESET
TCK R13 81 M10 50 I JTAG test clock with internal pullup.
TMS T13 80 N10 49 I/O JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. This device does not have a TRSTn pin. An external pullup resistor (recommended 2.2 kΩ) on the TMS pin to VDDIO should be placed on the board to keep JTAG in reset during normal operation.
VREGENZ J16 119 E10 64 I Internal voltage regulator enable with internal pullup. Tie low to VSS to enable internal VREG. Tie high to VDDIO to use an external supply.
XRSn G14 124 D12 69 I/OD Device Reset (in) and Watchdog Reset (out). During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRSn pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor between 2.2 kΩ and 10 kΩ should be placed between XRSn and VDDIO. If a capacitor is placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. This pin is an open-drain output with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device.
POWER AND GROUND
VDD3VFL R11, T11 72 M8 44 3.3-V Flash power pin. Place a minimum 0.1-µF decoupling capacitor on each pin. Connect this pin to 3.3-V supply.
VDD F9, F10, G6, J11, K8, K9 16, 76, 117, 137, 169 F5, F7, G9, J9 8, 45, 63, 78, 95 1.2-V Digital Logic Power Pins. TI recommends placing a decoupling capacitor near each VDD pin with a minimum total capacitance of approximately 20 µF. The exact value of the decoupling capacitance should be determined by your system voltage regulation solution.
VDDA N1, T6 36, 54 L2, M5 18, 35 3.3-V Analog Power Pins. Place a minimum 2.2-µF decoupling capacitor to VSSA on each pin. Connect this pin to 3.3-V supply.
VDDIO B1, E15, G7, G8, H5, J5, J10, K7, K10, T15 3, 15, 68, 75, 88, 91, 99, 114, 127, 138, 152, 168 C13, F4, F6, F8, H9, J8 7, 41, 55, 62, 70, 79, 94 3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF decoupling capacitor on each pin. Connect this pin to 3.3-V supply.
VDDOSC G15 120 E11 65 Power pins for the 3.3-V on-chip crystal oscillator (X1 and X2) and the two zero-pin internal oscillators (INTOSC). Place a 0.1-μF (minimum) decoupling capacitor on each pin. Connect this pin to 3.3-V supply.
VSS A1, A16, G5, G9, G10, G11, H6, H7, H8, H9, H10, J6, J7, J8, J9, K6, T16 PAD A1, A13, F9, G7, G8, H7, H8, J7, N13 PAD Digital Ground
VSSA M3, N2, T1, T5 34, 52 L1, N1, N5 17, 33 Analog Ground
VSSOSC F15 122 E12 67 Crystal oscillator (X1 and X2) ground pin. When using an external crystal, do not connect this pin to the board ground. Instead, connect it to the ground reference of the external crystal oscillator circuit. If an external crystal is not used, this pin may be connected to the board ground.