SPRSP69B July 2023 – November 2023 TMS320F28P650DK , TMS320F28P659DK-Q1
PRODMIX
Refer to the PDF data sheet for device specific package drawings
IDLE and HALT modes on this device are similar to those on other C28x devices. Table 6-11 describes the effect on the system when any of the clock-gating low-power modes are entered.
MODULES/ CLOCK DOMAIN | IDLE | STANDBY | HALT |
---|---|---|---|
SYSCLK | Active | Gated | Gated |
CPUCLK | Gated | Gated | Gated |
Clock to modules connected to PERx.SYSCLK | Active | Gated | Gated |
WDCLK | Active | Active | Gated if CLKSRCCTL1.WDHALTI = 0 |
PLL | Powered | Powered | Software must power down PLL before entering HALT. |
INTOSC1 | Powered | Powered | Powered down if CLKSRCCTL1.WDHALTI = 0 |
INTOSC2 | Powered | Powered | Powered down if CLKSRCCTL1.WDHALTI = 0 |
Flash(1) | Powered | Powered | Powered |
XTAL(2) | Powered | Powered | Powered |