SPRSP69B July 2023 – November 2023 TMS320F28P650DK , TMS320F28P659DK-Q1
PRODMIX
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
General | |||||
ADCCLK Conversion Cycles | 200-MHz SYSCLK | 10.1 | 11 | ADCCLKs | |
Power Up Time | External Reference mode | 500 | µs | ||
Internal Reference mode | 5000 | µs | |||
Internal Reference mode, when switching between 2.5-V range and 3.3-V range. | 5000 | µs | |||
VREFHI input current(1) | 130 | µA | |||
Internal Reference Capacitor Value(2) | 2.2 | µF | |||
External Reference Capacitor Value(2) | 2.2 | µF | |||
DC Characteristics | |||||
Gain Error | Internal reference | –45 | 45 | LSB | |
External reference | –5 | ±3 | 5 | ||
Offset Error(6) | –5 | ±2 | 5 | LSB | |
Channel-to-Channel Gain Error(4) | ±2 | LSB | |||
Channel-to-Channel Offset Error(4) | ±2 | LSB | |||
ADC-to-ADC Gain Error(5) | Identical VREFHI and VREFLO for all ADCs | ±4 | LSB | ||
ADC-to-ADC Offset Error(5) | Identical VREFHI and VREFLO for all ADCs | ±1 | LSB | ||
DNL Error | >–1 | ±0.5 | 1 | LSB | |
INL Error | –2 | ±0.5 | 2 | LSB | |
ADC-to-ADC Isolation | VREFHI = 2.5 V, synchronous ADCs | –1 | 1 | LSBs | |
ADC-to-ADC Isolation | VREFHI = 2.5 V, asynchronous ADCs | Not supported | LSBs | ||
AC Characteristics | |||||
SNR(3) | VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1 via PLL | 72.1 | dB | ||
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from INTOSC via PLL | 65.2 | ||||
THD(3) | VREFHI = 2.5 V, fin = 100 kHz | -86.9 | dB | ||
SFDR(3) | VREFHI = 2.5 V, fin = 100 kHz | 90 | dB | ||
SINAD(3) | VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1 via PLL | 72 | dB | ||
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from INTOSC via PLL | 65.1 | ||||
ENOB(3) | VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1, Single ADC | 11.7 | bits | ||
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1, synchronous ADCs | 11.7 | ||||
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1, asynchronous ADCs | Not Supported | ||||
PSRR | VDD = 1.2-V DC + 100mV DC up to Sine at 1 kHz |
60 | dB | ||
VDD = 1.2-V DC + 100 mV DC up to Sine at 300 kHz |
57 | ||||
VDDA = 3.3-V DC + 200 mV DC up to Sine at 1 kHz |
60 | ||||
VDDA = 3.3-V DC + 200 mV Sine at 900 kHz |
57 |