HCLK |
OSCIN |
GHVSRC |
- Is disabled through the CDDISx registers bit 1
|
GCLK |
OSCIN |
GHVSRC |
- Always the same frequency as HCLK
- In phase with HCLK
- Is disabled separately from HCLK through the CDDISx registers bit 0
- Can be divided by 1 up to 8 when running CPU self-test (LBIST) using the CLKDIV field of the STCCLKDIV register at address 0xFFFFE108
|
GCLK2 |
OSCIN |
GHVSRC |
- Always the same frequency as GCLK
- 2 cycles delayed from GCLK
- Is disabled along with GCLK
- Gets divided by the same divider setting as that for GCLK when running CPU self-test (LBIST)
|
VCLK |
OSCIN |
GHVSRC |
- Divided down from HCLK
- Can be HCLK/1, HCLK/2, ... or HCLK/16
- Is disabled separately from HCLK through the CDDISx registers bit 2
- Can be disabled separately for eQEP using CDDISx registers bit 9
|
VCLK2 |
OSCIN |
GHVSRC |
- Divided down from HCLK
- Can be HCLK/1, HCLK/2, ... or HCLK/16
- Frequency must be an integer multiple of VCLK frequency
- Is disabled separately from HCLK through the CDDISx registers bit 3
|
VCLKA1 |
VCLK |
VCLKASRC |
- Defaults to VCLK as the source
- Frequency can be as fast as HCLK frequency
- Is disabled through the CDDISx registers bit 4
|
RTICLK |
VCLK |
RCLKSRC |
- Defaults to VCLK as the source
- If a clock source other than VCLK is selected for RTICLK, then the RTICLK frequency must be less than or equal to VCLK/3
- Application can ensure this by programming the RTI1DIV field of the RCLKSRC register, if necessary
- Is disabled through the CDDISx registers bit 6
|