SPNS186C October 2012 – May 2018 TMS570LS0332 , TMS570LS0432
PRODUCTION DATA.
The Error Signaling Module (ESM) integrates all the device error conditions and groups them in the order of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest severity. The device response to each error is determined by the severity group it is connected to. Table 6-26 shows the channel assignment for each group.
ERROR GROUP | INTERRUPT CHARACTERISTICS | INFLUENCE ON ERROR PIN |
---|---|---|
Group1 | Maskable, low or high priority | Configurable |
Group2 | Nonmaskable, high priority | Fixed |
Group3 | No interrupt generated | Fixed |
ERROR SOURCES | GROUP | CHANNELS |
---|---|---|
Reserved | Group1 | 0 |
Reserved | Group1 | 1 |
Reserved | Group1 | 2 |
Reserved | Group1 | 3 |
Reserved | Group1 | 4 |
Reserved | Group1 | 5 |
FMC - correctable error: bus1 and bus2 interfaces (does not include accesses to EEPROM bank) | Group1 | 6 |
N2HET - parity | Group1 | 7 |
HTU - parity | Group1 | 8 |
HTU - MPU | Group1 | 9 |
PLL - Slip | Group1 | 10 |
Clock Monitor - interrupt | Group1 | 11 |
Reserved | Group1 | 12 |
Reserved | Group1 | 13 |
Reserved | Group1 | 14 |
VIM RAM - parity | Group1 | 15 |
Reserved | Group1 | 16 |
MibSPI1 - parity | Group1 | 17 |
Reserved | Group1 | 18 |
MibADC - parity | Group1 | 19 |
Reserved | Group1 | 20 |
DCAN1 - parity | Group1 | 21 |
Reserved | Group1 | 22 |
DCAN2 - parity | Group1 | 23 |
Reserved | Group1 | 24 |
Reserved | Group1 | 25 |
RAM even bank (B0TCM) - correctable error | Group1 | 26 |
CPU - self-test | Group1 | 27 |
RAM odd bank (B1TCM) - correctable error | Group1 | 28 |
Reserved | Group1 | 29 |
DCC - error | Group1 | 30 |
CCM-R4 - self-test | Group1 | 31 |
Reserved | Group1 | 32 |
Reserved | Group1 | 33 |
Reserved | Group1 | 34 |
FMC - correctable error (EEPROM bank access) | Group1 | 35 |
FMC - uncorrectable error (EEPROM bank access) | Group1 | 36 |
IOMM - Mux configuration error | Group1 | 37 |
Reserved | Group1 | 38 |
Reserved | Group1 | 39 |
eFuse farm – this error signal is generated whenever any bit in the eFuse farm error status register is set. The application can choose to generate and interrupt whenever this bit is set in order to service any eFuse farm error condition. | Group1 | 40 |
eFuse farm - self test error. It is not necessary to generate a separate interrupt when this bit gets set. | Group1 | 41 |
Reserved | Group1 | 42 |
Reserved | Group1 | 43 |
Reserved | Group1 | 44 |
Reserved | Group1 | 45 |
Reserved | Group1 | 46 |
Reserved | Group1 | 47 |
Reserved | Group1 | 48 |
Reserved | Group1 | 49 |
Reserved | Group1 | 50 |
Reserved | Group1 | 51 |
Reserved | Group1 | 52 |
Reserved | Group1 | 53 |
Reserved | Group1 | 54 |
Reserved | Group1 | 55 |
Reserved | Group1 | 56 |
Reserved | Group1 | 57 |
Reserved | Group1 | 58 |
Reserved | Group1 | 59 |
Reserved | Group1 | 60 |
Reserved | Group1 | 61 |
Reserved | Group1 | 62 |
Reserved | Group1 | 63 |
Reserved | Group2 | 0 |
Reserved | Group2 | 1 |
CCMR4 - compare | Group2 | 2 |
Reserved | Group2 | 3 |
FMC - uncorrectable error (address parity on bus1 accesses) | Group2 | 4 |
Reserved | Group2 | 5 |
RAM even bank (B0TCM) - uncorrectable error | Group2 | 6 |
Reserved | Group2 | 7 |
RAM odd bank (B1TCM) - uncorrectable error | Group2 | 8 |
Reserved | Group2 | 9 |
RAM even bank (B0TCM) - address bus parity error | Group2 | 10 |
Reserved | Group2 | 11 |
RAM odd bank (B1TCM) - address bus parity error | Group2 | 12 |
Reserved | Group2 | 13 |
Reserved | Group2 | 14 |
Reserved | Group2 | 15 |
TCM - ECC live lock detect | Group2 | 16 |
Reserved | Group2 | 17 |
Reserved | Group2 | 18 |
Reserved | Group2 | 19 |
Reserved | Group2 | 20 |
Reserved | Group2 | 21 |
Reserved | Group2 | 22 |
Reserved | Group2 | 23 |
RTI_WWD_NMI | Group2 | 24 |
Reserved | Group2 | 25 |
Reserved | Group2 | 26 |
Reserved | Group2 | 27 |
Reserved | Group2 | 28 |
Reserved | Group2 | 29 |
Reserved | Group2 | 30 |
Reserved | Group2 | 31 |
Reserved | Group3 | 0 |
eFuse Farm - autoload error | Group3 | 1 |
Reserved | Group3 | 2 |
RAM even bank (B0TCM) - ECC uncorrectable error | Group3 | 3 |
Reserved | Group3 | 4 |
RAM odd bank (B1TCM) - ECC uncorrectable error | Group3 | 5 |
Reserved | Group3 | 6 |
FMC - uncorrectable error: bus1 and bus2 interfaces (does not include address parity error and errors on accesses to EEPROM bank) | Group3 | 7 |
Reserved | Group3 | 8 |
Reserved | Group3 | 9 |
Reserved | Group3 | 10 |
Reserved | Group3 | 11 |
Reserved | Group3 | 12 |
Reserved | Group3 | 13 |
Reserved | Group3 | 14 |
Reserved | Group3 | 15 |
Reserved | Group3 | 16 |
Reserved | Group3 | 17 |
Reserved | Group3 | 18 |
Reserved | Group3 | 19 |
Reserved | Group3 | 20 |
Reserved | Group3 | 21 |
Reserved | Group3 | 22 |
Reserved | Group3 | 23 |
Reserved | Group3 | 24 |
Reserved | Group3 | 25 |
Reserved | Group3 | 26 |
Reserved | Group3 | 27 |
Reserved | Group3 | 28 |
Reserved | Group3 | 29 |
Reserved | Group3 | 30 |
Reserved | Group3 | 31 |