SPNS226E June   2013  – November 2016 TMS570LS0714

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
      1. 4.1.1 PGE QFP Package Pinout (144-Pin)
      2. 4.1.2 PZ QFP Package Pinout (100-Pin)
    2. 4.2 Signal Descriptions
      1. 4.2.1 PGE Package Terminal Functions
        1. 4.2.1.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.2.1.2  Enhanced High-End Timer (N2HET) Modules
        3. 4.2.1.3  Enhanced Capture Modules (eCAP)
        4. 4.2.1.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.2.1.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.2.1.6  General-Purpose Input/Output (GIO)
        7. 4.2.1.7  Controller Area Network Controllers (DCAN)
        8. 4.2.1.8  Local Interconnect Network Interface Module (LIN)
        9. 4.2.1.9  Standard Serial Communication Interface (SCI)
        10. 4.2.1.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.2.1.11 Standard Serial Peripheral Interface (SPI)
        12. 4.2.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.2.1.13 System Module Interface
        14. 4.2.1.14 Clock Inputs and Outputs
        15. 4.2.1.15 Test and Debug Modules Interface
        16. 4.2.1.16 Flash Supply and Test Pads
        17. 4.2.1.17 Supply for Core Logic: 1.2V nominal
        18. 4.2.1.18 Supply for I/O Cells: 3.3V nominal
        19. 4.2.1.19 Ground Reference for All Supplies Except VCCAD
      2. 4.2.2 PZ Package Terminal Functions
        1. 4.2.2.1  High-End Timer (N2HET) Modules
        2. 4.2.2.2  Enhanced Capture Modules (eCAP)
        3. 4.2.2.3  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        4. 4.2.2.4  Enhanced Pulse-Width Modulator Modules (ePWM)
        5. 4.2.2.5  General-Purpose Input/Output (GIO)
        6. 4.2.2.6  Controller Area Network Interface Modules (DCAN1, DCAN2)
        7. 4.2.2.7  Standard Serial Peripheral Interfaces (SPI2 and SPI4)
        8. 4.2.2.8  Multibuffered Serial Peripheral Interface (MibSPI1 and MibSPI3)
        9. 4.2.2.9  Local Interconnect Network Controller (LIN)
        10. 4.2.2.10 Multibuffered Analog-to-Digital Converter (MibADC)
        11. 4.2.2.11 System Module Interface
        12. 4.2.2.12 Clock Inputs and Outputs
        13. 4.2.2.13 Test and Debug Modules Interface
        14. 4.2.2.14 Flash Supply and Test Pads
        15. 4.2.2.15 Supply for Core Logic: 1.2-V Nominal
        16. 4.2.2.16 Supply for I/O Cells: 3.3-V Nominal
        17. 4.2.2.17 Ground Reference for All Supplies Except VCCAD
    3. 4.3 Pin Multiplexing
      1. 4.3.1 Output Multiplexing
      2. 4.3.2 Multiplexing of Inputs
    4. 4.4 Buffer Type
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Input/Output Electrical Characteristics Over Recommended Operating Conditions
    6. 5.6 Power Consumption Over Recommended Operating Conditions
    7. 5.7 Thermal Resistance Characteristics
    8. 5.8 Timing and Switching Characteristics
      1. 5.8.1 SYSCLK (Frequencies)
        1. 5.8.1.1 Switching Characteristics over Recommended Operating Conditions for Clock Domains
        2. 5.8.1.2 Wait States Required - PGE and PZ Packages
  6. 6 System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power-On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate Clock Tree After GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low-Power Oscillator
          1. 6.6.1.2.1 Features
          2. 6.6.1.2.2 LPO Electrical and Timing Specifications
        3. 6.6.1.3 Phase-Locked Loop (PLL) Clock Module
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 6.9.4 Master/Slave Access Privileges
      5. 6.9.5 Special Notes on Accesses to Certain Slaves
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Program Flash
      6. 6.10.6 Data Flash
    11. 6.11 Tightly Coupled RAM Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAMW ECC Support
    12. 6.12 Parity Protection for Accesses to Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 Vectored Interrupt Manager
      1. 6.14.1 VIM Features
      2. 6.14.2 Interrupt Request Assignments
    15. 6.15 DMA Controller
      1. 6.15.1 DMA Features
      2. 6.15.2 Default DMA Request Map
    16. 6.16 Real-Time Interrupt Module
      1. 6.16.1 Features
      2. 6.16.2 Block Diagrams
      3. 6.16.3 Clock Source Options
      4. 6.16.4 Network Time Synchronization Inputs
    17. 6.17 Error Signaling Module
      1. 6.17.1 ESM Features
      2. 6.17.2 ESM Channel Assignments
    18. 6.18 Reset/Abort/Error Sources
    19. 6.19 Digital Windowed Watchdog
    20. 6.20 Debug Subsystem
      1. 6.20.1 Block Diagram
      2. 6.20.2 Debug Components Memory Map
      3. 6.20.3 JTAG Identification Code
      4. 6.20.4 Debug ROM
      5. 6.20.5 JTAG Scan Interface Timings
      6. 6.20.6 Advanced JTAG Security Module
      7. 6.20.7 Boundary Scan Chain
  7. 7 Peripheral Information and Electrical Specifications
    1. 7.1  I/O Timings
      1. 7.1.1 Input Timings
      2. 7.1.2 Output Timings
        1. 7.1.2.1 Low-EMI Output Buffers
    2. 7.2  Enhanced PWM Modules (ePWM)
      1. 7.2.1 ePWM Clocking and Reset
      2. 7.2.2 Synchronization of ePWMx Time-Base Counters
      3. 7.2.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 7.2.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 7.2.5 ePWM Synchronization with External Devices
      6. 7.2.6 ePWM Trip Zones
        1. 7.2.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 7.2.6.2 Trip Zone TZ4n
        3. 7.2.6.3 Trip Zone TZ5n
        4. 7.2.6.4 Trip Zone TZ6n
      7. 7.2.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 7.2.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
    3. 7.3  Enhanced Capture Modules (eCAP)
      1. 7.3.1 Clock Enable Control for eCAPx Modules
      2. 7.3.2 PWM Output Capability of eCAPx
      3. 7.3.3 Input Connection to eCAPx Modules
      4. 7.3.4 Enhanced Capture Module (eCAP) Electrical Data/Timing
    4. 7.4  Enhanced Quadrature Encoder (eQEP)
      1. 7.4.1 Clock Enable Control for eQEPx Modules
      2. 7.4.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 7.4.3 Input Connections to eQEPx Modules
      4. 7.4.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    5. 7.5  12-Bit Multibuffered Analog-to-Digital Converter (MibADC)
      1. 7.5.1 Features
      2. 7.5.2 Event Trigger Options
        1. 7.5.2.1 MibADC1 Event Trigger Hookup
        2. 7.5.2.2 MibADC2 Event Trigger Hookup
        3. 7.5.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 7.5.3 ADC Electrical and Timing Specifications
      4. 7.5.4 Performance (Accuracy) Specifications
        1. 7.5.4.1 MibADC Nonlinearity Errors
        2. 7.5.4.2 MibADC Total Error
    6. 7.6  General-Purpose Input/Output
      1. 7.6.1 Features
    7. 7.7  Enhanced High-End Timer (N2HET)
      1. 7.7.1 Features
      2. 7.7.2 N2HET RAM Organization
      3. 7.7.3 Input Timing Specifications
      4. 7.7.4 N2HET1 to N2HET2 Synchronization
      5. 7.7.5 N2HET Checking
        1. 7.7.5.1 Internal Monitoring
        2. 7.7.5.2 Output Monitoring Using Dual Clock Comparator (DCC)
      6. 7.7.6 Disabling N2HET Outputs
      7. 7.7.7 High-End Timer Transfer Unit (HET)
        1. 7.7.7.1 Features
        2. 7.7.7.2 Trigger Connections
    8. 7.8  Controller Area Network (DCAN)
      1. 7.8.1 Features
      2. 7.8.2 Electrical and Timing Specifications
    9. 7.9  Local Interconnect Network Interface (LIN)
      1. 7.9.1 LIN Features
    10. 7.10 Serial Communication Interface (SCI)
      1. 7.10.1 Features
    11. 7.11 Inter-Integrated Circuit (I2C) Module
      1. 7.11.1 Features
      2. 7.11.2 I2C I/O Timing Specifications
    12. 7.12 Multibuffered / Standard Serial Peripheral Interface
      1. 7.12.1 Features
      2. 7.12.2 MibSPI Transmit and Receive RAM Organization
      3. 7.12.3 MibSPI Transmit Trigger Events
        1. 7.12.3.1 MibSPI1 Event Trigger Hookup
        2. 7.12.3.2 MibSPI3 Event Trigger Hookup
        3. 7.12.3.3 MibSPI5 Event Trigger Hookup
      4. 7.12.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.12.5 SPI Slave Mode I/O Timings
  8. 8 Applications, Implementation, and Layout
    1. 8.1 TI Designs or Reference Designs
  9. 9 Device and Documentation Support
    1. 9.1  Getting Started and Next Steps
    2. 9.2  Device and Development-Support Tool Nomenclature
    3. 9.3  Tools and Software
      1. 9.3.1 Kits and Evaluation Modules for Hercules TMS570 MCUs
      2. 9.3.2 Development Tools
      3. 9.3.3 Software
    4. 9.4  Documentation Support
    5. 9.5  Community Resources
    6. 9.6  Trademarks
    7. 9.7  Electrostatic Discharge Caution
    8. 9.8  Glossary
    9. 9.9  Device Identification
      1. 9.9.1 Device Identification Code Register
      2. 9.9.2 Die Identification Registers
    10. 9.10 Module Certifications
      1. 9.10.1 DCAN Certification
      2. 9.10.2 LIN Certification
        1. 9.10.2.1 LIN Master Mode
        2. 9.10.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 9.10.2.3 LIN Slave Mode - Adaptive Baud Rate
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PGE|144
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Revision History

This data manual revision history highlights the technical changes made to the SPNS226D device-specific data manual to make it an SPNS226E revision.

Scope: Applicable updates to the TMS570LS0714 device family, specifically relating to the TMS570LS0714 devices (Silicon Revision A), which are now in the production data (PD) stage of development have been incorporated.

Changes from September 15, 2015 to November 1, 2016 (from D Revision (September 2015) to E Revision)

  • GLOBAL: PZ package is now fully qualifiedGo
  • Section 1.1 (Features): Updated/Changed the GIO pin count in GIO bulletGo
  • Section 1.1: Updated/Changed the SPI features bulletGo
  • Section 3.1 (Related Products): Added new section.Go
  • Section 4.2 (Signal Descriptions): Updated/Changed reference to Technical Reference ManualGo
  • Table 4-2 (PGE Enhanced High-End Timer Modules (N2HET)): Added a description for pins 14 and 55 (N2HET1_PIN_nDIS and N2HET2_PIN_nDIS, respectively).Go
  • Table 4-20 (PZ Enhanced High-End Timer Modules (N2HET)): Added Pin 10, GIOA[5] / INT[5] / EXTCLKIN /EPWM1A/N2HET1_PIN_nDISGo
  • Table 6-20 (Device Memory Map): Updated/Changed the FRAME SIZE column value for "Flash Data Space ECC" under Flash Module Bus2 Interface from "768KB" to "1MB".Go
  • Section 6.19 (Digital Windowed Watchdog): Added Figure 6-13, Digital Windowed Watchdog ExampleGo
  • Table 7-11 (eCAPx Clock Enable Control): Updated/Changed "ePWM" to "eCAP" in MODULE INSTANCE columnGo
  • Table 7-15 (eQEPx Clock Enable Control): Updated/Changed "ePWM" to "eQEP" in MODULE INSTANCE columnGo
  • Table 7-20 (MibADC1 Trigger Event Hookup): Added lead-in paragraph referencing the tableGo
  • Table 7-21 (MibADC2 Event Trigger Hookup): Added lead-in paragraph referencing the tableGo
  • Figure 7-11 (ePWM1SOC1A Switch Implementation): Added missing ePWM1 SOC1A detailed switch connection example and lead-in reference sentenceGo
  • Section 9.1 (Getting Started and Next Steps): Added new sectionGo
  • Section 9.2 (Device and Development-Support Tool Nomenclature): Moved subsection after "Getting Started and Next Steps" subsection (new)Go
  • Section 9.9.1 Added the address of the Device ID register.Go