SPNS226 Data sheet

SPNS226E June 2013 – November 2016 TMS570LS0714

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

PZ|100

Thermal pad, mechanical data (Package|Pins)

Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings⁽¹⁾

Over Operating Free-Air Temperature Range

		MIN	MAX	UNIT
Supply voltage range:	V_CC⁽²⁾	–0.3	1.43	V
	V_CCIO, V_CCP⁽²⁾	–0.3	4.6
	V_CCAD⁽²⁾	–0.3	6.25
Input voltage	All input pins, with exception of ADC pins	–0.3	4.6	V
Input voltage	ADC input pins	–0.3	6.25	V
Output voltage	All output pins	–0.3	4.6	V
Input clamp current	I_IK (V_I < 0 or V_I > V_CCIO) All pins, except AD1IN[23:0] or AD2IN[15:0]	–20	20	mA
	I_IK (V_I < 0 or V_I > V_CCAD) AD1IN[23:0] or AD2IN[15:0]	–10	10
	Total	–40	40
Output clamp current	I_OK (V_O < 0 or V_O > V_CCIO) All pins, except AWM1_EXT_x	–20	20	mA
Output clamp current	Total	–40	40	mA
Operating free-air temperature (T_A)		–40	125	°C
Operating junction temperature (T_J)		–40	150	°C
Storage temperature (T_stg)		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated grounds.

5.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge (ESD) performance:	Human Body Model (HBM), per AEC Q100-002⁽¹⁾		±2	kV
		Charged Device Model (CDM), per AEC Q100-011	All pins	±500	V
			100-pin PZ corner pins (1, 25, 26, 50, 51, 75, 76, 100)	±750	V
			144-pin PGE corner pins (1, 36, 37, 72, 73, 108, 109, 144)	±750	V

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS‑001 specification.

5.3 Power-On Hours (POH)⁽¹⁾⁽²⁾

NOMINAL CVDD VOLTAGE (V)	JUNCTION TEMPERATURE (Tj)	LIFETIME POH
1.2	105ºC	100K

(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products.

(2) To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table. To convert to equivalent POH for a specific temperature profile, see the Calculating Equivalent Power-on-Hours for Hercules Safety MCUs Application Report (SPNA207).

5.4 Recommended Operating Conditions⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
V_CC	Digital logic supply voltage (Core)		1.14	1.2	1.32	V
V_CCIO	Digital logic supply voltage (I/O)		3	3.3	3.6	V
V_CCAD	MibADC supply voltage		3		5.25	V
V_CCP	Flash pump supply voltage		3	3.3	3.6	V
V_SS	Digital logic supply ground			0		V
V_SSAD	MibADC supply ground		–0.1		0.1	V
V_ADREFHI	Analog-to-digital high-voltage reference source		V_SSAD		V_CCAD	V
V_ADREFLO	Analog-to-digital low-voltage reference source		V_SSAD		V_CCAD	V
V_SLEW	Maximum positive slew rate for V_CCIO, V_CCAD and V_CPP supplies				1	V/μs
V_hys	Input hysteresis	All inputs	180			mV
V_IL	Low-level input voltage	All inputs	–0.3		0.8	V
V_IH	High-level input voltage	All inputs	2		V_CCIO + 0.3	V
T_A	Operating free-air temperature		–40		125	°C
T_J	Operating junction temperature⁽²⁾		–40		150	°C

(1) All voltages are with respect to V_SS, except V_CCAD, which is with respect to V_SSAD

(2) Reliability data is based upon a temperature profile that is equivalent to 100,000 power-on hours at 105°C junction temperature.

5.5 Input/Output Electrical Characteristics Over Recommended Operating Conditions⁽¹⁾

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OL	Low-level output voltage		I_OL = I_OLmax			0.2V_CCIO	V
			I_OL = 50 µA, standard output mode			0.2
			I_OL = 50 µA, low-EMI output mode (see Section 7.1.2.1)			0.2V_CCIO
V_OH	High-level output voltage		I_OH = I_OHmax	0.8V_CCIO			V
			I_OH = 50 µA, standard output mode	V_CCIO - 0.3
			I_OH = 50 µA, low-EMI output mode (see Section 7.1.2.1)	0.8V_CCIO
I_IC	Input clamp current (I/O pins)		V_I < V_SSIO - 0.3 or V_I > V_CCIO + 0.3	–3.5		3.5	mA
I_I	Input current (I/O pins)	I_IH Pulldown 20 µA	V_I = V_CCIO	5		40	µA
		I_IH Pulldown 100 µA	V_I = V_CCIO	40		195
		I_IL Pullup 20 µA	V_I = V_SS	–40		–5
		I_IL Pullup 100 µA	V_I = V_SS	–195		–40
		All other pins	No pullup or pulldown	–1		1
C_I	Input capacitance				2		pF
C_O	Output capacitance				3		pF

(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.

5.6 Power Consumption Over Recommended Operating Conditions

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
I_CC	V_CC digital supply current (operating mode) f_VCLK = f_HCLK/2; Flash in pipelined mode; V_CCmax	f_HCLK = 100 MHz	130 ⁽³⁾	270 ⁽¹⁾	mA
		f_HCLK = 160 MHz	160 ⁽³⁾	300 ⁽¹⁾	mA
	V_CC digital supply current (LBIST/PBIST mode)	LBIST/PBIST clock frequency = 50 MHz	150⁽³⁾	290⁽²⁾⁽⁴⁾	mA
		LBIST/PBIST clock frequency = 80 MHz	215⁽³⁾	360 ⁽²⁾⁽⁴⁾
		LBIST/PBIST clock frequency = 90 MHz	240⁽³⁾	390 ⁽²⁾⁽⁴⁾
I_CCIO	V_CCIO digital supply current (operating mode)	No DC load, V_CCmax		15	mA
I_CCAD	V_CCAD supply current (operating mode)	Single ADC operational, V_CCADmax		15	mA
I_CCAD	V_CCAD supply current (operating mode)	Both ADCs operational, V_CCADmax		30	mA
I_CCREFHI	AD_REFHI supply current (operating mode)	Single ADC operational, AD_REFHImax		3	mA
I_CCREFHI	AD_REFHI supply current (operating mode)	Both ADCs operational, AD_REFHImax		6	mA
I_CCP	V_CCP supply current	Read from 1 bank and program another bank, V_CCPmax		55	mA

(1) The maximum I_CC,value can be derated

linearly with voltage
by 0.85 mA/MHz for lower operating frequency when f_HCLK= 2 * f_VCLK
for lower junction temperature by the equation below where T_JK is the junction temperature in Kelvin and the result is in milliamperes.
126 - 0.005 e^{0.024 T_JK}

(2) The maximum I_CC,value can be derated

linearly with voltage
by 0.85 mA/MHz for lower operating frequency
for lower junction temperature by the equation below where T_JK is the junction temperature in Kelvin and the result is in milliamperes.
126 - 0.005 e^{0.024 T_JK}

(3) The typical value is the average current for the nominal process corner and junction temperature of 25°C.

(4) LBIST and PBIST currents are for a short duration, typically less than 10 ms. They are usually ignored for thermal calculations for the device and the voltage regulator.

5.7 Thermal Resistance Characteristics

Table 5-1 shows the thermal resistance characteristics for the QFP - PGE mechanical package.

Table 5-2 shows the thermal resistance characteristics for the QFP - PZ mechanical package.

Table 5-1 Thermal Resistance Characteristics (PGE Package)

		°C/W
RΘ_JA	Junction-to-free air thermal resistance, still air using JEDEC 2S2P test board	37.5
RΘ_JB	Junction-to-board thermal resistance	19.7
RΘ_JC	Junction-to-case thermal resistance	9.4
Ψ_JT	Junction-to-package top, Still air	0.40

Table 5-2 Thermal Resistance Characteristics (PZ Package)

		°C/W
RΘ_JA	Junction-to-free air thermal resistance, still air using JEDEC 2S2P test board	43.5
RΘ_JB	Junction-to-board thermal resistance	21.6
RΘ_JC	Junction-to-case thermal resistance	11.2
Ψ_JT	Junction-to-package top, Still air	0.50

5.8 Timing and Switching Characteristics

5.8.1 SYSCLK (Frequencies)

5.8.1.1 Switching Characteristics over Recommended Operating Conditions for Clock Domains

Table 5-3 Clock Domain Timing Specifications

PARAMETER	DESCRIPTION	CONDITIONS		MAX	UNIT
f_HCLK	HCLK - System clock frequency	PZ	Pipeline mode enabled	100	MHz
		PZ	Pipeline mode disabled	45
		PGE	Pipeline mode enabled	160
		PGE	Pipeline mode disabled	50
f_GCLK	GCLK - CPU clock frequency			f_HCLK	MHz
f_VCLK	VCLK - Primary peripheral clock frequency			100	MHz
f_VCLK2	VCLK2 - Secondary peripheral clock frequency			100	MHz
f_VCLK4	VCLK4 - Secondary peripheral clock frequency			150	MHz
f_VCLKA1	VCLKA1 - Primary asynchronous peripheral clock frequency			100	MHz
f_RTICLK	RTICLK - Clock frequency			f_VCLK	MHz

5.8.1.2 Wait States Required - PGE and PZ Packages

TMS570LS0714 wait_states_new_spns225_160MHz.gif

Figure 5-1 Wait States Scheme — PGE, 160 MHz

TMS570LS0714 wait_states_new_spns225_100MHz.gif

Figure 5-2 Wait States Scheme — PZ, 100 MHz

As shown in Figure 5-1 and Figure 5-2, the TCM RAM can support program and data fetches at full CPU speed without any address or data wait states required.

The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined mode. The flash supports a maximum CPU clock speed of 160 MHz in pipelined mode for the PGE Package, and 100 MHz for the PZ package.

The flash wrapper defaults to nonpipelined mode with zero address wait state and one random-read data wait state.