SPNS225D June 2013 – November 2016 TMS570LS0914
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The signal descriptions section shows pin information in module function order per package.
Section 4.2.1 and Section 4.2.2 identify the external signal names, the associated pin or ball numbers along with the mechanical package designator, the pin or ball type (Input, Output, I/O, Power, or Ground), whether the pin or ball has any internal pullup/pulldown, whether the pin or ball can be configured as a GIO, and a functional pin or ball description. The first signal name listed is the primary function for that terminal (pin or ball). The signal name in Bold is the function being described. For information on how to select between different multiplexed functions, see Section 4.3, Pin Multiplexing or see the I/O Multiplexing and Control Module (IOMM) chapter of the TMS570LS09x/07x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (SPNU607).
NOTE
All I/O signals except nRST are configured as inputs while nPORRST is low and immediately after nPORRST goes high.
All output-only signals are configured as high impedance while nPORRST is low, and are configured as outputs immediately after nPORRST goes high.
While nPORRST is low, the input buffers are disabled, and the output buffers are high impedance.
In the Terminal Functions tables of Section 4.2.1 and Section 4.2.2, the RESET PULL STATE is the state of the pullup or pulldown while nPORRST is low and immediately after nPORRST goes high. The default pull direction may change when software configures the pin for an alternate function. The PULL TYPE is the type of pull asserted when the signal name in bold is enabled for the given terminal.
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
ADREFHI(1) | 66 | Power | – | None | ADC high reference supply |
ADREFLO(1) | 67 | Power | ADC low reference supply | ||
VCCAD(1) | 69 | Power | Operating supply for ADC | ||
VSSAD(1) | 68 | Ground | |||
AD1EVT | 86 | I/O | Pulldown | Programmable, 20 µA | ADC1 event trigger input, or GIO |
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS |
55 | I/O | Pullup | Programmable, 20 µA | ADC2 event trigger input, or GIO |
AD1IN[0] | 60 | Input | – | None | ADC1 analog input |
AD1IN[01] | 71 | ||||
AD1IN[02] | 73 | ||||
AD1IN[03] | 74 | ||||
AD1IN[04] | 76 | ||||
AD1IN[05] | 78 | ||||
AD1IN[06] | 80 | ||||
AD1IN[07] | 61 | ||||
AD1IN[08] / AD2IN[08] | 83 | Input | – | None | ADC1/ADC2 shared analog inputs |
AD1IN[09] / AD2IN[09] | 70 | ||||
AD1IN[10] / AD2IN[10] | 72 | ||||
AD1IN[11] / AD2IN[11] | 75 | ||||
AD1IN[12] / AD2IN[12] | 77 | ||||
AD1IN[13] / AD2IN[13] | 79 | ||||
AD1IN[14] / AD2IN[14] | 82 | ||||
AD1IN[15] / AD2IN[15] | 85 | ||||
AD1IN[16] / AD2IN[0] | 58 | ||||
AD1IN[17] / AD2IN[01] | 59 | ||||
AD1IN[18] / AD2IN[02] | 62 | ||||
AD1IN[19] / AD2IN[03] | 63 | ||||
AD1IN[20] / AD2IN[04] | 64 | ||||
AD1IN[21] / AD2IN[05] | 65 | ||||
AD1IN[22] / AD2IN[06] | 81 | ||||
AD1IN[23] / AD2IN[07] | 84 | ||||
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 | 51 | Output | Pullup | – | AWM1 external analog mux enable |
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 | 52 | Output | Pullup | – | AWM1 external analog mux select line0 |
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A | 53 | Output | Pullup | – | AWM1 external analog mux select line0 |
TERMINAL | SIGNAL TYPE | RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 | 41 | I/O | Pulldown | Fixed, 20 µA | Enhanced Capture Module 1 I/O |
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 | 51 | Pullup | Enhanced Capture Module 2 I/O | ||
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 | 52 | Enhanced Capture Module 3 I/O | |||
MIBSPI1NENA/N2HET1[23]/ECAP4 | 96 | Enhanced Capture Module 4 I/O | |||
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5 | 97 | Enhanced Capture Module 5 I/O | |||
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 | 105 | Enhanced Capture Module 6 I/O |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A | 53 | Input | Pullup | Fixed, 20 µA | Enhanced QEP1 Input A |
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B | 54 | Input | Enhanced QEP1 Input B | ||
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDIS | 55 | I/O | Enhanced QEP1 Index | ||
MIBSPI1NCS[1]/N2HET1[17]//EQEP1S | 130 | I/O | Enhanced QEP1 Strobe | ||
N2HET1[01]/SPI4NENA/N2HET2[8]/EQEP2A | 23 | Input | Pulldown | Enhanced QEP2 Input A | |
N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B | 24 | Input | Enhanced QEP2 Input B | ||
GIOA[2]/N2HET2[0]/EQEP2I | 9 | I/O | Enhanced QEP2 Index | ||
N2HET1[30]/EQEP2S | 127 | I/O | Enhanced QEP2 Strobe |
TERMINAL | SIGNAL TYPE | RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
GIOA[5]/EXTCLKIN1/EPWM1A/N2HET1_PIN_nDIS | 14 | Output | Pulldown | – | Enhanced PWM1 Output A |
GIOA[6]/N2HET2[4]/EPWM1B | 16 | Enhanced PWM1 Output B | |||
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO | 6 | External ePWM Sync Pulse Output | |||
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO | 139 | Input | Pullup | Fixed, 20 µA | External ePWM Sync Pulse Output |
GIOA[7]/N2HET2[6]/EPWM2A | 22 | Output | Pulldown | – | Enhanced PWM2 Output A |
N2HET1[0]/SPI4CLK/EPWM2B | 25 | Enhanced PWM2 Output B | |||
N2HET1[02]/SPI4SIMO[0]/EPWM3A | 30 | Enhanced PWM3 Output A | |||
N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EPWM3B | 31 | Enhanced PWM3 Output B | |||
MIBSPI5NCS[0]/EPWM4A | 32 | Output | Pullup | – | Enhanced PWM4 Output A |
N2HET1[04]/EPWM4B | 36 | Output | Pulldown | – | Enhanced PWM4 Output B |
N2HET1[06]/SCIRX/EPWM5A | 38 | Enhanced PWM5 Output A | |||
N2HET1[13]/SCITX/EPWM5B | 39 | Enhanced PWM5 Output B | |||
N2HET1[18]/EPWM6A | 140 | Enhanced PWM6 Output A | |||
N2HET1[20]/EPWM6B | 141 | Enhanced PWM6 Output B | |||
N2HET1[09]/N2HET2[16]/EPWM7A | 35 | Enhanced PWM7 Output A | |||
N2HET1[07]/N2HET2[14]/EPWM7B | 33 | Enhanced PWM7 Output B | |||
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1 | 3 | Input | Pullup | Fixed, 20 µA | Trip Zone Inputs 1, 2 and 3. These signals are either connected asynchronously to the ePWMx trip zone inputs, or double-synchronized with VCLK4, or double-synchronized and then filtered with a 6-cycle VCLK4-based counter before connecting to the ePWMx trip zone inputs. |
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2 | 4 | ||||
N2HET1[10]/nTZ3 | 118 | Pulldown |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
GIOA[0] | 2 | I/O | Pulldown | Programmable, 20 µA | General-purpose I/O. All GIO terminals are capable of generating interrupts to the CPU on rising / falling / both edges. |
GIOA[1] | 5 | ||||
GIOA[2]/N2HET2[0]/EQEPII | 9 | ||||
GIOA[5]/EXTCLKIN1/EPWM1A/N2HET1_PIN_nDIS | 14 | ||||
GIOA[6]/N2HET2[4]/EPWM1B | 16 | ||||
GIOA[7]/N2HET2[6]/EPWM2A | 22 | ||||
GIOB[0] | 126 | ||||
GIOB[1] | 133 | ||||
GIOB[2] | 142 | ||||
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDIS | 55(1) | Pullup | |||
GIOB[3] | 1 | Pulldown |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
CAN1RX | 90 | I/O | Pullup | Programmable, 20 µA | CAN1 receive, or GIO |
CAN1TX | 89 | CAN1 transmit, or GIO | |||
CAN2RX | 129 | CAN2 receive, or GIO | |||
CAN2TX | 128 | CAN2 transmit, or GIO | |||
CAN3RX | 12 | CAN3 receive, or GIO | |||
CAN3TX | 13 | CAN3 transmit, or GIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
LINRX | 131 | I/O | Pullup | Programmable, 20 µA | LIN receive, or GIO |
LINTX | 132 | LIN transmit, or GIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
N2HET1[06]/SCIRX/EPWM5A | 38 | I/O | Pulldown | Programmable, 20 µA | SCI receive, or GIO |
N2HET1[13]/SCITX/EPWM5B | 39 | SCI transmit, or GIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2 | 4 | I/O | Pullup | Programmable, 20 µA | I2C serial data, or GIO |
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1 | 3 | I2C serial clock, or GIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
N2HET1[0]/SPI4CLK/EPWM2B | 25 | I/O | Pulldown | Programmable, 20 µA | SPI4 clock, or GIO |
N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B | 24 | SPI4 chip select, or GIO | |||
N2HET1[01]/SPI4NENA/N2HET2[8]/EQEP2A | 23 | SPI4 enable, or GIO | |||
N2HET1[02]/SPI4SIMO[0]/EPWM3A | 30 | SPI4 slave-input master-output, or GIO | |||
N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EPWM3B | 31 | SPI4 slave-output master-input, or GIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
MIBSPI1CLK | 95 | I/O | Pullup | Programmable, 20 µA | MibSPI1 clock, or GIO |
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 | 105 | MibSPI1 chip select, or GIO | |||
MIBSPI1NCS[1]/N2HET1[17]//EQEP1S | 130 | ||||
MIBSPI1NCS[2]/N2HET1[19]/ | 40 | ||||
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 | 41 | Pulldown | Programmable, 20 µA | MibSPI1 chip select, or GIO | |
N2HET1[24]/MIBSPI1NCS[5] | 91 | ||||
MIBSPI1NENA/N2HET1[23]/ECAP4 | 96 | Pullup | Programmable, 20 µA | MibSPI1 enable, or GIO | |
MIBSPI1SIMO[0] | 93 | MibSPI1 slave-in master-out, or GIO | |||
N2HET1[08]/MIBSPI1SIMO[1] | 106 | Pulldown | Programmable, 20 µA | MibSPI1 slave-in master-out, or GIO | |
MIBSPI1SOMI[0] | 94 | Pullup | Programmable, 20 µA | MibSPI1 slave-out master-in, or GIO | |
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 | 105 | ||||
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A | 53 | I/O | Pullup | Programmable, 20 µA | MibSPI3 clock, or GIO |
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDIS | 55 | MibSPI3 chip select, or GIO | |||
MIBSPI3NCS[1]/N2HET1[25] | 37 | ||||
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2 | 4 | ||||
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1 | 3 | ||||
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO | 6 | Pulldown | Programmable, 20 µA | MibSPI3 chip select, or GIO | |
MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]/EQEP1B | 54 | Pullup | Programmable, 20 µA | MibSPI3 chip select, or GIO | |
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B | 54 | MibSPI3 enable, or GIO | |||
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 | 52 | MibSPI3 slave-in master-out, or GIO | |||
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 | 51 | MibSPI3 slave-out master-in, or GIO | |||
MIBSPI5CLK | 100 | I/O | Pullup | Programmable, 20 µA | MibSPI5 clock, or GIO |
MIBSPI5NCS[0]/EPWM4A | 32 | MibSPI5 chip select, or GIO | |||
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5 | 97 | MibSPI5 enable, or GIO | |||
MIBSPI5SIMO[0]/MIBSPI5SOMI[2] | 99 | MibSPI5 slave-in master-out, or GIO | |||
MIBSPI5SOMI[0] | 98 | MibSPI5 slave-out master-in, or GIO | |||
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5 | 97 | MibSPI5 SOMI[0], or GIO | |||
MIBSPI5SIMO[0]/MIBSPI5SOMI[2] | 99 | MibSPI5 SOMI[0], or GIO |
TERMINAL | SIGNAL TYPE | RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
nPORRST | 46 | Input | Pulldown | 100 µA | Power-on reset, cold reset External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter. See . |
nRST | 116 | I/O | Pullup | 100 µA | System reset, warm reset, bidirectional. The internal circuitry indicates any reset condition by driving nRST low. The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal. This terminal has a glitch filter. See . |
nERROR | 117 | I/O | Pulldown | 20 µA | ESM Error Signal Indicates error of high severity. See . |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
OSCIN | 18 | Input | – | None | From external crystal/resonator, or external clock input |
KELVIN_GND | 19 | Input | Kelvin ground for oscillator | ||
OSCOUT | 20 | Output | To external crystal/resonator | ||
ECLK | 119 | I/O | Pulldown | Programmable, 20 µA | External prescaled clock output, or GIO. |
GIOA[5]/EXTCLKIN1/EPWM1A /N2HET1_PIN_nDIS | 14 | Input | Pulldown | 20 µA | External clock input #1 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
TEST | 34 | Input | Pulldown | Fixed, 100 µA | Test enable. This terminal must be connected to ground directly or via a pulldown resistor. |
nTRST | 109 | Input | JTAG test hardware reset | ||
RTCK | 113 | Output | - | None | JTAG return test clock |
TCK | 112 | Input | Pulldown | Fixed, 100 µA | JTAG test clock |
TDI | 110 | Input | Pullup | JTAG test data in | |
TDO | 111 | Output | Pulldown | JTAG test data out | |
TMS | 108 | Input | Pullup | JTAG test select |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
VCCP | 134 | 3.3-V Power | – | None | Flash pump supply |
FLTP1 | 7 | – | – | None | Flash test pads. These terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)]. |
FLTP2 | 8 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
VCC | 17 | 1.2-V Power | – | None | Core supply |
VCC | 29 | ||||
VCC | 45 | ||||
VCC | 48 | ||||
VCC | 49 | ||||
VCC | 57 | ||||
VCC | 87 | ||||
VCC | 101 | ||||
VCC | 114 | ||||
VCC | 123 | ||||
VCC | 137 | ||||
VCC | 143 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
VCCIO | 10 | 3.3-V Power | – | None | Operating supply for I/Os |
VCCIO | 26 | ||||
VCCIO | 42 | ||||
VCCIO | 104 | ||||
VCCIO | 120 | ||||
VCCIO | 136 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
VSS | 11 | Ground | – | None | Ground reference |
VSS | 21 | ||||
VSS | 27 | ||||
VSS | 28 | ||||
VSS | 43 | ||||
VSS | 44 | ||||
VSS | 47 | ||||
VSS | 50 | ||||
VSS | 56 | ||||
VSS | 88 | ||||
VSS | 102 | ||||
VSS | 103 | ||||
VSS | 115 | ||||
VSS | 121 | ||||
VSS | 122 | ||||
VSS | 135 | ||||
VSS | 138 | ||||
VSS | 144 |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
N2HET1[0]/ SPI4CLK / EPWM2B | 19 | I/O | Pulldown | Programmable, 20 µA |
N2HET2 timer input capture or output compare, or GIO. Each terminal has a suppression filter with a programmable duration. Timer input capture or output compare. The N2HET applicable terminals can be programmed as general-purpose input/output (GIO). |
N2HET1[2] / SPI4SIMO / EPWM3A | 22 | ||||
N2HET1[4] / EPWM4B | 25 | ||||
N2HET1[6] / SCIRX / EPWM5A | 26 | ||||
N2HET1[8] / MIBSPI1SIMO[1] | 74 | ||||
N2HET1[10] / nTZ3 | 83 | ||||
N2HET1[12] | 89 | ||||
N2HET1[14] | 90 | ||||
N2HET1[16] / EPWM1SYNCI / EPWM1SYNCO | 97 | ||||
MIBSPI1nCS[1] / N2HET1[17] / EQEP1S | 93 | Pullup | |||
N2HET1[18] / EPWM6A | 98 | Pulldown | |||
MIBSPI1nCS[2] / N2HET1[19] | 27 | Pullup | |||
MIBSPI1nCS[3] / N2HET1[21] | 39 | ||||
N2HET1[22] | 11 | Pulldown | |||
MIBSPI1nENA / N2HET1[23] / ECAP4 | 68 | Pullup | |||
N2HET1[24] / MIBSPI1nCS[5] | 64 | Pulldown | |||
MIBSPI3nENA / MIBSPI3nCS[5] / N2HET1[31] / EQEP1B | 37 | Pullup | |||
GIOA[5] / INT[5] / EXTCLKIN /EPWM1A/N2HET1_PIN_nDIS | 10 | Pulldown | Disable selected PWM outputs | ||
GIOA[2] / INT[2] / N2HET2[0] / EQEP2I | 5 | Pulldown |
N2HET2 timer input capture or output compare, or GIO. Each terminal has a suppression filter with a programmable duration. Timer input capture or output compare. The N2HET applicable terminals can be programmed as general-purpose input/output (GIO). |
||
GIOA[3] / INT[3] / N2HET2[2] | 8 | ||||
GIOA[6] / INT[6] / N2HET2[4] / EPWM1B | 12 | ||||
GIOA[7] / INT[7] / N2HET2[6] / EPWM2A | 18 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 100 PZ | ||||
MIBSPI3SOMI[0] / AWM1_EXT_ENA / ECAP2 | 34 | I/O | Pullup | Fixed, 20 µA | Enhanced Capture Module 2 I/O |
MIBSPI3SIMO[0] / AWM1_EXT_SEL[0] / ECAP3 | 35 | Enhanced Capture Module 3 I/O | |||
MIBSPI1NENA / N2HET1[23] / ECAP4 | 68 | Enhanced Capture Module 4 I/O | |||
MIBSPI1NCS[0] / MIBSPI1SOMI[1] / ECAP6 | 73 | Enhanced Capture Module 6 I/O |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
MIBSPI3CLK / AWM1_EXT_SEL[1] / EQEP1A | 36 | I/O | Pullup | Fixed, 20 µA | Enhanced QEP1 Input A |
MIBSPI3nENA / MIBSPI3nCS[5] / N2HET1[31] / EQEP1B | 37 | Enhanced QEP1 Input B | |||
MIBSPI3nCS[0] / AD2EVT / GIOB[2] / EQEP1I/N2HET2_PIN_nDIS | 38 | Enhanced QEP1 Index | |||
MIBSPI1nCS[1] / N2HET1[17] / EQEP1S | 93 | Enhanced QEP1 Strobe | |||
GIOA[2] / INT[2] / N2HET2[0] / EQEP2I | 5 | Pulldown | Enhanced QEP2 Index |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
GIOA[5] / INT[5] / EXTCLKIN / EPWM1A/N2HET1_PIN_nDIS | 10 | Output | Pulldown | – | Enhanced PWM1 Output A |
GIOA[6] / INT[6] / N2HET2[4] / EPWM1B | 12 | Pulldown | Enhanced PWM1 Output B | ||
N2HET1[16] / EPWM1SYNCI / EPWM1SYNCO | 97 | Input | Pulldown | Fixed, 20 µA | External ePWM Sync Pulse Input |
N2HET1[16] / EPWM1SYNCI / EPWM1SYNCO | 97 | Output | Pulldown | – | External ePWM Sync Pulse Output |
GIOA[7] / INT[7] / N2HET2[6] / EPWM2A | 18 | Enhanced PWM2 Output A | |||
N2HET1[0] / SPI4CLK / EPWM2B | 19 | Enhanced PWM2 Output B | |||
N2HET1[2] / SPI4SIMO / EPWM3A | 22 | Enhanced PWM3 Output A | |||
N2HET1[4] / EPWM4B | 25 | Enhanced PWM4 Output B | |||
N2HET1[6] / SCIRX / EPWM5A | 26 | Enhanced PWM5 Output A | |||
N2HET1[18] / EPWM6A | 98 | Enhanced PWM6 Output A | |||
N2HET1[10] / nTZ3 | 83 | Input | Pulldown | Trip Zone 1 input 3 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 100 PZ | ||||
GIOA | |||||
GIOA[0] / INT[0] | 1 | I/O | Pulldown | Programmable, 20 µA | General-purpose input/output All GPIO terminals are capable of generating interrupts to the CPU on rising/falling/both edges. |
GIOA[1] / INT[1] | 2 | ||||
GIOA[2] / INT[2] / N2HET2[0] / EQEP2I | 5 | ||||
GIOA[3] / INT[3] / N2HET2[2] | 8 | ||||
GIOA[4]/ INT[4] | 9 | ||||
GIOA[5] / INT[5] / EXTCLKIN / EPWM1A/ N2HET1_PIN_nDIS | 10 | ||||
GIOA[6] / INT[6] / N2HET2[4] / EPWM1B | 12 | ||||
GIOA[7] / INT[7] / N2HET2[6] / EPWM2A | 18 | ||||
GIOB | |||||
MIBSPI3nCS[0] / AD2EVT / GIOB[2] / EQEP1I/N2HET2_PIN_nDIS | 38 | I/O | General-purpose input/output |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 100 PZ | ||||
DCAN1 | |||||
CAN1RX | 63 | I/O | Pullup | Programmable, 20 µA | CAN1 Receive, or general-purpose I/O (GPIO) |
CAN1TX | 62 | CAN1 Transmit, or GPIO | |||
DCAN2 | |||||
CAN2RX | 92 | I/O | Pullup | Programmable, 20 µA | CAN2 Receive, or GPIO |
CAN2TX | 91 | CAN2 Transmit, or GPIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 100 PZ | ||||
SPI2 | |||||
SPI2CLK | 71 | I/O | Pullup | Programmable, 20 µA | SPI2 Serial Clock, or GPIO |
SPI2nCS[0] | 23 | SPI2 Chip Select, or GPIO | |||
SPI2SIMO | 70 | SPI2 Slave-In-Master-Out, or GPIO | |||
SPI2SOMI | 69 | SPI2 Slave-Out-Master-In, or GPIO | |||
The drive strengths for the SPI2CLK, SPI2SIMO and SPI2SOMI signals are selected individually by configuring the respective SRS bits of the SPIPC9 register fo SPI2. SRS = 0 for 8mA drive (fast). This is the default mode as the SRS bits in the SPIPC9 register default to 0. SRS = 1 for 2mA drive (slow) |
|||||
SPI4 | |||||
N2HET1[0] / SPI4CLK / EPWM2B | 19 | I/O | Pulldown | Programmable, 20 µA | SPI2 Serial Clock, or GPIO |
N2HET1[2] / SPI4SIMO / EPWM3A | 22 | SPI2 Slave-In-Master-Out, or GPIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 100 PZ | ||||
MibSPI1 | |||||
MIBSPI1CLK | 67 | I/O | Pullup | Programmable, 20 µA | MibSPI1 Serial Clock, or GPIO |
MIBSPI1nCS[0]/MIBSPI1SOMI[1]/ ECAP6 |
73 | MibSPI1 Chip Select, or GPIO | |||
MIBSPI1nCS[1]/N2HET1[17]/ EQEP1S |
93 | ||||
MIBSPI1nCS[2]/N2HET1[19] | 27 | ||||
MIBSPI1nCS[3]/N2HET1[21] | 39 | ||||
MIBSPI1nENA/N2HET1[23]/ ECAP4 |
68 | MibSPI1 Enable, or GPIO | |||
MIBSPI1SIMO[0] | 65 | MibSPI1 Slave-In-Master-Out, or GPIO | |||
N2HET1[8]/MIBSPI1SIMO[1] | 74 | ||||
MIBSPI1SOMI[0] | 66 | MibSPI1 Slave-Out-Master-In, or GPIO | |||
MIBSPI1nCS[0]/MIBSPI1SOMI[1]/ ECAP6 |
73 | ||||
MibSPI3 | |||||
MIBSPI3CLK/AWM1_EXT_SEL[1]/ EQEP1A |
36 | I/O | Pullup | Programmable, 20 µA | MibSPI3 Serial Clock, or GPIO |
MIBSPI3nCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS |
38 | MibSPI3 Chip Select, or GPIO | |||
MIBSPI3nENA/MIBSPI3nCS[5]/ N2HET1[31]/EQEP1B |
37 | ||||
MIBSPI3nENA/MIBSPI3nCS[5]/ N2HET1[31]/EQEP1B |
37 | MibSPI3 Enable, or GPIO | |||
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ ECAP3 |
35 | MibSPI3 Slave-In-Master-Out, or GPIO | |||
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ ECAP2 |
34 | MibSPI3 Slave-Out-Master-In, or GPIO |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
LINRX | 94 | I/O | Pullup | Programmable, 20 µA | LIN Receive, or GPIO |
LINTX | 95 | LIN Transmit, or GPIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 100 PZ | ||||
MibADC1 | |||||
AD1EVT | 58 | I/O | Pulldown | Programmable, 20 µA | ADC1 Event Trigger or GPIO |
AD1IN[0] | 42 | Input | – | – | Analog Inputs |
AD1IN[1] | 49 | ||||
AD1IN[2] | 51 | ||||
AD1IN[3] | 52 | ||||
AD1IN[4] | 54 | ||||
AD1IN[5] | 55 | ||||
AD1IN[6] | 56 | ||||
AD1IN[7] | 43 | ||||
AD1IN[8]/AD2IN[8] | 57 | ||||
AD1IN[9]/AD2IN[9] | 48 | ||||
AD1IN[10]/AD2IN[10] | 50 | ||||
AD1IN[11]/AD2IN[11] | 53 | ||||
AD1IN[16]/AD2IN[0] | 40 | ||||
AD1IN[17]/AD2IN[1] | 41 | ||||
AD1IN[20]/AD2IN[4] | 44 | ||||
AD1IN[21]/AD2IN[5] | 45 | ||||
ADREFHI/VCCAD | 46 | Input/ Power |
– | – | ADC High Reference Level/ADC Operating Supply |
ADREFLO/VSSAD | 47 | Input/ Ground |
– | – | ADC Low Reference Level/ADC Supply Ground |
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ ECAP2 |
34 | AWM external analog mux enable | |||
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ ECAP3 |
35 | AWM external analog mux select line 0 | |||
MIBSPI3CLK/AWM1_EXT_SEL[1]/ EQEP1A |
36 | AWM external analog mux select line1 | |||
MibADC2 | |||||
MIBSPI3nCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS |
38 | I/O | ADC2 Event Trigger or GPIO |
TERMINAL | SIGNAL TYPE | RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
nPORRST | 31 | Input | Pullup | 100 µA | Power-on reset, cold reset External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter. See . |
nRST | 81 | I/O | Pullup | 100 µA | The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal. This terminal has a glitch filter. See . |
nERROR | 82 | I/O | Pulldown | 20 µA | ESM Error Signal. Indicates error of high severity. See . |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
OSCIN | 14 | Input | – | – | From external crystal/resonator, or external clock input |
KELVIN_GND | 15 | Input | – | – | Dedicated ground for oscillator |
OSCOUT | 16 | Output | – | – | To external crystal/resonator |
ECLK | 84 | I/O | Pulldown | Programmable, 20 µA | External prescaled clock output, or GIO. |
GIOA[5]/INT[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS | 10 | Input | Pulldown | 20 µA | External Clock In |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
nTRST | 76 | Input | Pulldown | Fixed, 100 µA | JTAG test hardware reset |
RTCK | 80 | Output | – | – | JTAG return test clock |
TCK | 79 | Input | Pulldown | Fixed, 100 µA | JTAG test clock |
TDI | 77 | I/O | Pullup | Fixed, 100 µA | JTAG test data in |
TDO | 78 | I/O | Pulldown | Fixed, 100 µA | JTAG test data out |
TMS | 75 | I/O | Pullup | Fixed, 100 µA | JTAG test select |
TEST | 24 | I/O | Pulldown | Fixed, 100 µA | Test enable. This terminal must be connected to ground directly or via a pulldown resistor. |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 100 PZ | ||||
VCCP | 96 | 3.3-V Power | – | – | Flash external pump voltage (3.3 V). This terminal is required for both Flash read and Flash program and erase operations. |
FLTP1 | 3 | Input | – | – | Flash Test Pins. For proper operation this terminal must connect only to a test pad or not be connected at all [no connect (NC)]. The test pad must not be exposed in the final product where it might be subjected to an ESD event. |
FLTP2 | 4 | Input | – | – |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 100 PZ | ||||
VCC | 13 | 1.2-V Power | – | – | Digital logic and RAM supply |
VCC | 21 | ||||
VCC | 30 | ||||
VCC | 32 | ||||
VCC | 61 | ||||
VCC | 88 | ||||
VCC | 99 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 100 PZ | ||||
VCCIO | 6 | 3.3-V Power | – | – | I/O Supply |
VCCIO | 28 | ||||
VCCIO | 60 | ||||
VCCIO | 85 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 100 PZ | ||||
VSS | 7 | Ground | – | – | Device Ground Reference. This is a single ground reference for all supplies except for the ADC Supply. |
VSS | 17 | ||||
VSS | 20 | ||||
VSS | 29 | ||||
VSS | 33 | ||||
VSS | 59 | ||||
VSS | 72 | ||||
VSS | 86 | ||||
VSS | 87 | ||||
VSS | 100 |
This microcontroller has several interfaces and uses extensive multiplexing to bring out the functions as required by the target application. The multiplexing is mostly on the output signals. A few inputs are also multiplexed to allow the same input signal to be driven in from a selected terminal.
Table 4-37 and Table 4-38 show the pin multiplexing control x register (PINMMRx) and the associated bit fields that control each pin mux function.
144-PIN PGE |
DEFAULT FUNCTION |
CTRL1 | OPTION 2 | CTRL2 | OPTION 3 | CTRL3 | OPTION 4 | CTRL4 | OPTION 5 | CTRL5 | OPTION 6 | CTRL6 |
---|---|---|---|---|---|---|---|---|---|---|---|---|
86 | AD1EVT | 10[0] | ||||||||||
2 | GIOA[0] | 0[8] | ||||||||||
5 | GIOA[1] | 1[0] | ||||||||||
9 | GIOA[2] | 2[0] | N2HET2[0] | 2[3] | EQEP2I | 2[4] | ||||||
14 | GIOA[5] | 2[24] | EXTCLKIN1 | 2[25] | EPWM1A | 2[26] | ||||||
16 | GIOA[6] | 3[16] | N2HET2[4] | 3[17] | EPWM1B | 3[18] | ||||||
22 | GIOA[7] | 4[0] | N2HET2[6] | 4[1] | EPWM2A | 4[2] | ||||||
126 | GIOB[0] | 18[24] | ||||||||||
133 | GIOB[1] | 21[8] | ||||||||||
1 | GIOB[3] | 0[0] | ||||||||||
105 | MIBSPI1NCS[0] | 13[24] | MIBSPI1SOMI[1] | 13[25] | ECAP6 | 13[28] | ||||||
130 | MIBSPI1NCS[1] | 20[16] | N2HET1[17] | 20[17] | EQEP1S | 20[20] | ||||||
40 | MIBSPI1NCS[2] | 8[8] | N2HET1[19] | 8[9] | ||||||||
96 | MIBSPI1NENA | 12[16] | N2HET1[23] | 12[17] | ECAP4 | 12[20] | ||||||
53 | MIBSPI3CLK | 33[24] | AWM1_EXT_SEL[1] | 33[25] | EQEP1A | 33[26] | ||||||
55 | MIBSPI3NCS[0] | 9[16] | AD2EVT | 9[17] | GIOB[2] | 9[18] | EQEP1I | 9[19] | ||||
37 | MIBSPI3NCS[1] | 7[8] | N2HET1[25] | 7[9] | ||||||||
4 | MIBSPI3NCS[2] | 0[24] | I2C_SDA | 0[25] | N2HET1[27] | 0[26] | nTZ2 | 0[27] | ||||
3 | MIBSPI3NCS[3] | 0[16] | I2C_SCL | 0[17] | N2HET1[29] | 0[18] | nTZ1 | 0[19] | ||||
54 | MIBSPI3NENA | 9[8] | MIBSPI3NCS[5] | 9[9] | N2HET1[31] | 9[10] | EQEP1B | 9[11] | ||||
52 | MIBSPI3SIMO | 33[16] | AWM1_EXT_SEL[0] | 33[17] | ECAP3 | 33[18] | ||||||
51 | MIBSPI3SOMI | 33[8] | AWM1_EXT_ENA | 33[9] | ECAP2 | 33[10] | ||||||
100 | MIBSPI5CLK | 13[16] | ||||||||||
32 | MIBSPI5NCS[0] | 27[0] | EPWM4A | 27[2] | ||||||||
97 | MIBSPI5NENA | 12[24] | MIBSPI5SOMI[1] | 12[28] | ECAP5 | 12[29] | ||||||
99 | MIBSPI5SIMO[0] | 13[8] | MIBSPI5SOMI[2] | 13[12] | ||||||||
98 | MIBSPI5SOMI[0] | 13[0] | ||||||||||
25 | N2HET1[0] | 5[0] | SPI4CLK | 5[1] | EPWM2B | 5[2] | ||||||
23 | N2HET1[01] | 4[16] | SPI4NENA | 4[17] | 4[19] | N2HET2[8] | 4[20] | EQEP2A | 4[21] | |||
30 | N2HET1[02] | 5[8] | SPI4SIMO | 5[9] | EPWM3A | 5[10] | ||||||
24 | N2HET1[03] | 4[24] | SPI4NCS[0] | 4[25] | 4[27] | N2HET2[10] | 4[28] | EQEP2B | 4[29] | |||
36 | N2HET1[04] | 33[0] | EPWM4B | 33[1] | ||||||||
31 | N2HET1[05] | 5[16] | SPI4SOMI | 5[17] | N2HET2[12] | 5[18] | EPWM3B | 5[19] | ||||
38 | N2HET1[06] | 7[16] | SCIRX | 7[17] | EPWM5A | 7[18] | ||||||
33 | N2HET1[07] | 6[0] | N2HET2[14] | 6[3] | EPWM7B | 6[4] | ||||||
106 | N2HET1[08] | 14[0] | MIBSPI1SIMO[1] | 14[1] | ||||||||
35 | N2HET1[09] | 6[16] | N2HET2[16] | 6[17] | EPWM7A | 6[20] | ||||||
118 | N2HET1[10] | 17[0] | nTZ3 | 17[4] | ||||||||
6 | N2HET1[11] | 1[8] | MIBSPI3NCS[4] | 1[9] | N2HET2[18] | 1[10] | EPWM1SYNCO | 1[13] | ||||
124 | N2HET1[12] | 17[16] | ||||||||||
39 | N2HET1[13] | 8[0] | SCITX | 8[1] | EPWM5B | 8[2] | ||||||
125 | N2HET1[14] | 18[8] | ||||||||||
41 | N2HET1[15] | 8[16] | MIBSPI1NCS[4] | 8[17] | ECAP1 | 8[18] | ||||||
139 | N2HET1[16] | 34[0] | EPWM1SYNCI | 34[1] | EPWM1SYNCO | 34[2] | ||||||
140 | N2HET1[18] | 34[8] | EPWM6A | 34[9] | ||||||||
141 | N2HET1[20] | 34[16] | EPWM6B | 34[17] | ||||||||
15 | N2HET1[22] | 3[8] | ||||||||||
91 | N2HET1[24] | 11[24] | MIBSPI1NCS[5] | 11[25] | ||||||||
92 | N2HET1[26] | 12[0] | ||||||||||
107 | N2HET1[28] | 14[8] | ||||||||||
127 | N2HET1[30] | 19[8] | EQEP2S | 19[11] |
100-PIN PZ |
DEFAULT FUNCTION |
CTRL1 | OPTION 2 | CTRL2 | OPTION 3 | CTRL3 | OPTION 4 | CTRL4 | OPTION 5 | CTRL5 | OPTION 6 | CTRL6 |
---|---|---|---|---|---|---|---|---|---|---|---|---|
2 | GIOA[1]/INT[1] | 1[0] | ||||||||||
5 | GIOA[2]/INT[2] | 2[0] | N2HET2[0] | 2[3] | EQEP2I | 2[4] | ||||||
10 | GIOA[5]/INT[5] | 2[24] | EXTCLKIN1 | 2[25] | EPWM1A | 2[26] | ||||||
12 | GIOA[6]/INT[6] | 3[16] | N2HET2[4] | 3[17] | EPWM1B | 3[18] | ||||||
18 | GIOA[7]/INT[7] | 4[0] | N2HET2[6] | 4[1] | EPWM2A | 4[2] | ||||||
73 | MIBSPI1NCS[0] | 13[24] | MIBSPI1SOMI[1] | 13[25] | ECAP6 | 13[28] | ||||||
93 | MIBSPI1NCS[1] | 20[16] | N2HET1[17] | 20[17] | EQEP1S | 20[20] | ||||||
27 | MIBSPI1NCS[2] | 8[8] | N2HET1[19] | 8[9] | ||||||||
68 | MIBSPI1NENA | 12[16] | N2HET1[23] | 12[17] | ECAP4 | 12[20] | ||||||
36 | MIBSPI3CLK | 33[24] | AWM1_EXT_SEL[1] | 33[25] | EQEP1A | 33[26] | ||||||
38 | MIBSPI3NCS[0] | 9[16] | AD2EVT | 9[17] | GIOB[2] | 9[18] | EQEP1I | 9[19] | ||||
37 | MIBSPI3NENA | 9[8] | MIBSPI3NCS[5] | 9[9] | N2HET1[31] | 9[10] | EQEP1B | 9[11] | ||||
35 | MIBSPI3SIMO[0] | 33[16] | AWM1_EXT_SEL[0] | 33[17] | ECAP3 | 33[18] | ||||||
34 | MIBSPI3SOMI[0] | 33[8] | AWM1_EXT_ENA | 33[9] | ECAP2 | 33[10] | ||||||
19 | N2HET1[0] | 5[0] | SPI4CLK | 5[1] | EPWM2B | 5[2] | ||||||
22 | N2HET1[02] | 5[8] | SPI4SIMO | 5[9] | EPWM3A | 5[10] | ||||||
25 | N2HET1[04] | 33[0] | EPWM4B | 33[1] | ||||||||
26 | N2HET1[06] | 7[16] | SCIRX | 7[17] | EPWM5A | 7[18] | ||||||
74 | N2HET1[08] | 14[0] | MIBSPI1SIMO[1] | 14[1] | ||||||||
83 | N2HET1[10] | 17[0] | nTZ3 | 17[4] | ||||||||
97 | N2HET1[16] | 34[0] | EPWM1SYNCI | 34[1] | EPWM1SYNCO | 34[2] | ||||||
98 | N2HET1[18] | 34[8] | EPWM6A | 34[9] | ||||||||
64 | N2HET1[24] | 11[24] | MIBSPI1NCS[5] | 11[25] |
Some signals are connected to more than one terminal, the inputs for these signals can come from any of the terminals. A multiplexor is implemented to let the application choose the terminal that will be used, providing the input signal is from among the available options.
SIGNAL NAME |
DEDICATED INPUTS | MULTIPLEXED INPUTS | INPUT MULTIPLEXOR CONTROL |
INPUT PATH SELECTED | ||||
---|---|---|---|---|---|---|---|---|
144 PGE | 100 PZ | 144 PGE | 100 PZ | BIT1 | BIT2 | DEDICATED, IF | MUXED, IF | |
GIOB[2] | 142 | – | 55 | 38 | PINMUX29[16] | PINMUX29[16] | BIT1 = 0(3) | BIT1 = 1(3) |
N2HET1[17] | – | – | 130 | 93 | PINMUX20[17] | PINMUX24[16] | not(BIT1) or (BIT1 and BIT2) = 1 | BIT1 and not(BIT2) = 1 |
N2HET1[19] | – | – | 40 | 27 | PINMUX8[9] | PINMUX24[24] | not(BIT1) or (BIT1 and BIT2) = 1 | BIT1 and not(BIT2) = 1 |
N2HET1[21] | – | – | – | – | PINMUX9[25] | PINMUX25[0] | not(BIT1) or (BIT1 and BIT2) = 1 | BIT1 and not(BIT2) = 1 |
N2HET1[23] | – | – | 96 | 68 | PINMUX12[17] | PINMUX25[8] | not(BIT1) or (BIT1 and BIT2) = 1 | BIT1 and not(BIT2) = 1 |
N2HET1[25] | – | – | 37 | – | PINMUX7[9] | PINMUX25[16] | not(BIT1) or (BIT1 and BIT2) = 1 | BIT1 and not(BIT2) = 1 |
N2HET1[27] | – | – | 4 | – | PINMUX0[26] | PINMUX25[24] | not(BIT1) or (BIT1 and BIT2) = 1 | BIT1 and not(BIT2) = 1 |
N2HET1[29] | – | – | 3 | – | PINMUX0[18] | PINMUX26[0] | not(BIT1) or (BIT1 and BIT2) = 1 | BIT1 and not(BIT2) = 1 |
N2HET1[31] | – | – | 54 | 37 | PINMUX9[10] | PINMUX26[8] | not(BIT1) or (BIT1 and BIT2) = 1 | BIT1 and not(BIT2) = 1 |
Low-level Output Current, IOL for VI = VOLmax
or High-level Output Current, IOH for VI = VOHmin |
Signals |
---|---|
8mA |
MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3], MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3], TMS, TDI, TDO, RTCK, SPI4CLK, SPI4SIMO, SPI4SOMI, SPI4NCS[0], SPI4NENA, nERROR, N2HET2[1], N2HET2[3], N2HET2[5], N2HET2[7], N2HET2[9], N2HET2[11], N2HET2[13], N2HET2[15] ECAP1, ECAP4, ECAP5, ECAP6 EQEP1I, EQEP1S, EQEP2I, EQEP2S EPWM1A, EPWM1B, EPWM1SYNCO, EPW2A, EPWM2B, EPWM3A, EPWM3B, EPWM4A, EPWM4B, EPWM5A, EPWM5B, EPWM6A, EPWM6B, EPWM7A, EPWM7B |
4mA |
TEST, MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK, ECAP2, ECAP3 nRST |
2mA zero-dominant |
AD1EVT, CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX, GIOA[0-7], GIOB[0-7], LINRX, LINTX, MIBSPI1NCS[0], MIBSPI1NCS[1-3], MIBSPI1NENA, MIBSPI3NCS[0-3], MIBSPI3NENA, MIBSPI5NCS[0-3], MIBSPI5NENA, N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[6], N2HET2[8], N2HET2[10], N2HET2[12], N2HET2[14], N2HET2[16], N2HET2[18], |
selectable 8mA / 2mA |
ECLK, SPI2CLK, SPI2SIMO, SPI2SOMI The default output buffer drive strength is 8mA for these signals. |
SIGNAL | CONTROL BIT | ADDRESS | 8mA (DEFAULT) | 2mA |
---|---|---|---|---|
ECLK | SYSPC10[0] | 0xFFFF FF78 | 0 | 1 |
SPI2CLK | SPI2PC9[9] | 0xFFF7 F668 | 0 | 1 |
SPI2SIMO | SPI2PC9[10] | 0xFFF7 F668 | 0 | 1 |
SPI2SOMI | SPI2PC9[11](1) | 0xFFF7 F668 | 0 | 1 |