SPNS141G August   2010  – October 2018 TMS570LS10106 , TMS570LS10116 , TMS570LS10206 , TMS570LS20206 , TMS570LS20216

PRODUCTION DATA.  

  1. 1 TMS570LS Series 16/32-BIT RISC Flash Microcontroller
    1. 1.1 Features
    2. 1.2 Description
    3. 1.3 Functional Block Diagram
  2. 2 Device Overview
    1. 2.1 Terms and Acronyms
    2. 2.2 Device Characteristics
    3. 2.3 Memory
      1. 2.3.1 Memory Map
      2. 2.3.2 Flash Memory
      3. 2.3.3 System Modules Assignment
      4. 2.3.4 Peripheral Selects
      5. 2.3.5 Memory Auto-Initialization
      6. 2.3.6 PBIST RAM Self Test
    4. 2.4 Pin Assignments
      1. 2.4.1 PGE QFP Package Pinout (144 pin)
      2. 2.4.2 ZWT BGA Package Pinout (337 ball)
    5. 2.5 Terminal Functions
    6. 2.6 Device Support
      1. 2.6.1 Device and Development-Support Tool Nomenclature
  3. 3 Reset / Abort Sources
    1. 3.1 Reset / Abort Sources
  4. 4 Peripherals
    1. 4.1  Error Signaling Module (ESM)
    2. 4.2  Direct Memory Access (DMA)
    3. 4.3  High End Timer Transfer Unit (HET-TU)
    4. 4.4  Vectored Interrupt Manager (VIM)
    5. 4.5  MIBADC Event Trigger Sources
    6. 4.6  MIBSPI
      1. 4.6.1 MIBSPI Event Trigger Sources
      2. 4.6.2 MIBSPIP5/DMM Pin Multiplexing
    7. 4.7  ETM
    8. 4.8  Debug Scan Chains
      1. 4.8.1 JTAG
    9. 4.9  CCM
      1. 4.9.1 Dual Core Implementation
      2. 4.9.2 CCM-R4
    10. 4.10 LPM
    11. 4.11 Voltage Monitor
    12. 4.12 CRC
    13. 4.13 System Module Access
    14. 4.14 Debug ROM
    15. 4.15 CPU Self Test Controller: STC / LBIST
  5. 5 Device Registers
    1. 5.1 Device Identification Code Register
      1. Table 5-1 Device ID Bit Allocation Register Field Descriptions
    2. 5.2 Die-ID Registers
    3. 5.3 PLL Registers
  6. 6 Device Electrical Specifications
    1. 7 Operating Conditions
      1. 7.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)
      2. 7.2 Device Recommended Operating Conditions
      3. 7.3 Electrical Characteristics Over Operating Free-Air Temperature Range
  7. 8 Peripheral and Electrical Specifications
    1. 8.1  Clocks
      1. 8.1.1 PLL And Clock Specifications
      2. 8.1.2 External Reference Resonator/Crystal Oscillator Clock Option
      3. 8.1.3 Validated FMPLL Setting
      4. 8.1.4 LPO And Clock Detection
      5. 8.1.5 Switching Characteristics Over Recommended Operating Conditions For Clocks
        1. 8.1.5.1 Timing - Wait States
    2. 8.2  ECLK Specification
      1. 8.2.1 Switching Characteristics Over Recommended Operating Conditions For External Clocks
    3. 8.3  RST And PORRST Timings
      1. 8.3.1 Timing Requirements For PORRST
      2. 8.3.2 Switching Characteristics Over Recommended Operating Conditions For RST
      3. 8.3.3 IO Status During PORRST
    4. 8.4  TEST Pin Timing
    5. 8.5  DAP - JTAG Scan Interface Timing
      1. 8.5.1 JTAG clock specification 12-MHz and 50-pF load on TDO output
    6. 8.6  Output Timings
      1. 8.6.1 Switching Characteristics For Output Timings Versus Load Capacitance (CL)
    7. 8.7  Input Timings
      1. 8.7.1 Timing Requirements For Input Timings
    8. 8.8  Flash Timings
    9. 8.9  SPI Master Mode Timing Parameters
      1. 8.9.1 SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
      2. 8.9.2 SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
    10. 8.10 SPI Slave Mode Timing Parameters
      1. 8.10.1 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO = input, and SPISOMI = output)
      2. 8.10.2 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output)
    11. 8.11 CAN Controller Mode Timings
      1. 8.11.1 Dynamic Characteristics For The CANnTX And CANnRX Pins
    12. 8.12 SCI/LIN Mode Timings
    13. 8.13 FlexRay Controller Mode Timings
      1. 8.13.1 Jitter Timing
    14. 8.14 EMIF Timings
      1. 8.14.1 Read Timing (Asynchronous RAM)
      2. 8.14.2 Write Timing (Asynchronous RAM)
    15. 8.15 ETM Timings
      1. 8.15.1 ETMTRACECLK Timing
      2. 8.15.2 ETMDATA Timing
    16. 8.16 RTP Timings
      1. 8.16.1 RTPCLK Timing
      2. 8.16.2 RTPDATA Timing
      3. 8.16.3 RTPENABLE Timing
    17. 8.17 DMM Timings
      1. 8.17.1 DMMCLK Timing
      2. 8.17.2 DMMDATA Timing
      3. 8.17.3 DMMENA Timing
    18. 8.18 MibADC
      1. 8.18.1 MibADC
      2. 8.18.2 MibADC Recommended Operating Conditions
      3. 8.18.3 Operating Characteristics Over Full Ranges Of Recommended Operating Conditions
      4. 8.18.4 MibADC Input Model
      5. 8.18.5 MibADC Timings
      6. 8.18.6 MibADC Nonlinearity Error
      7. 8.18.7 MibADC Total Error
  8. 9 Revision History
  9. 10Mechanical Packaging and Orderable Information
    1. 10.1 Thermal Data
      1. 10.1.1 PGE (S-PQFP-G144) plastic Quad Flat Pack
      2. 10.1.2 ZWT (S-PBGA-N337) Plastic ball grid array
    2. 10.2 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZWT|337
  • PGE|144
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3 Electrical Characteristics Over Operating Free-Air Temperature Range(1)

Parameter Test Conditions MIN TYP MAX Unit
Vhys Input hysteresis 0.15 V
VIL Low-level input voltage All inputs(2) -0.3 0.8 V
VIH High-level input voltage All inputs 2 VCCIO + 0.3 V
VOL Low-level output voltage IOL = IOL MAX 0.2 VCCIO V
IOL = 50 µA 0.2
VOH High-level output voltage IOH = IOH MAX 0.8 VCCIO V
IOH = 50 µA VCCIO - 0.2
VILoscin Low-level input voltage OSCIN -0.3 0.2 VCC V
VIHoscin High-level input voltage OSCIN 0.8 VCC VCC + 0.3 V
VMON Voltage monitoring threshold VCC low 1.0 1.2 1.35 V
VCC high 1.7 2 2.38
VCCIO low 2.0 2.4 3.0
IIC Input clamp current VI < VSSIO - 0.3 or VI > VCCIO + 0.3 -2 2 mA
II Input current (I/O pins) IIL Pulldown VI = VSS -1 1 µA
IIH Pulldown 20 uA VI = VCCIO 5 40
IIH Pulldown 100 uA VI = VCCIO 40 195
IIL Pullup 20 uA VI = VSS -40 -5
IIL Pullup 100 uA VI = VSS -195 -40
IIH Pullup VI = VCCIO -1 1
All other pins No pullup or pulldown -1 1
IOL Low-level output current TDO VOL = VOL MAX 8 mA
TDI
TMS
RTCK
ECLK
FRAYTX1
FRAYTXEN1
FRAYTX2
FRAYTXEN2
DMMENA
ETMTRACECTL
ETMTRACECLKOUT
ETMDATA[31:0]
RTPSYNC
RTPCLK
RTPDATA[15:0]
EMIFWE
EMIFOE
EMIFCS[3:0]
EMIFDATA[15:0]
EMIFADD[21:0]
EMIFBADD[1:0]
EMIFDQM[1:0]
ERROR
IOL Low-level output current RST VOL = VOL MAX 4 mA
MIBSPI1CLK
MIBSPI1SIMO
MIBSPI1SOMI
MIBSPI3CLK
MIBSPI3SIMO
MIBSPI3SOMI
MIBSPI5CLK
MIBSPI5SIMO[3:0]
MIBSPI5SOMI[3:0]
DMMDATA[15:8]
DMMDATA[4]
All other output pins 2
IOH High-level output current TDO VOH = VOH MIN -8 mA
TDI
TMS
RTCK
ECLK
FRAYRX1
FRAYTX1
FRAYTXEN1
FRAYRX2
FRAYTX2
FRAYTXEN2
ETMTRACECTL
ETMTRACECLKOUT
ETMDATA[31:0]
RTPSYNC
RTPCLK
RTPDATA[15:0]
DMMENA
EMIFWE
EMIFOE
EMIFCS[3:0]
EMIFDATA[15:0]
EMIFADD[21:0]
EMIFBADD[1:0]
EMIFDQM[1:0]
ERROR
IOH High-level output current RST VOH = VOH MIN -4 mA
MIBSPI1CLK
MIBSPI1SIMO
MIBSPI1SOMI
MIBSPI3CLK
MIBSPI3SIMO
MIBSPI3SOMI
MIBSPI5CLK
MIBSPI5SIMO[3:0]
MIBSPI5SOMI[3:0]
DMMDATA[15:8]
DMMDATA[4]
All other output pins -2
ICC(3) VCC Digital supply current (Operating mode) All packages HCLK = 100MHz, VCLK = 100MHz 350 mA
HCLK = 140MHz, VCLK= 70MHz 390 mA
BGA packages HCLK = 160MHz, VCLK = 80MHz 430 mA
VCC Digital supply current (CPU selftest mode: LBIST)(4)(5) All packages STCCLK = 46.666MHz Peak 510 mA
STCCLK = 50.0MHz Peak 540 mA
BGA packages STCCLK = 53.333MHz Peak 580 mA
VCC Digital supply current (Mem selftest mode: PBIST)(4)(6) All packages HCLK=80MHz, VCLK=40MHz Peak 340 mA
HCLK=100MHz, VLCK=100MHz Peak 430 mA
VCC Digital supply current (doze mode) OSCIN = 6 MHz, VCC = 1.65 V(7) 35 mA
VCC Digital supply current (snooze mode) All frequencies, VCC = 1.65 V(7) 30 mA
VCC Digital supply current (sleep mode) All frequencies, VCC = 1.65 V(7) 25 mA
ICCIO VCCIO Digital supply current (operating mode) No DC load, VCCIO = 3.6 V(8) 15 mA
VCCIO Digital supply current (doze mode) No DC load, VCCIO = 3.6 V(8) 700 µA
VCCIO Digital supply current (snooze mode) No DC load, VCCIO = 3.6 V(8) 100 µA
VCCIO Digital supply current (sleep mode) No DC load, VCCIO = 3.6 V(8) 100 µA
ICCAD VCCAD supply current (operating mode) All frequencies, VCCAD = 3.6 V 30 mA
VCCAD supply current (doze mode) All frequencies, VCCAD = 3.6 V(7) 200 µA
VCCAD supply current (snooze mode) All frequencies, VCCAD = 3.6 V(7) 200 µA
VCCAD supply current (sleep mode) All frequencies, VCCAD = 3.6 V(7) 200 µA
ICCP VCCP pump supply current VCCP = 3.6 V read operation 25 mA
VCCP = 3.6 V program(9) 90 mA
VCCP = 3.6 V erase 90 mA
VCCP = 3.6 V doze mode(7) 5 µA
VCCP = 3.6 V snooze mode(7) 5 µA
VCCP = 3.6 V sleep mode(7) 5 µA
CI Input capacitance(10) 2 pF
CO Output capacitance 3 pF
(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.
(2) This does not apply to PORRST pin.
(3) Typical values are at Vcc=1.5V and maximum values are at Vcc=1.65V
(4) The peak current is measured on the TI EVM board with two 10µF and thirteen 100nF capacitors on VCC domain. Running at a lower frequency consumes less current.
(5) LBIST currents specified are for execution of LBIST with a certain STC clock. Lower current consumption can be achieved by configuring a slower STC Clock frequency. The current peak duration can last for the duration of 1 LBIST test interval.
(6) PBIST currents specified are for execution of PBIST on all RAMs(Group 1- 14) and all the algrithms. Lower current consumption can be achieved by configuring a slower HCLK frequency. Different algorithms consume different current. For more information, please refer to Basic PBIST Configuration and influence on current consumption(SPNA128).
(7) For Flash banks/pumps in sleep mode.
(8) I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO - 0.2 V.
(9) This assumes reading from one bank while programming a different bank.
(10) The maximum input capacitance CI of the FlexRay RX pin(s) is 10pF.