SPNS141G August 2010 – October 2018 TMS570LS10106 , TMS570LS10116 , TMS570LS10206 , TMS570LS20206 , TMS570LS20216
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
NO. | MIN | MAX | Unit | ||
---|---|---|---|---|---|
1 | tc(SPC)M | Cycle time, SPICLK (4) | 50 | 256tc(VCLK) | ns |
2(5) | tw(SPCH)M | Pulse duration, SPICLK high (clock polarity = 0) | 0.5tc(SPC)M – 3 – tr | 0.5tc(SPC)M + 5 | ns |
tw(SPCL)M | Pulse duration, SPICLK low (clock polarity = 1) | 0.5tc(SPC)M – 3 – tf | 0.5tc(SPC)M + 5 | ||
3(5) | tw(SPCL)M | Pulse duration, SPICLK low (clock polarity = 0) | 0.5tc(SPC)M – 3 – tf | 0.5tc(SPC)M + 5 | ns |
tw(SPCH)M | Pulse duration, SPICLK high (clock polarity = 1) | 0.5tc(SPC)M – 3 – tr | 0.5tc(SPC)M + 5 | ||
4(5) | td(SIMO-SPCL)M | Delay time, SPISIMO valid before SPICLK low (clock polarity = 0) | 0.5tc(SPC)M – 10 | ns | |
td(SIMO-SPCH)M | Delay time, SPISIMO valid before SPICLK high (clock polarity = 1) | 0.5tc(SPC)M – 10 | |||
5(5) | tv(SPCL-SIMO)M | Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) | 0.5tc(SPC)M – tf(SPC) -7 | ns | |
tv(SPCH-SIMO)M | Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) | 0.5tc(SPC)M – tr(SPC) -7 | |||
6(5) | tsu(SOMI-SPCL)M | Setup time, SPISOMI before SPICLK low (clock polarity = 0) | tf(SPC) | ns | |
tsu(SOMI-SPCH)M | Setup time, SPISOMI before SPICLK high (clock polarity = 1) | tr(SPC) + 4 | |||
7(5) | th(SPCL-SOMI)M | Hold time, SPISOMI data valid after SPICLK low (clock polarity = 0) | 10 | ns | |
th(SPCH-SOMI)M | Hold time, SPISOMI data valid after SPICLK high (clock polarity = 1) | 10 | |||
8(6) | tC2TDELAY | Setup time CS active until SPICLK high, assumes that SPInENA is low at tSPIENA (clock polarity = 0) | (C2TDELAY+CSHOLD+2)*tc(VCLK) - tf(SPICS) +
tr(SPC)- 9 |
(C2TDELAY+CSHOLD+2)*tc(VCLK) - tf(SPICS) +
tr(SPC)+ 5 |
ns |
Setup time CS active until SPICLK low, assumes that SPInENA is low at tSPIENA (clock polarity = 1) | (C2TDELAY+CSHOLD+2)*tc(VCLK) - tf(SPICS) +
tf(SPC) - 9 |
(C2TDELAY+CSHOLD+2)*tc(VCLK) - tf(SPICS) +
tf(SPC) + 5 |
ns | ||
9(6) | tT2CDELAY | Hold time SPICLK low until CS inactive (clock polarity = 0) | 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) -
tf(SPC) + tr(SPICS) - 5 |
0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) -
tf(SPC) + tr(SPICS) + 10 |
ns |
Hold time SPICLK high until CS inactive (clock polarity = 1) | 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) -
tr(SPC) + tr(SPICS) - 5 |
0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) -
tr(SPC) + tr(SPICS) + 10 |
ns | ||
10 | tSPIENA | SPIENAn Sample point | C2TDELAY * tc(VCLK) - tf(SPICS) - 20 | C2TDELAY * tc(VCLK) | ns |
11 | tSPIENAW | SPIENAn Sample point from write to buffer | (C2TDELAY+2)*tc(VCLK) | ns |