SPNS165B April 2012 – May 2015 TMS570LS2124 , TMS570LS2134 , TMS570LS3134
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The TMS570LS31x4/21x4 device is a high-performance automotive-grade microcontroller family for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.
The TMS570LS31x4/21x4 device integrates the ARM Cortex-R4F Floating-Point CPU. The CPU offers an efficient 1.66 DMIPS/MHz, and has configurations that can run up to 180 MHz, providing up to 298 DMIPS. The device supports the word-invariant big-endian [BE32] format.
The TMS570LS3134 device has 3MB of integrated flash and 256KB of data RAM. The TMS570LS2134 device has 2MB of integrated flash and 256KB of data RAM. The TMS570LS2124 device has 2MB of integrated flash and 192KB of data RAM. Both the flash and RAM have single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word modes.
The TMS570LS31x4/21x4 device features peripherals for real-time control-based applications, including two Next Generation High-End Timer (N2HET) timing coprocessors and two 12-bit Analog-to-Digital Converters (ADCs) supporting up to 24 inputs.
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.
The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are three separate groupings. Each sequence can be converted once when triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster conversion time is desired.
The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three DCANs, and one I2C module. The SPIs provide a convenient method of serial high-speed communication between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format.
The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication or multiplexed wiring.
The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports speeds of 100 and 400 Kbps.
The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. There are two FMPLL modules on this device. These modules, when enabled, provide two of the seven possible clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the available clock sources and the device clock domains.
The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous external clock on the ECLK pin (or ball). The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.
The DMA controller has 16 channels, 32 peripheral requests, and parity protection on its memory. An MPU is built into the DMA to limit the DMA to prescribed areas of memory and to protect the rest of the memory system from any malfunction of the DMA.
The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt is generated or the external ERROR pin is toggled when a fault is detected. The ERROR pin can be monitored externally as an indicator of a fault condition in the microcontroller.
The External Memory Interface (EMIF) provides off-chip expansion capability with the ability to interface to synchronous DRAM (SDRAM) devices, asynchronous memories, peripherals, or FPGA devices.
Several interfaces are implemented to enhance the debugging capabilities of application code. In addition to the built-in ARM Cortex-R4F CoreSight debug features, an External Trace Macrocell (ETM) provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM and peripheral accesses by the CPU or any other master. A Data Modification Module (DMM) gives the ability to write external data into the device memory. Both the RTP and DMM have no or only minimum impact on the program execution time of the application code. A Parameter Overlay Module (POM) can reroute flash accesses to internal memory or to the EMIF. This rerouting allows the dynamic calibration against production code of parameters and tables without rebuilding the code to explicitly access RAM or halting the processor to reprogram the data flash.
With integrated safety features and a wide choice of communication and control peripherals, the TMS570LS31x4/21x4 device is an ideal solution for high-performance real-time control applications with safety-critical requirements.
PART NUMBER | PACKAGE | BODY SIZE |
---|---|---|
TMS570LS2124ZWT | NFBGA (337) | 16.0 mm × 16.0 mm |
TMS570LS2124PGE | LQFP (144) | 20.0 mm × 20.0 mm |
TMS570LS2134ZWT | NFBGA (337) | 16.0 mm × 16.0 mm |
TMS570LS2134PGE | LQFP (144) | 20.0 mm × 20.0 mm |
TMS570LS3134ZWT | NFBGA (337) | 16.0 mm × 16.0 mm |
TMS570LS3134PGE | LQFP (144) | 20.0 mm × 20.0 mm |
This data manual revision history highlights the technical changes made to the SPNS165A device-specific data manual to make it an SPNS165B revision.
Scope: Applicable updates to the Hercules™ TMS570 MCU device family, specifically relating to the TMS570LS31x4/21x4 devices, which are now in the production data (PD) stage of development have been incorporated.
Changes from October 1, 2013 to May 15, 2015 (from A Revision (September 2013) to B Revision)
Table 3-1 lists the features of the TMS570LS2124/LS2134/LS3134 devices.
FEATURES | DEVICES | ||||||||
---|---|---|---|---|---|---|---|---|---|
Generic Part Number | TMS570LC4357ZWT(1) | TMS570LS3137ZWT(1) | TMS570LS3134ZWT | TMS570LS3134PGE | TMS570LS2134ZWT | TMS570LS2134PGE | TMS570LS2124ZWT | TMS570LS2124PGE | TMS570LS1227ZWT(1) |
Package | 337 BGA | 337 BGA | 337 BGA | 144 QFP | 337 BGA | 144 QFP | 337 BGA | 144 QFP | 337 BGA |
CPU | ARM Cortex-R5F | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4F |
Frequency (MHz) | 300 | 180 | 180 | 160 | 180 | 160 | 180 | 160 | 180 |
Cache (KB) | 32 I 32 D |
– | – | – | – | – | – | – | – |
Flash (KB) | 4096 | 3072 | 3072 | 3072 | 2048 | 2048 | 2048 | 2048 | 1280 |
RAM (KB) | 512 | 256 | 256 | 256 | 256 | 256 | 192 | 192 | 192 |
Data Flash [EEPROM] (KB) | 128 | 64 | 64 | 64 | 64 | 64 | 64 | 64 | 64 |
EMAC | 10/100 | 10/100 | – | – | – | – | – | – | 10/100 |
FlexRay | 2-ch | 2-ch | – | – | – | – | – | – | 2-ch |
CAN | 4 | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
MibADC 12-bit (Ch) |
2 (41ch) | 2 (24ch) | 2 (24ch) | 2 (24ch) | 2 (24ch) | 2 (24ch) | 2 (24ch) | 2 (24ch) | 2 (24ch) |
N2HET (Ch) | 2 (64) | 2 (44) | 2 (44) | 2 (40) | 2 (44) | 2 (40) | 2 (44) | 2 (40) | 2 (44) |
ePWM Channels | 14 | – | – | – | – | – | – | – | 14 |
eCAP Channels | 6 | – | – | – | – | – | – | – | 6 |
eQEP Channels | 2 | – | – | – | – | – | – | – | 2 |
MibSPI (CS) | 5 (4 x 6 + 2) | 3 (6 + 6 + 4) | 3 (6 + 6 + 4) | 3 (5 + 6 + 1) | 3 (6 + 6 + 4) | 3 (5 + 6 + 1) | 3 (6 + 6 + 4) | 3 (5 + 6 + 1) | 3 (6 + 6 + 4) |
SPI (CS) | – | 2 (2 + 1) | 2 (2 + 1) | 1 (1) | 2 (2 + 1) | 1 (1) | 2 (2 + 1) | 1 (1) | 2 (2 + 1) |
SCI (LIN) | 4 (2 with LIN) | 2 (1 with LIN) | 2 (1 with LIN) | 2 (1 with LIN) | 2 (1 with LIN) | 2 (1 with LIN) | 2 (1 with LIN) | 2 (1 with LIN) | 2 (1 with LIN) |
I2C | 2 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
GPIO (INT)(4) | 168 (with 16 interrupt capable) | 144 (with 16 interrupt capable) | 144 (with 16 interrupt capable) | 64 (with 10 interrupt capable) | 144 (with 16 interrupt capable) | 64 (with 10 interrupt capable) | 144 (with 16 interrupt capable) | 64 (with 10 interrupt capable) | 101 (with 16 interrupt capable) |
EMIF | 16-bit data | 16-bit data | 16-bit data | – | 16-bit data | – | 16-bit data | – | 16-bit data |
ETM (Trace) | 32-bit | 32-bit | 32-bit | – | 32-bit | – | 32-bit | – | – |
RTP/DMM | 16/16 | 16/16 | 16/16 | – | 16/16 | – | 16/16 | – | – |
Operating Temperature |
–40ºC to 125ºC | –40ºC to 125ºC | –40ºC to 125ºC | –40ºC to 125ºC | –40ºC to 125ºC | –40ºC to 125ºC | –40ºC to 125ºC | –40ºC to 125ºC | –40ºC to 125ºC |
Core Supply (V) | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V |
I/O Supply (V) | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V |
Section 4.2.1 and Section 4.2.2identify the external signal names, the associated pin or ball numbers along with the mechanical package designator, the pin or ball type (Input, Output, I/O, Power, or Ground), whether the pin or ball has any internal pullup or pulldown, whether the pin or ball can be configured as a GPIO, and a functional pin or ball description. The first signal name listed is the primary function for that terminal. The signal name in bold is the function being described. For information on how to select between different multiplexed functions, see the TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (SPNU499) .
NOTE
In the Terminal Functions table below, the "Reset Pull State" is the state of the pull applied to the terminal while nPORRST is low and immediately after nPORRST goes High. The default pull direction may change when software configures the pin for an alternate function. The "Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given terminal by the IOMM control registers.
All I/O signals except nRST are configured as inputs while nPORRST is low and immediately after nPORRST goes High. While nPORRST is low, the input buffers are disabled, and the output buffers are disabled with the default pulls enabled.
All output-only signals have the output buffer disabled and the default pull enabled while nPORRST is low, and are configured as outputs with the pulls disabled immediately after nPORRST goes High.
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
ADREFHI(1) | 66 | Input | N/A | None | ADC high reference supply |
ADREFLO(1) | 67 | Input | ADC low reference supply | ||
VCCAD(1) | 69 | Power | Operating supply for ADC | ||
VSSAD(1) | 68 | Ground | |||
AD1EVT | 86 | I/O | Pulldown | Programmable, 20 µA | ADC1 event trigger input, or GPIO |
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS | 55 | I/O | Pullup | Programmable, 20 µA | ADC2 event trigger input, or GPIO |
AD1IN[0] | 60 | Input | N/A | None | ADC1 analog input |
AD1IN[1] | 71 | ||||
AD1IN[2] | 73 | ||||
AD1IN[3] | 74 | ||||
AD1IN[4] | 76 | ||||
AD1IN[5] | 78 | ||||
AD1IN[6] | 80 | ||||
AD1IN[7] | 61 | ||||
AD1IN[8] / AD2IN[8] | 83 | Input | N/A | None | ADC1/ADC2 shared analog inputs |
AD1IN[9] / AD2IN[9] | 70 | ||||
AD1IN[10] / AD2IN[10] | 72 | ||||
AD1IN[11] / AD2IN[11] | 75 | ||||
AD1IN[12] / AD2IN[12] | 77 | ||||
AD1IN[13] / AD2IN[13] | 79 | ||||
AD1IN[14] / AD2IN[14] | 82 | ||||
AD1IN[15] / AD2IN[15] | 85 | ||||
AD1IN[16] / AD2IN[0] | 58 | ||||
AD1IN[17] / AD2IN[1] | 59 | ||||
AD1IN[18] / AD2IN[2] | 62 | ||||
AD1IN[19] / AD2IN[3] | 63 | ||||
AD1IN[20] / AD2IN[4] | 64 | ||||
AD1IN[21] / AD2IN[5] | 65 | ||||
AD1IN[22] / AD2IN[6] | 81 | ||||
AD1IN[23] / AD2IN[7] | 84 |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
GIOA[0] | 2 | I/O | Pulldown | Programmable, 20 µA | General-purpose I/O. All GPIO terminals are capable of generating interrupts to the CPU on rising / falling / both edges. |
GIOA[1] | 5 | ||||
GIOA[2]/N2HET2[0] | 9 | ||||
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS | 14 | ||||
GIOA[6]/N2HET2[4] | 16 | ||||
GIOA[7]/N2HET2[6] | 22 | ||||
GIOB[0] | 126 | ||||
GIOB[1] | 133 | ||||
GIOB[2]/N2HET1_PIN_nDIS | 142 | ||||
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS | 55(1) | Pullup | |||
GIOB[3] | 1 | Pulldown |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
CAN1RX | 90 | I/O | Pullup | Programmable, 20 µA | CAN1 receive, or GPIO |
CAN1TX | 89 | CAN1 transmit, or GPIO | |||
CAN2RX | 129 | CAN2 receive, or GPIO | |||
CAN2TX | 128 | CAN2 transmit, or GPIO | |||
CAN3RX | 12 | CAN3 receive, or GPIO | |||
CAN3TX | 13 | CAN3 transmit, or GPIO |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
LINRX | 131 | I/O | Pullup | Programmable, 20 µA | LIN receive, or GPIO |
LINTX | 132 | LIN transmit, or GPIO |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
N2HET1[6]/SCIRX | 38 | I/O | Pulldown | Programmable, 20 µA | SCI receive, or GPIO |
N2HET1[13]/SCITX | 39 | SCI transmit, or GPIO |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] | 4 | I/O | Pullup | Programmable, 20 µA | I2C serial data, or GPIO |
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] | 3 | I2C serial clock, or GPIO |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
N2HET1[0]/SPI4CLK | 25 | I/O | Pulldown | Programmable, 20 µA | SPI4 clock, or GPIO |
N2HET1[3]/SPI4NCS[0]/N2HET2[10] | 24 | SPI4 chip select, or GPIO | |||
N2HET1[1]/SPI4NENA/N2HET2[8] | 23 | SPI4 enable, or GPIO | |||
N2HET1[2]/SPI4SIMO[0] | 30 | SPI4 slave-input master-output, or GPIO | |||
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] | 31 | SPI4 slave-output master-input, or GPIO |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
MIBSPI1CLK | 95 | I/O | Pullup | Programmable, 20 µA | MibSPI1 clock, or GPIO |
MIBSPI1NCS[0]/MIBSPI1SOMI[1] | 105 | MibSPI1 chip select, or GPIO | |||
MIBSPI1NCS[1]/N2HET1[17] | 130 | ||||
MIBSPI1NCS[2]/N2HET1[19] | 40 | ||||
N2HET1[15]/MIBSPI1NCS[4] | 41 | Pulldown | Programmable, 20 µA | MibSPI1 chip select, or GPIO | |
N2HET1[24]/MIBSPI1NCS[5] | 91 | ||||
MIBSPI1NENA/N2HET1[23] | 96 | Pullup | Programmable, 20 µA | MibSPI1 enable, or GPIO | |
MIBSPI1SIMO[0] | 93 | MibSPI1 slave-in master-out, or GPIO | |||
N2HET1[8]/MIBSPI1SIMO[1] | 106 | Pulldown | Programmable, 20 µA | MibSPI1 slave-in master-out, or GPIO | |
MIBSPI1SOMI[0] | 94 | Pullup | Programmable, 20 µA | MibSPI1 slave-out master-in, or GPIO | |
MIBSPI1NCS[0]/MIBSPI1SOMI[1] | 105 | ||||
MIBSPI3CLK | 53 | I/O | Pullup | Programmable, 20 µA | MibSPI3 clock, or GPIO |
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS | 55 | MibSPI3 chip select, or GPIO | |||
MIBSPI3NCS[1]/N2HET1[25]/MDCLK | 37 | ||||
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] | 4 | ||||
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] | 3 | ||||
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] | 6 | Pulldown | Programmable, 20 µA | MibSPI3 chip select, or GPIO | |
MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31] | 54 | Pullup | Programmable, 20 µA | MibSPI3 chip select, or GPIO | |
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] | 54 | MibSPI3 enable, or GPIO | |||
MIBSPI3SIMO[0] | 52 | MibSPI3 slave-in master-out, or GPIO | |||
MIBSPI3SOMI[0] | 51 | MibSPI3 slave-out master-in, or GPIO | |||
MIBSPI5CLK | 100 | I/O | Pullup | Programmable, 20 µA | MibSPI5 clock, or GPIO |
MIBSPI5NCS[0] | 32 | MibSPI5 chip select, or GPIO | |||
MIBSPI5NENA | 97 | MibSPI5 enable, or GPIO | |||
MIBSPI5SIMO[0] | 99 | MibSPI5 slave-in master-out, or GPIO | |||
MIBSPI5SOMI[0] | 98 | MibSPI5 slave-out master-in, or GPIO |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
nPORRST | 46 | Input | Pulldown | Fixed 100-µA Pulldown |
Power-on reset, cold reset External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter. See Section 6.8. |
nRST | 116 | I/O | Pullup | Fixed 100-µA Pullup |
System reset, warm reset, bidirectional. The internal circuitry indicates any reset condition by driving nRST low. The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal. This terminal has a glitch filter. See Section 6.8. |
nERROR | 117 | I/O | Pulldown | Fixed 20-µA Pulldown |
ESM Error Signal Indicates error of high severity. See Section 6.18. |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
OSCIN | 18 | Input | N/A | None | From external crystal/resonator, or external clock input |
KELVIN_GND | 19 | Input | Kelvin ground for oscillator | ||
OSCOUT | 20 | Output | To external crystal/resonator | ||
ECLK | 119 | I/O | Pulldown | Programmable, 20 µA | External prescaled clock output, or GIO. |
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS | 14 | Input | Pulldown | 20 µA | External clock input #1 |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
VCCP | 134 | 3.3-V Power | N/A | None | Flash pump supply |
FLTP1 | 7 | N/A | None | Flash test pads. These terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)]. | |
FLTP2 | 8 |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
VCC | 17 | 1.2-V Power | N/A | None | 1.2-V Core supply |
VCC | 29 | ||||
VCC | 45 | ||||
VCC | 48 | ||||
VCC | 49 | ||||
VCC | 57 | ||||
VCC | 87 | ||||
VCC | 101 | ||||
VCC | 114 | ||||
VCC | 123 | ||||
VCC | 137 | ||||
VCC | 143 |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
VCCIO | 10 | 3.3-V Power | N/A | None | 3.3-V Operating supply for I/Os |
VCCIO | 26 | ||||
VCCIO | 42 | ||||
VCCIO | 104 | ||||
VCCIO | 120 | ||||
VCCIO | 136 |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 144 PGE | ||||
VSS | 11 | Ground | N/A | None | Ground reference |
VSS | 21 | ||||
VSS | 27 | ||||
VSS | 28 | ||||
VSS | 43 | ||||
VSS | 44 | ||||
VSS | 47 | ||||
VSS | 50 | ||||
VSS | 56 | ||||
VSS | 88 | ||||
VSS | 102 | ||||
VSS | 103 | ||||
VSS | 115 | ||||
VSS | 121 | ||||
VSS | 122 | ||||
VSS | 135 | ||||
VSS | 138 | ||||
VSS | 144 |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
ADREFHI(1) | V15 | Input | N/A | None | ADC high reference supply |
ADREFLO(1) | V16 | Input | ADC low reference supply | ||
VCCAD(1) | W15 | Power | Operating supply for ADC | ||
VSSAD | V19 | Ground | N/A | None | ADC supply power |
VSSAD | W16 | ||||
VSSAD | W18 | ||||
VSSAD | W19 | ||||
AD1EVT | N19 | I/O | Pulldown | Programmable, 20 µA | ADC1 event trigger input, or GPIO |
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS | V10 | I/O | Pullup | Programmable, 20 µA | ADC2 event trigger input, or GPIO |
AD1IN[0] | W14 | Input | N/A | None | ADC1 analog input |
AD1IN[1] | V17 | ||||
AD1IN[2] | V18 | ||||
AD1IN[3] | T17 | ||||
AD1IN[4] | U18 | ||||
AD1IN[5] | R17 | ||||
AD1IN[6] | T19 | ||||
AD1IN[7] | V14 | ||||
AD1IN[8] / AD2IN[8] | P18 | Input | N/A | None | ADC1/ADC2 shared analog inputs |
AD1IN[9] / AD2IN[9] | W17 | ||||
AD1IN[10] / AD2IN[10] | U17 | ||||
AD1IN[11] / AD2IN[11] | U19 | ||||
AD1IN[12] / AD2IN[12] | T16 | ||||
AD1IN[13] / AD2IN[13] | T18 | ||||
AD1IN[14] / AD2IN[14] | R18 | ||||
AD1IN[15] / AD2IN[15] | P19 | ||||
AD1IN[16] / AD2IN[0] | V13 | ||||
AD1IN[17] / AD2IN[1] | U13 | ||||
AD1IN[18] / AD2IN[2] | U14 | ||||
AD1IN[19] / AD2IN[3] | U16 | ||||
AD1IN[20] / AD2IN[4] | U15 | ||||
AD1IN[21] / AD2IN[5] | T15 | ||||
AD1IN[22] / AD2IN[6] | R19 | ||||
AD1IN[23] / AD2IN[7] | R16 |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
CAN1RX | B10 | I/O | Pullup | Programmable, 20 µA | CAN1 receive, or GPIO |
CAN1TX | A10 | CAN1 transmit, or GPIO | |||
CAN2RX | H1 | CAN2 receive, or GPIO | |||
CAN2TX | H2 | CAN2 transmit, or GPIO | |||
CAN3RX | M19 | CAN3 receive, or GPIO | |||
CAN3TX | M18 | CAN3 transmit, or GPIO |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
LINRX | A7 | I/O | Pullup | Programmable, 20 µA | LIN receive, or GPIO |
LINTX | B7 | LIN transmit, or GPIO |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
N2HET1[6]/SCIRX | W3 | I/O | Pulldown | Programmable, 20 µA | SCI receive, or GPIO |
N2HET1[13]/SCITX | N2 | SCI transmit, or GPIO |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] | B2 | I/O | Pullup | Programmable, 20 µA | I2C serial data, or GPIO |
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] | C3 | I2C serial clock, or GPIO |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
SPI2CLK | E2 | I/O | Pullup | Programmable, 20 µA | SPI2 clock, or GPIO |
SPI2NCS[0] | N3 | SPI2 chip select, or GPIO | |||
SPI2NENA/SPI2NCS[1] | D3 | SPI2 chip select, or GPIO | |||
SPI2NENA/SPI2NCS[1] | D3 | SPI2 enable, or GPIO | |||
SPI2SIMO[0] | D1 | SPI2 slave-input master-output, or GPIO | |||
SPI2SOMI[0] | D2 | SPI2 slave-output master-input, or GPIO | |||
N2HET1[0]/SPI4CLK | K18 | I/O | Pulldown | Programmable, 20 µA | SPI4 clock, or GPIO |
N2HET1[3]/SPI4NCS[0]/N2HET2[10] | U1 | SPI4 chip select, or GPIO | |||
N2HET1[1]/SPI4NENA/N2HET2[8] | V2 | SPI4 enable, or GPIO | |||
N2HET1[2]/SPI4SIMO[0] | W5 | SPI4 slave-input master-output, or GPIO | |||
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] | V6 | SPI4 slave-output master-input, or GPIO |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
MIBSPI1CLK | F18 | I/O | Pullup | Programmable, 20 µA | MibSPI1 clock, or GPIO |
MIBSPI1NCS[0]/MIBSPI1SOMI[1] | R2 | MibSPI1 chip select, or GPIO | |||
MIBSPI1NCS[1]/N2HET1[17] | F3 | ||||
MIBSPI1NCS[2]/N2HET1[19] | G3 | ||||
MIBSPI1NCS[3]/N2HET1[21] | J3 | ||||
N2HET1[15]/MIBSPI1NCS[4] | N1 | Pulldown | Programmable, 20 µA | MibSPI1 chip select, or GPIO | |
N2HET1[24]/MIBSPI1NCS[5] | P1 | ||||
MIBSPI1NENA/N2HET1[23] | G19 | Pullup | Programmable, 20 µA | MibSPI1 enable, or GPIO | |
MIBSPI1SIMO[0] | F19 | MibSPI1 slave-in master-out, or GPIO | |||
N2HET1[8]/MIBSPI1SIMO[1] | E18 | Pulldown | Programmable, 20 µA | MibSPI1 slave-in master-out, or GPIO | |
MIBSPI1SOMI[0] | G18 | Pullup | Programmable, 20 µA | MibSPI1 slave-out master-in, or GPIO | |
MIBSPI1NCS[0]/MIBSPI1SOMI[1] | R2 | ||||
MIBSPI3CLK | V9 | I/O | Pullup | Programmable, 20 µA | MibSPI3 clock, or GPIO |
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS | V10 | MibSPI3 chip select, or GPIO | |||
MIBSPI3NCS[1]/N2HET1[25]/MDCLK | V5 | ||||
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] | B2 | ||||
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] | C3 | ||||
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] | E3 | Pulldown | Programmable, 20 µA | MibSPI3 chip select, or GPIO | |
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] | W9 | Pullup | Programmable, 20 µA | MibSPI3 chip select, or GPIO | |
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] | W9 | MibSPI3 enable, or GPIO | |||
MIBSPI3SIMO[0] | W8 | MibSPI3 slave-in master-out, or GPIO | |||
MIBSPI3SOMI[0] | V8 | MibSPI3 slave-out master-in, or GPIO | |||
MIBSPI5CLK/DMM_DATA[4] | H19 | I/O | Pullup | Programmable, 20 µA | MibSPI5 clock, or GPIO |
MIBSPI5NCS[0]/DMM_DATA[5] | E19 | MibSPI5 chip select, or GPIO | |||
MIBSPI5NCS[1]/DMM_DATA[6] | B6 | ||||
MIBSPI5NCS[2]/DMM_DATA[2] | W6 | ||||
MIBSPI5NCS[3]/DMM_DATA[3] | T12 | ||||
MIBSPI5NENA/DMM_DATA[7] | H18 | MibSPI5 enable, or GPIO | |||
MIBSPI5SIMO[0]/DMM_DATA[8] | J19 | MibSPI5 slave-in master-out, or GPIO | |||
MIBSPI5SIMO[1]/DMM_DATA[9] | E16 | ||||
MIBSPI5SIMO[2]/DMM_DATA[10] | H17 | ||||
MIBSPI5SIMO[3]/DMM_DATA[11] | G17 | ||||
MIBSPI5SOMI[0]/DMM_DATA[12] | J18 | ||||
MIBSPI5SOMI[1]/DMM_DATA[13] | E17 | ||||
MIBSPI5SOMI[2]/DMM_DATA[14] | H16 | ||||
MIBSPI5SOMI[3]/DMM_DATA[15] | G16 |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
EMIF_CKE | L3 | Output | Pulldown | None | EMIF Clock Enable |
EMIF_CLK | K3 | I/O | None | EMIF clock. This is an output signal in functional mode. It is gated off by default, so that the signal is tri-stated. PINMUX29[8] must be cleared to enable this output. | |
ETMDATA[13]/EMIF_nOE | E12 | Pulldown | None | EMIF Output Enable | |
EMIF_nWAIT | P3 | I/O | Pullup | Fixed 20-µA Pullup |
EMIF Extended Wait Signal |
EMIF_nWE | D17 | Output | Pullup | None | EMIF Write Enable. |
EMIF_nCAS | R4 | Output | EMIF column address strobe | ||
EMIF_nRAS | R3 | Output | EMIF row address strobe | ||
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] | N17 | Output | Pulldown | EMIF chip select, SDRAM | |
EMIF_nCS[2] | L17 | Output | Pullup | EMIF chip selects, asynchronous This applies to chip selects 2, 3, and 4 |
|
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] | K17 | Output | Pulldown | ||
EMIF_nCS[4]/RTP_DATA[7] | M17 | Output | Pullup | ||
ETMDATA[15]/EMIF_nDQM[0] | E10 | Output | Pulldown | EMIF Data Mask or Write Strobe. Data mask for SDRAM devices, write strobe for connected asynchronous devices. |
|
ETMDATA[14]/EMIF_nDQM[1] | E11 | Output | |||
ETMDATA[12]/EMIF_BA[0] | E13 | Output | EMIF bank address or address line | ||
EMIF_BA[1]/N2HET2[5] | D16 | Output | EMIF bank address or address line | ||
EMIF_ADDR[0]/N2HET2[1] | D4 | Output | EMIF address | ||
EMIF_ADDR[1]/N2HET2[3] | D5 | Output | |||
ETMDATA[11]/EMIF_ADDR[2] | E6 | Output | |||
ETMDATA[10]/EMIF_ADDR[3] | E7 | Output | |||
ETMDATA[9]/EMIF_ADDR[4] | E8 | Output | |||
ETMDATA[8]/EMIF_ADDR[5] | E9 | Output | |||
EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] | C4 | Output | |||
EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] | C5 | Output | |||
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] | C6 | Output | |||
EMIF_ADDR[9]/RTP_DATA[10] | C7 | Output | |||
EMIF_ADDR[10]/RTP_DATA[9] | C8 | Output | |||
EMIF_ADDR[11]/RTP_DATA[8] | C9 | Output | |||
EMIF_ADDR[12]/RTP_DATA[6] | C10 | Output | |||
EMIF_ADDR[13]/RTP_DATA[5] | C11 | Output | |||
EMIF_ADDR[14]/RTP_DATA[4] | C12 | Output | |||
EMIF_ADDR[15]/RTP_DATA[3] | C13 | Output | |||
EMIF_ADDR[16]/RTP_DATA[2] | D14 | Output | |||
EMIF_ADDR[17]/RTP_DATA[1] | C14 | Output | Pulldown | ||
EMIF_ADDR[18]/RTP_DATA[0] | D15 | Output | |||
EMIF_ADDR[19]/RTP_nENA | C15 | Output | |||
EMIF_ADDR[20]/RTP_nSYNC | C16 | Output | |||
EMIF_ADDR[21]/RTP_CLK | C17 | Output | |||
ETMDATA[16]/EMIF_DATA[0] | K15 | I/O | Pulldown | Fixed 20-µA Pullup |
EMIF Data |
ETMDATA[17]/EMIF_DATA[1] | L15 | I/O | |||
ETMDATA[18]/EMIF_DATA[2] | M15 | I/O | |||
ETMDATA[19]/EMIF_DATA[3] | N15 | I/O | |||
ETMDATA[20]/EMIF_DATA[4] | E5 | I/O | |||
ETMDATA[21]/EMIF_DATA[5] | F5 | I/O | |||
ETMDATA[22]/EMIF_DATA[6] | G5 | I/O | |||
ETMDATA[23]/EMIF_DATA[7] | K5 | I/O | |||
ETMDATA[24]/EMIF_DATA[8] | L5 | I/O | |||
ETMDATA[25]/EMIF_DATA[9] | M5 | I/O | |||
ETMDATA[26]/EMIF_DATA[10] | N5 | I/O | |||
ETMDATA[27]/EMIF_DATA[11] | P5 | I/O | |||
ETMDATA[28]/EMIF_DATA[12] | R5 | I/O | |||
ETMDATA[29]/EMIF_DATA[13] | R6 | I/O | |||
ETMDATA[30]/EMIF_DATA[14] | R7 | I/O | |||
ETMDATA[31]/EMIF_DATA[15] | R8 | I/O |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
ETMTRACECLKIN/EXTCLKIN2 | R9 | Input | Pulldown | Fixed 20-µA Pullup |
ETM Trace Clock Input |
ETMTRACECLKOUT | R10 | Output | Pulldown | None | ETM Trace Clock Output |
ETMTRACECTL | R11 | ETM trace control | |||
ETMDATA[0] | R12 | ETM data | |||
ETMDATA[1] | R13 | ||||
ETMDATA[2] | J15 | ||||
ETMDATA[3] | H15 | ||||
ETMDATA[4] | G15 | ||||
ETMDATA[5] | F15 | ||||
ETMDATA[6] | E15 | ||||
ETMDATA[7] | E14 | ||||
ETMDATA[8]/EMIF_ADDR[5] | E9 | ||||
ETMDATA[9]/EMIF_ADDR[4] | E8 | ||||
ETMDATA[10]/EMIF_ADDR[3] | E7 | ||||
ETMDATA[11]/EMIF_ADDR[2] | E6 | ||||
ETMDATA[12]/EMIF_BA[0] | E13 | ||||
ETMDATA[13]/EMIF_nOE | E12 | ||||
ETMDATA[14]/EMIF_nDQM[1] | E11 | ||||
ETMDATA[15]/EMIF_nDQM[0] | E10 | ||||
ETMDATA[16]/EMIF_DATA[0] | K15 | ||||
ETMDATA[17]/EMIF_DATA[1] | L15 | ||||
ETMDATA[18]/EMIF_DATA[2] | M15 | ||||
ETMDATA[19]/EMIF_DATA[3] | N15 | ||||
ETMDATA[20]/EMIF_DATA[4] | E5 | ||||
ETMDATA[21]/EMIF_DATA[5] | F5 | ||||
ETMDATA[22]/EMIF_DATA[6] | G5 | ||||
ETMDATA[23]/EMIF_DATA[7] | K5 | ||||
ETMDATA[24]/EMIF_DATA[8] | L5 | ||||
ETMDATA[25]/EMIF_DATA[9] | M5 | ||||
ETMDATA[26]/EMIF_DATA[10] | N5 | ||||
ETMDATA[27]/EMIF_DATA[11] | P5 | ||||
ETMDATA[28]/EMIF_DATA[12] | R5 | ||||
ETMDATA[29]/EMIF_DATA[13] | R6 | ||||
ETMDATA[30]/EMIF_DATA[14] | R7 | ||||
ETMDATA[31]/EMIF_DATA[15] | R8 |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
EMIF_ADDR[21]/RTP_CLK | C17 | I/O | Pulldown | Programmable, 20 µA | RTP packet clock, or GPIO |
EMIF_ADDR[19]/RTP_nENA | C15 | I/O | RTP packet handshake, or GPIO | ||
EMIF_ADDR[20]/RTP_nSYNC | C16 | I/O | RTP synchronization, or GPIO | ||
EMIF_ADDR[18]/RTP_DATA[0] | D15 | I/O | RTP packet data, or GPIO | ||
EMIF_ADDR[17]/RTP_DATA[1] | C14 | ||||
EMIF_ADDR[16]/RTP_DATA[2] | D14 | ||||
EMIF_ADDR[15]/RTP_DATA[3] | C13 | ||||
EMIF_ADDR[14]/RTP_DATA[4] | C12 | ||||
EMIF_ADDR[13]/RTP_DATA[5] | C11 | ||||
EMIF_ADDR[12]/RTP_DATA[6] | C10 | ||||
EMIF_nCS[4]/RTP_DATA[7] | M17 | Pullup | Programmable, 20 µA | ||
EMIF_ADDR[11]/RTP_DATA[8] | C9 | Pulldown | Programmable, 20 µA | ||
EMIF_ADDR[10]/RTP_DATA[9] | C8 | ||||
EMIF_ADDR[9]/RTP_DATA[10] | C7 | ||||
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] | C6 | ||||
EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] | C5 | ||||
EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] | C4 | ||||
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] | N17 | ||||
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] | K17 |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
DMM_CLK | F17 | I/O | Pullup | Programmable, 20 µA | DMM clock, or GPIO |
DMM_nENA | F16 | DMM handshake, or GPIO | |||
DMM_SYNC | J16 | DMM synchronization, or GPIO | |||
DMM_DATA[0] | L19 | DMM data, or GPIO | |||
DMM_DATA[1] | L18 | ||||
MIBSPI5NCS[2]/DMM_DATA[2] | W6 | ||||
MIBSPI5NCS[3]/DMM_DATA[3] | T12 | ||||
MIBSPI5CLK/DMM_DATA[4] | H19 | ||||
MIBSPI5NCS[0]/DMM_DATA[5] | E19 | ||||
MIBSPI5NCS[1]/DMM_DATA[6] | B6 | ||||
MIBSPI5NENA/DMM_DATA[7] | H18 | ||||
MIBSPI5SIMO[0]/DMM_DATA[8] | J19 | ||||
MIBSPI5SIMO[1]/DMM_DATA[9] | E16 | ||||
MIBSPI5SIMO[2]/DMM_DATA[10] | H17 | ||||
MIBSPI5SIMO[3]/DMM_DATA[11] | G17 | ||||
MIBSPI5SOMI[0]/DMM_DATA[12] | J18 | ||||
MIBSPI5SOMI[1]/DMM_DATA[13] | E17 | ||||
MIBSPI5SOMI[2]/DMM_DATA[14] | H16 | ||||
MIBSPI5SOMI[3]/DMM_DATA[15] | G16 |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
nPORRST | W7 | Input | Pulldown | Fixed 100-µA Pulldown |
Power-on reset, cold reset External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter. See Section 6.8. |
nRST | B17 | I/O | Pullup | Fixed 100-µA Pullup |
System reset, warm reset, bidirectional. The internal circuitry indicates any reset condition by driving nRST low. The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal. This terminal has a glitch filter. See Section 6.8. |
nERROR | B14 | I/O | Pulldown | Fixed 20-µA Pulldown |
ESM Error Signal Indicates error of high severity. See Section 6.18. |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
OSCIN | K1 | Input | N/A | None | From external crystal/resonator, or external clock input |
KELVIN_GND | L2 | Input | Kelvin ground for oscillator | ||
OSCOUT | L1 | Output | To external crystal/resonator | ||
ECLK | A12 | I/O | Pulldown | Programmable, 20 µA | External prescaled clock output, or GIO. |
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS | B5 | Input | Pulldown | Fixed 20-µA Pulldown |
External clock input #1 |
ETMTRACECLKIN/EXTCLKIN2 | R9 | Input | External clock input #2 | ||
VCCPLL | P11 | 1.2-V Power | N/A | None | Dedicated core supply for PLLs |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
VCCP | F8 | 3.3-V Power | N/A | None | Flash pump supply |
FLTP1 | J5 | – | N/A | None | Flash test pads. These terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)]. |
FLTP2 | H5 |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
NC | D6 | – | N/A | None | No Connects. These balls are not connected to any internal logic and can be connected to the PCB ground without affecting the functionality of the device. |
NC | D7 | – | N/A | None | |
NC | D8 | – | N/A | None | |
NC | D9 | – | N/A | None | |
NC | D10 | – | N/A | None | |
NC | D11 | – | N/A | None | |
NC | D12 | – | N/A | None | |
NC | D13 | – | N/A | None | |
NC | E4 | – | N/A | None | |
NC | F4 | – | N/A | None | |
NC | G4 | – | N/A | None | |
NC | K4 | – | N/A | None | |
NC | K16 | – | N/A | None | |
NC | L4 | – | N/A | None | |
NC | L16 | – | N/A | None | |
NC | M4 | – | N/A | None | |
NC | M16 | – | N/A | None | |
NC | N4 | – | N/A | None | |
NC | N16 | – | N/A | None | |
NC | N18 | – | N/A | None | |
NC | P4 | – | N/A | None | |
NC | P15 | – | N/A | None | |
NC | P16 | – | N/A | None | |
NC | P17 | – | N/A | None | |
NC | R1 | – | N/A | None | |
NC | R14 | – | N/A | None | |
NC | R15 | – | N/A | None | |
NC | T2 | – | N/A | None | |
NC | T3 | – | N/A | None | |
NC | T4 | – | N/A | None | |
NC | T5 | – | N/A | None | |
NC | T6 | – | N/A | None | |
NC | T7 | – | N/A | None | |
NC | T8 | – | N/A | None | |
NC | T9 | – | N/A | None | |
NC | T10 | – | N/A | None | |
NC | T11 | – | N/A | None | |
NC | T13 | – | N/A | None | |
NC | T14 | – | N/A | None | |
NC | U3 | – | N/A | None | |
NC | U4 | – | N/A | None | |
NC | U5 | – | N/A | None | No Connects. These balls are not connected to any internal logic and can be connected to the PCB ground without affecting the functionality of the device. |
NC | U6 | – | N/A | None | |
NC | U7 | – | N/A | None | |
NC | U8 | – | N/A | None | |
NC | U9 | – | N/A | None | |
NC | U10 | – | N/A | None | |
NC | U11 | – | N/A | None | |
NC | U12 | – | N/A | None | |
NC | V3 | – | N/A | None | |
NC | V4 | – | N/A | None | |
NC | V11 | – | N/A | None | |
NC | V12 | – | N/A | None | |
NC | W4 | – | N/A | None | |
NC | W11 | – | N/A | None | |
NC | W12 | – | N/A | None | |
NC | W13 | – | N/A | None |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
VCC | F9 | 1.2-V Power | N/A | None | Core supply |
VCC | F10 | ||||
VCC | H10 | ||||
VCC | J14 | ||||
VCC | K6 | ||||
VCC | K8 | ||||
VCC | K12 | ||||
VCC | K14 | ||||
VCC | L6 | ||||
VCC | M10 | ||||
VCC | P10 |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
VCCIO | F6 | 3.3-V Power | N/A | None | Operating supply for I/Os |
VCCIO | F7 | ||||
VCCIO | F11 | ||||
VCCIO | F12 | ||||
VCCIO | F13 | ||||
VCCIO | F14 | ||||
VCCIO | G6 | ||||
VCCIO | G14 | ||||
VCCIO | H6 | ||||
VCCIO | H14 | ||||
VCCIO | J6 | ||||
VCCIO | L14 | ||||
VCCIO | M6 | ||||
VCCIO | M14 | ||||
VCCIO | N6 | ||||
VCCIO | N14 | ||||
VCCIO | P6 | ||||
VCCIO | P7 | ||||
VCCIO | P8 | ||||
VCCIO | P9 | ||||
VCCIO | P12 | ||||
VCCIO | P13 | ||||
VCCIO | P14 |
TERMINAL | SIGNAL TYPE |
RESET PULL STATE |
PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 337 ZWT | ||||
VSS | A1 | Ground | N/A | None | Ground reference |
VSS | A2 | ||||
VSS | A18 | ||||
VSS | A19 | ||||
VSS | B1 | ||||
VSS | B19 | ||||
VSS | H8 | ||||
VSS | H9 | ||||
VSS | H11 | ||||
VSS | H12 | ||||
VSS | J8 | ||||
VSS | J9 | ||||
VSS | J10 | ||||
VSS | J11 | ||||
VSS | J12 | ||||
VSS | K9 | ||||
VSS | K10 | ||||
VSS | K11 | ||||
VSS | L8 | ||||
VSS | L9 | ||||
VSS | L10 | ||||
VSS | L11 | ||||
VSS | L12 | ||||
VSS | M8 | ||||
VSS | M9 | ||||
VSS | M11 | ||||
VSS | M12 | ||||
VSS | V1 | ||||
VSS | W1 | ||||
VSS | W2 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Supply voltage | VCC(2) | –0.3 | 1.43 | V | |
VCCIO, VCCP(2) | –0.3 | 4.6 | |||
VCCAD | –0.3 | 6.25 | |||
Input voltage | All input pins | –0.3 | 4.6 | V | |
ADC input pins | –0.3 | 6.25 | |||
Input clamp current | IIK (VI < 0 or VI > VCCIO) All pins, except AD1IN[23:0] and AD2IN[15:0] |
–20 | 20 | mA | |
IIK (VI < 0 or VI > VCCAD) AD1IN[23:0] and AD2IN[15:0] |
–10 | 10 | |||
Total | –40 | 40 | mA | ||
Operating free-air temperature, TA: | –40 | 125 | °C | ||
Operating junction temperature, TJ: | –40 | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
VESD | Electrostatic discharge (ESD) performance: | Human body model (HBM), per AEC Q100-002(1) | ±2 | kV | |
Charged device model (CDM), per AEC Q100-011 |
All pins | ±500 | V | ||
Corner pins on 144-pin PGE (1, 36, 37, 72, 73, 108, 109, 144) |
±750 | ||||
Corner balls on 337-ball ZWT (A1, A19, W1, W19) |
±750 |
NOMINAL CORE VOLTAGE (VCC) | JUNCTION TEMPERATURE (Tj) |
LIFETIME POH |
---|---|---|
1.2 | 105ºC | 100K |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Digital logic supply voltage (Core) | 1.14 | 1.2 | 1.32 | V | |
VCCPLL | PLL Supply Voltage | 1.14 | 1.2 | 1.32 | V | |
VCCIO | Digital logic supply voltage (I/O) | 3 | 3.3 | 3.6 | V | |
VCCAD | MibADC supply voltage | 3 | 3.3/5.0 | 5.25 | V | |
VCCP | Flash pump supply voltage | 3 | 3.3 | 3.6 | V | |
VSS | Digital logic supply ground | 0 | V | |||
VSSAD | MibADC supply ground | –0.1 | 0.1 | V | ||
VADREFHI | A-to-D high-voltage reference source | VSSAD | VCCAD | V | ||
VADREFLO | A-to-D low-voltage reference source | VSSAD | VCCAD | V | ||
VSLEW | Maximum positive slew rate for VCCIO, VCCAD and VCCP supplies | 1 | V/µs | |||
TA | Operating free-air temperature | -40 | 125 | °C | ||
TJ | Operating junction temperature(2) | -40 | 150 | °C |
PARAMETER | DESCRIPTION | CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
fHCLK | HCLK - System clock frequency | PGE | Pipeline mode enabled | 160 | MHz | |
Pipeline mode disabled | 50 | |||||
ZWT | Pipeline mode enabled | 180 | ||||
Pipeline mode disabled | 50 | |||||
fGCLK | GCLK - CPU clock frequency | fHCLK | MHz | |||
fVCLK | VCLK - Primary peripheral clock frequency | 100 | MHz | |||
fVCLK2 | VCLK2 - Secondary peripheral clock frequency | 100 | MHz | |||
fVCLK3 | VCLK3 - Secondary peripheral clock frequency | 100 | MHz | |||
fVCLKA1 | VCLKA1 - Primary asynchronous peripheral clock frequency | 100 | MHz | |||
fVCLKA2 | VCLKA2 - Secondary asynchronous peripheral clock frequency | 100 | MHz | |||
fVCLKA4 | VCLKA4 - Secondary asynchronous peripheral clock frequency | 50 | MHz | |||
fRTICLK | RTICLK - clock frequency | fVCLK | MHz |
As shown in Figure 5-1, the TCM RAM can support program and data fetches at full CPU speed without any address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined mode. The flash supports a maximum CPU clock speed of 160 MHz in pipelined mode for the PGE Package and 180 MHz for the ZWT package, with one address wait state and three data wait states.
The flash wrapper defaults to nonpipelined mode with zero address wait state and one random-read data wait state.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ICC, ICCPLL | VCC Digital supply current (operating mode) | fHCLK = 180 MHz (ZWT Package only) fVCLK = 90 MHz, Flash in pipelined mode, VCCmax |
220(3) | 440(1) | mA | ||
VCC Digital supply current (LBIST mode) | LBIST clock rate = 90 MHz (ZWT Package only) |
700(2)(4) | |||||
VCC Digital supply current (PBIST mode) | PBIST ROM clock frequency = 90 MHz (ZWT Package only) |
700(2)(4) | |||||
VCC Digital supply current (operating mode) | fHCLK = 160 MHz fVCLK = 80 MHz, Flash in pipelined mode, VCCmax |
200(3) | 420(1) | ||||
VCC Digital supply current (LBIST mode) | LBIST clock rate = 80 MHz | 665(2)(4) | |||||
VCC Digital supply current (PBIST mode) | PBIST ROM clock frequency = 80 MHz |
665(2)(4) | |||||
ICCIO | VCCIO supply current (operating mode) | No DC load, VCCmax | 10 | mA | |||
ICCAD | VCCAD supply current (operating mode) | Single ADC operational, VCCADmax | 15 | mA | |||
Both ADCs operational, VCCADmax | 30 | ||||||
IADREFHI | ADREFHI supply current (operating mode) | Single ADC operational, ADREFHImax | 3 | mA | |||
Both ADCs operational, ADREFHImax | 6 | ||||||
ICCP | VCCP pump supply current | Read from 1 bank and program or erase another bank, VCCPmax | 60 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Vhys | Input hysteresis | 180 | mV | ||||
VIL | Low-level input voltage | –0.3 | 0.8 | V | |||
VIH | High-level input voltage | 2 | VCCIO + 0.3 | V | |||
VOL | Low-level output voltage | IOL = IOLmax | 0.2 VCCIO | V | |||
IOL = 50 µA, standard output mode | 0.2 | ||||||
IOL = 50 µA, low-EMI output mode (see Section 5.13) | 0.2 VCCIO | ||||||
VOH | High-level output voltage | IOH = IOHmax | 0.8 VCCIO | V | |||
IOH = 50 µA, standard output mode | VCCIO – 0.3 | ||||||
IOH = 50 µA, low-EMI output mode (see Section 5.13) | 0.8 VCCIO | ||||||
IIK | Input clamp current (I/O pins) | VI < VSSIO - 0.3 or VI > VCCIO + 0.3 | –3.5 | 3.5 | mA | ||
II | Input current (I/O pins) | IIH Pulldown 20 µA | VI = VCCIO | 5 | 40 | µA | |
IIH Pulldown 100 µA | VI = VCCIO | 40 | 195 | ||||
IIL Pullup 20 µA | VI = VSS | –40 | –5 | ||||
IIL Pullup 100 µA | VI = VSS | –195 | –40 | ||||
All other pins | No pullup or pulldown | –1 | 1 | ||||
CI | Input capacitance | 2 | pF | ||||
CO | Output capacitance | 3 | pF |
Table 5-2 shows the thermal resistance characteristics for the QFP - PGE mechanical package.
Table 5-3 shows the thermal resistance characteristics for the BGA - ZWT mechanical package.
°C / W | ||
---|---|---|
RΘJA | Junction-to-free air thermal resistance, Still air using JEDEC 2S2P test board | 39 |
RΘJB | Junction-to-board thermal resistance | 26.3 |
RΘJC | Junction-to-case thermal resistance | 6.7 |
ΨJT | Junction-to-package top, Still air | 0.10 |
°C / W | ||
---|---|---|
RΘJA | Junction-to-free air thermal resistance, Still air (includes 5 × 5 thermal via cluster in 2s2p PCB connected to first ground plane) | 18.8 |
RΘJB | Junction-to-board thermal resistance | 14.1 |
RΘJC | Junction-to-case thermal resistance | 7.1 |
ΨJT | Junction-to-package top, Still air (includes 5 × 5 thermal via cluster in 2s2p PCB connected to first ground plane) | 0.33 |
LOW-LEVEL OUTPUT CURRENT, IOL for VI=VOLmax or HIGH-LEVEL OUTPUT CURRENT, IOH for VI=VOHmin |
SIGNALS |
---|---|
8 mA |
MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3], MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3], TMS, TDI, TDO, RTCK, SPI4CLK, SPI4SIMO, SPI4SOMI, nERROR, N2HET2[1], N2HET2[3], All EMIF Outputs and I/Os, All ETM Outputs |
4 mA |
MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK, nRST |
2 mA zero-dominant |
AD1EVT, CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX, DMM_CLK, DMM_DATA[0], DMM_DATA[1], DMM_nENA, DMM_SYNC, GIOA[0-7], GIOB[0-7], LINRX, LINTX, MIBSPI1NCS[0], MIBSPI1NCS[1-3], MIBSPI1NENA, MIBSPI3NCS[0-3], MIBSPI3NENA, MIBSPI5NCS[0-3], MIBSPI5NENA, N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7], N2HET2[8], N2HET2[9], N2HET2[10], N2HET2[11], N2HET2[12], N2HET2[13], N2HET2[14], N2HET2[15], N2HET2[16], N2HET2[18], SPI2NCS[0], SPI2NENA, SPI4NCS[0], SPI4NENA |
selectable 8 mA/2 mA |
ECLK, SPI2CLK, SPI2SIMO, SPI2SOMI The default output buffer drive strength is 8 mA for these signals. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
tpw | Input minimum pulse width | tc(VCLK) + 10(2) | ns |
PARAMETER | MIN | MAX | UNIT | |||
---|---|---|---|---|---|---|
Rise time, tr | 8 mA low EMI pins (see Table 5-4) |
CL = 15 pF | 2.5 | ns | ||
CL = 50 pF | 4 | |||||
CL = 100 pF | 7.2 | |||||
CL = 150 pF | 12.5 | |||||
Fall time, tf | CL = 15 pF | 2.5 | ||||
CL = 50 pF | 4 | |||||
CL = 100 pF | 7.2 | |||||
CL = 150 pF | 12.5 | |||||
Rise time, tr | 4 mA low EMI pins (see Table 5-4) |
CL = 15 pF | 5.6 | ns | ||
CL = 50 pF | 10.4 | |||||
CL = 100 pF | 16.8 | |||||
CL = 150 pF | 23.2 | |||||
Fall time, tf | CL = 15 pF | 5.6 | ||||
CL= 50 pF | 10.4 | |||||
CL = 100 pF | 16.8 | |||||
CL = 150 pF | 23.2 | |||||
Rise time, tr | 2 mA-z low EMI pins (see Table 5-4) |
CL = 15 pF | 8 | ns | ||
CL = 50 pF | 15 | |||||
CL = 100 pF | 23 | |||||
CL = 150 pF | 33 | |||||
Fall time, tf | CL = 15 pF | 8 | ||||
CL = 50 pF | 15 | |||||
CL = 100 pF | 23 | |||||
CL = 150 pF | 33 | |||||
Rise time, tr | Selectable 8 mA/2 mA-z pins (see Table 5-4) |
8 mA mode | CL = 15 pF | 2.5 | ns | |
CL = 50 pF | 4 | |||||
CL = 100 pF | 7.2 | |||||
CL = 150 pF | 12.5 | |||||
Fall time, tf | CL = 15 pF | 2.5 | ||||
CL = 50 pF | 4 | |||||
CL = 100 pF | 7.2 | |||||
CL = 150 pF | 12.5 | |||||
Rise time, tr | 2 mA-z mode | CL = 15 pF | 8 | ns | ||
CL = 50 pF | 15 | |||||
CL = 100 pF | 23 | |||||
CL = 150 pF | 33 | |||||
Fall time, tf | CL = 15 pF | 8 | ||||
CL = 50 pF | 15 | |||||
CL = 100 pF | 23 | |||||
CL = 150 pF | 33 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
td(parallel_out) | Delay between low-to-high, or high-to-low transition of general-purpose output signals that can be configured by an application in parallel, for example, all signals in a GIOA port, or all N2HET1 signals, and so forth. | 5 | ns |
The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of emissions from the pins which they drive. This is accomplished by adaptively controlling the impedance of the output buffer, and is particularly effective with capacitive loads.
This is not the default mode of operation of the low-EMI output buffers and must be enabled by setting the system module GPCR1 register for the desired module or signal, as shown in Table 5-9. The adaptive impedance control circuit monitors the DC bias point of the output signal. The buffer internally generates two reference levels, VREFLOW and VREFHIGH, which are set to approximately 10% and 90% of VCCIO, respectively.
Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then the impedance of the output buffer will increase to Hi-Z. A high degree of decoupling between the internal ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing, for example, the buffer is driving low on a resistive path to ground. Current loads on the buffer which try to pull the output voltage above VREFLOW will be opposed by the impedance of the output buffer so as to maintain the output voltage at or below VREFLOW.
Conversely, once the output buffer has driven the output to a high level, if the output voltage is above VREFHIGH then the impedance of the output buffer will again increase to Hi-Z. A high degree of decoupling between internal power bus ad output pin will occur with capacitive loads or any loads in which no current is flowing, for example, buffer is driving high on a resistive path to VCCIO. Current loads on the buffer which try to pull the output voltage below VREFHIGH will be opposed by the impedance of the buffer output so as to maintain the output voltage at or above VREFHIGH.
The bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance control mode cannot respond to high-frequency noise coupling into the power buses of the buffer. In this manner, internal bus noise approaching 20% peak-to-peak of VCCIO can be rejected.
Unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will allow a positive current load to pull the output voltage up to VCCIO + 0.6 V without opposition. Also, a negative current load will pull the output voltage down to VSSIO – 0.6 V without opposition. This is not an issue because the actual clamp current capability is always greater than the IOH / IOL specifications.
The low-EMI output buffers are automatically configured to be in the standard buffer mode when the device enters a low-power mode.
MODULE OR SIGNAL NAME | CONTROL REGISTER TO ENABLE LOW-EMI MODE |
---|---|
Module: MibSPI1 | GPREG1.0 |
Module: SPI2 | GPREG1.1 |
Module: MibSPI3 | GPREG1.2 |
Reserved | GPREG1.3 |
Module: MibSPI5 | GPREG1.4 |
Reserved | GPREG1.5 |
Module: EMIF | GPREG1.6 |
Module: ETM | GPREG1.7 |
Signal: TMS | GPREG1.8 |
Signal: TDI | GPREG1.9 |
Signal: TDO | GPREG1.10 |
Signal: RTCK | GPREG1.11 |
Signal: TEST | GPREG1.12 |
Signal: nERROR | GPREG1.13 |
Reserved | GPREG1.14 |
Module: RTP | GPREG1.15 |